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Interpretation of capacitance-voltage characteristics on silicon-on-insulator (SOI) capacitors
Solid-State Electronics Vol. 32. No. I, pp. 65-68, 1989 Printed
0038-I101/89 $3.00+ 0.00 Copyright 0 1989Pergamon Press plc
in Great Britain. All rights reserved
INTERPRETATION OF CAPACITANCE-VOLTAGE CHARACTERISTICS ON SILICON-ON-INSULATOR (SOI) CAPACITORS L. J. MCDAID, S. HALL and W. ECCLESTON Department of Electrical Engineering and Electronics, The University of Liverpool, Liverpool, L69 3BX, U.K. J. C. ALDERMAN Allen Clark Res. Centre (Plessey), Caswell, Towcester, Northants, NN12 8EQ, U.K. (Received
14 April 1988; in revisedform
11 July 1988)
Abstract-To predict the performance of SOI transistors, it is essential that material dimensions and parameters arc accurately known. It is demonstrated here that from a single high frequency capacitance-voltage (C-V) plot performed on an SOI capacitor, one can obtain the buried insulator and body (active layer) thickness. The results obtained from the method are verified by independent C-V measurements carried out on the same device. In the present case this technique is demonstrated using SIMOX material but applies equally well to other SO1 technologies. Because of the ease of fabrication of the capacitor such a measurement can be performed on starting material. The measurement strictly applies to the condition of a fully depleted body, but in the partially depleted case the thickness of the buried oxide can still be estimated.
NOTATION
total system capacitance gate oxide capacitance body capacitance accumulation capacitance at the body-buried oxide interface buried oxide capacitance silicon substrate capacitance doping level in the body doping level in the substrate charge on the gate accumulation charge at the body-buried oxide interface electronic charge thickness of the body thickness of the buried oxide , gate voltage depletion distance depletion in the substrate potential at the gate oxide-body interface accumulation layer potential interface permittivity of free space permittivity of the silicon regions permittivity of the oxide regions
elsewhere establish the above parameters involve current-voltage (I-V) measurements on 5 devices[5] or SEM cross-section. The former method a special test transistor which is difficult fabricate for small channel The latter method is complicated and destructive. On conventional MOS the high frequency extracting parameters such as oxide thickness, doping concentration and fixed oxide charge. It has already been shown[7-81 that the above technique together with low frequency estimate device parameters on semiconductor-insulator-semiconductor (SIS) structures. terminal high frequency performed on an SOI capacitor thickness of both the body and buried insulator. The values from this measurement verified by independent C-V’s performed
further tests, such as 1. INTRODUCTION
The restriction in the volume of silicon in the body region of an SOI transistor influences its operation regions. Several workers[l4] have the effect of this on device performance. It was found that in the case where the body was fully-depleted, device characteristics were dependent thickness of this region and also of the buried insulator. The techniques used
capacitor may be used for carrier lifetime[9]. starting
material, schematic cross-section capacitor is shown in Fig. 1. The buried insulator realised using SIMOX. N-type (100) 50 Qcm silicon wafers were implanted ions/cm2 at 200 keV and a subsequent annealing at 1250°C. The capacitor isolated with a gate area 200 by 200pm. The substrate
L. J. MCDAID
66
et
the substrate, at the gate oxide-body interface. Neglecting potentials dropped across inversion layers, 4, can be written as the sum of potentials dropped across the depletion region in the substrate, buried oxide, depletion region in the body and accumulation layer at the body-buried oxide interface. Hence 4, is given by:
@‘Nt 0s
w,
0
BURIED
Si
SJBkfATE
carrier type surrounded the body allowing electrical contact to that region. This contact was used only for independent C-V measurements and is otherwise left open-circuit. The C-V measurement was taken with a Hewlett-Packard 4162 impedance bridge at a frequency of 1 MHz. THEORY
(3)
For the condition where the depletion distance in the body is less than or equal to the body thickness we can write:
cofv, = Cord’s + @bwb. Differentation
AND RESULTS
We proceed with the theoretical derivation of the two-terminal system capacitance Cr for the case of an ideal SOI capacitor. This is done for the general case where depletion regions exist in both the body and substrate. Negative gate voltage caused depletion under the top gate oxide and accumulation at the body-buried oxide interface. (Note that the opposite is true for positive gate voltage: accumulation at the gate oxide-body interface and in the substrate with depletion at the body-buried oxide interface.) The accumulation layer is a result of the body being electrically isolated and hence the net charge in the body region is zero. The electrostatic effect of the accumulation layer is to cause depletion in the substrate. Hence for the condition where the depletion distance in the body is less than or equal to the body thickness we can write: N,K = %Wi,,
2EOE,+c&*
5
where tabis the buried oxide thickness, ,sois the permittivity of free space, Emis the relative permittivity of the silicon and .soXis the relative permittivity of the buried oxide. +acc is the surface potential associated with the electron accumulation at the body-buried oxide interface. (It can also be shown that eqn (3) can be arrived at by integrating Poisson’s equation across the structure.) The total system capacitance Cr is equal to the rate of change of gate charge with respect to gate voltage, hence differentiating eqn (2) we have:
OXIDE
Fig. 1. Section through the SOI-capacitor.
2. MEASUREMENT
Snbw2,
bb +
4s=2EE+r
(1)
where N, and Nb are the doping levels in the substrate and body respectively and W,, W, are the depletion distances in the substrate, body. From Gauss’s law the charge on the gate is given by
where C,,, is the capacitance of the gate oxide and Vg is the gate potential with respect to the substrate. The potential +s is the surface potential, with respect to
(5)
of eqn (5) with respect of I$, yields: dV a=l+gNbdwb dA
(6)
C,, -dK’
Substituting for W, in eqn (3), using eqn (l), and differentiating eqn (3) with respect to wb gives:
4%
9Niwts -4Ntibb + -‘Pbwb+ Wa.x
d=-+sos,N,
kEs
so&0X
dW,’
The total charge in the accumulation layer, Q,, the body-buried oxide interface, is given by:
(7) at
09
Q, = d%wt.. Therefore we can write:
W, W, = 4% -dwb
-
dQ,,
4Nb -
C,,Y
(9)
where C,, is the associated interface capacitance. By combining eqns (4), (6), (7) and (9) we arrive at the expression for the system capacitance:
(10) where C,,, is the buried oxide capacitance, Cb and C, are the capacitances associated with the depletion regions in the body and substrate respectively. For the condition where the body is fully depleted the structure becomes equivalent to a conventional MOS capacitor and in this regime the series combination of Cof, C,, C,, and Cob become the effective oxide
Characteristics of silicon-on-insulator capacitors capacitance. It can be shown that the above derivation, for positive gate voltage, yields the same expression as eqn (10) with C, tending to infinity and C, now referring to the gate oxide-body interface capacitance. Note that for capacitors with body thicknesses greater than the maximum depletion distance, eqn (10) yields the capacitance of the buried oxide (if the body doping is known) and so the two-terminal C-V is a useful measurement for all body thicknesses. Figure 2 shows the C-V plot for the two terminal bias arrangement. We identify and discuss three regions A, B and C. A. This is the minimum value of the system capacitance and corresponds to the series combination of gate oxide, fully depleted body, interface, buried oxide and substrate capacitances. The substrate is at its maximum depletion distance as defined by the doping level in that region. In this regime eqn (10) can be applied in its present form. B. This maximum value of system capacitance corresponds to the gate oxide, buried oxide and body-buried interface capacitances in series. Hence the right-hand side of eqn (10) reduces to the sum of the first, third and fourth terms. C. The capacitance at this point corresponds to the gate oxide, fully depleted body, body-buried oxide interface and buried oxide capacitances in series. In this case the right-hand side of eqn (10) becomes equal to the sum of the first four terms. In the present case the minimum value of capacitance associated with the body-buried oxide interface, Ca,, corresponds to the flatband condition at that interface. For a doping level of 5 x lOI cme3 in the body, this debye capacitance is found to be 80 pF. As this capacitance is in series with the system capacitance, whose maximum value is about 4.4 pF (see Fig. 2), good accuracy is still maintained by ignoring this quantity in regions A, B and C. The application of eqn (10) in regions B and C gives
67
directly the capacitance associated with the body and knowing the value of the gate oxide capacitance (from ellipsometry) the thickness of the buried oxide can then be estimated from region B. We note with reference to Fig. 2 that the shift in the C-V plot reflects the poor quality of the body-buried oxide interface and is due to the high level of fixed charge influencing that interface. In the present case the parameters of interest are found to be; buried oxide thickness, t,, = 3300 A, body thickness, t, = 2200 A. Due to the spatial distribution of charge in the body, when the body is fully depleted, there exists a charge centroid effect181which will tend to “smear” out the C-V plot. This effect will only be observed if the body region is fully depleted prior to inversion in the substrate. However in the present case, the body doping is about a factor of 10 higher than the substrate doping hence the centroid effect is not observed as the capacitance is at its minimum value just as the body bcomes fully depleted. The above dimensions were compared with those obtained from independent C-V measurements using the body contact as a third terminal (Fig. 1). Figure 3 is the C-V plot obtained between body and substrate. The maximum value of capacitance for this bias arrangement can be interpreted as that associated with the buried insulator particularly in the presence of oxide charge. The thickness of the buried oxide obtained from this value is 3370 A and is within 2% of that obtained from the proposed two-terminal measurement. The minimum value of capacitance, for positive gate voltage, indicates lateral depletion towards the annular contact surrounding the body. Interpretation of this value in terms of device geometry is meaningless as the effective area of the capacitor is reduced. Figure 4 is the C-V plot obtained between gate and substrate. In this case the body contact was grounded. The maximum value corresponds to the capacitance associated with the gate oxide. The
Cm=) C(Pf=J
5
5
F= 1Ml-k
Fs 1MH-r
t
t
t
(Cl
--1
(A)
J
-3
’
-2
’
-1
0
I
I
I
I
I
I
I
I
I
1
2
3
4
5
6
7
6
9
I
I
I
10 11 12 V IVoltrJ
Fig. 2. Two two-terminal C-V plot between gate and substrate.
e
-3
’
-2
’
-1
I, 0
1
I
I,,,,,,_
2
3
4
5
6
7
8 9 V(VokS)
Fig. 3. The C-V plot taken between the body and substrate.
L. J. MCDA~Det al.
68 C(PF)
F.
through the capacitor. Note that for the two-terminal C-V plot the impedance of the body region is of no consequence to the measurement as this region is open circuit.
1MHz
3. CONCLUSION
VPfOkS)
Fig. 4. The C-V plot taken between the gate and substrate with the body grounded.
equivalent circuit for this conditidn is the gate oxide capacitance in series with the capacitance associated with the depletion region in the body. However, this is only true up until the point when the body becomes fully depleted; indicated by (D) in Fig. 4. It can be shown that after this point the equivalent circuit includes the capacitance associated with the buried oxide, interface states at the body-buried oxide interface and depletion in the substrate. The substrate depletion distance, which is a function of the relative doping densities in the body and substrate and also of the body/buried oxide thicknesses, is determined by inversion beneath the gate oxide. Identifying the point of full depletion, (D) in Fig. 4 and calculating the thickness of the body gave 2100 A which is within 4.5% of that calculated by the two-terminal C-V. Note also from Fig. 4 that the C-V is smeared out prior to full depletion of the body. This is due to states within the band gap situated close to the buried oxide interface and at the interface. Also the high series resistance associated with the thin body region may contribute to this smearing[lO]. However, the effect of this on the measurements was overcome by monitoring the phase angle between the measuring (alternating) voltage and displacement current
A method has been demonstrated to measure nondestructively the electrical thickness of both the body and buried oxide of SO1 material. The method only requires the fabrication of a simple thin-film SOI capacitor and a subsequent routine, two-terminal high-frequency C-V measurement. A simple analysis then gives directly the body thickness. The thickness of the buried oxide can then be estimated (for either fully or partially depleted body), if the thickness of the gate oxide is known. It is important to note that non-uniformities in the doping levels in the capacitor do not affect the measurement as the analysis does not require these parameters. Acknowledgements-The authors wish to thank P. L. F. Hemment and K. Reeson of the University of Surrey for the SIMOX material. Thanks are also due to Mrs S. L. Patridge of GEC (Hirst) Research Laboratories. This work has been carried out with the support of the Alvey directorate. Finally, the authors would like to thank the Directors of the Plessey Company for permission to publish. REFERENCES
1. N. Sasaki and R. Togei, Solid-St. Electron. 22, 417 (1978). 2. E. R.. Worley, Solid-St. Electron. 23, 1107 (1980). 3. H. K. Lim and J. G. Fossum. IEEE Truns. Electron Dev. ED-30, (1983). 4. J. P. Colinge, IEEE Electron Dev. L&r. EDL-7, (1986). 5. J. Whitfield and S. Thomas, IEEE Hecfron Dev. Mt. EDC-7, (1986). 6. Nicollian and Brews, MOS #feral Oxide Semiconducfor) Physics and Technology. Wiley, New York (1982). I. K. Nagai, T. Sekigawa and Y. Hayashi, Solid-St. Electron. 28, 789 (1985).
8. F. T. Brady, S. S. Li and D. E. Burk, Appl. Phys. Lat. 52, (1988). 9. Hall, McDaid, Eccleston and Alderman. To be published. 10. J. D. Wiley and G. L. Miller, IEEE Trans. Electron Dev. ED-22, (1975).
0038-I101/89 $3.00+ 0.00 Copyright 0 1989Pergamon Press plc
in Great Britain. All rights reserved
INTERPRETATION OF CAPACITANCE-VOLTAGE CHARACTERISTICS ON SILICON-ON-INSULATOR (SOI) CAPACITORS L. J. MCDAID, S. HALL and W. ECCLESTON Department of Electrical Engineering and Electronics, The University of Liverpool, Liverpool, L69 3BX, U.K. J. C. ALDERMAN Allen Clark Res. Centre (Plessey), Caswell, Towcester, Northants, NN12 8EQ, U.K. (Received
14 April 1988; in revisedform
11 July 1988)
Abstract-To predict the performance of SOI transistors, it is essential that material dimensions and parameters arc accurately known. It is demonstrated here that from a single high frequency capacitance-voltage (C-V) plot performed on an SOI capacitor, one can obtain the buried insulator and body (active layer) thickness. The results obtained from the method are verified by independent C-V measurements carried out on the same device. In the present case this technique is demonstrated using SIMOX material but applies equally well to other SO1 technologies. Because of the ease of fabrication of the capacitor such a measurement can be performed on starting material. The measurement strictly applies to the condition of a fully depleted body, but in the partially depleted case the thickness of the buried oxide can still be estimated.
NOTATION
total system capacitance gate oxide capacitance body capacitance accumulation capacitance at the body-buried oxide interface buried oxide capacitance silicon substrate capacitance doping level in the body doping level in the substrate charge on the gate accumulation charge at the body-buried oxide interface electronic charge thickness of the body thickness of the buried oxide , gate voltage depletion distance depletion in the substrate potential at the gate oxide-body interface accumulation layer potential interface permittivity of free space permittivity of the silicon regions permittivity of the oxide regions
elsewhere establish the above parameters involve current-voltage (I-V) measurements on 5 devices[5] or SEM cross-section. The former method a special test transistor which is difficult fabricate for small channel The latter method is complicated and destructive. On conventional MOS the high frequency extracting parameters such as oxide thickness, doping concentration and fixed oxide charge. It has already been shown[7-81 that the above technique together with low frequency estimate device parameters on semiconductor-insulator-semiconductor (SIS) structures. terminal high frequency performed on an SOI capacitor thickness of both the body and buried insulator. The values from this measurement verified by independent C-V’s performed
further tests, such as 1. INTRODUCTION
The restriction in the volume of silicon in the body region of an SOI transistor influences its operation regions. Several workers[l4] have the effect of this on device performance. It was found that in the case where the body was fully-depleted, device characteristics were dependent thickness of this region and also of the buried insulator. The techniques used
capacitor may be used for carrier lifetime[9]. starting
material, schematic cross-section capacitor is shown in Fig. 1. The buried insulator realised using SIMOX. N-type (100) 50 Qcm silicon wafers were implanted ions/cm2 at 200 keV and a subsequent annealing at 1250°C. The capacitor isolated with a gate area 200 by 200pm. The substrate
L. J. MCDAID
66
et
the substrate, at the gate oxide-body interface. Neglecting potentials dropped across inversion layers, 4, can be written as the sum of potentials dropped across the depletion region in the substrate, buried oxide, depletion region in the body and accumulation layer at the body-buried oxide interface. Hence 4, is given by:
@‘Nt 0s
w,
0
BURIED
Si
SJBkfATE
carrier type surrounded the body allowing electrical contact to that region. This contact was used only for independent C-V measurements and is otherwise left open-circuit. The C-V measurement was taken with a Hewlett-Packard 4162 impedance bridge at a frequency of 1 MHz. THEORY
(3)
For the condition where the depletion distance in the body is less than or equal to the body thickness we can write:
cofv, = Cord’s + @bwb. Differentation
AND RESULTS
We proceed with the theoretical derivation of the two-terminal system capacitance Cr for the case of an ideal SOI capacitor. This is done for the general case where depletion regions exist in both the body and substrate. Negative gate voltage caused depletion under the top gate oxide and accumulation at the body-buried oxide interface. (Note that the opposite is true for positive gate voltage: accumulation at the gate oxide-body interface and in the substrate with depletion at the body-buried oxide interface.) The accumulation layer is a result of the body being electrically isolated and hence the net charge in the body region is zero. The electrostatic effect of the accumulation layer is to cause depletion in the substrate. Hence for the condition where the depletion distance in the body is less than or equal to the body thickness we can write: N,K = %Wi,,
2EOE,+c&*
5
where tabis the buried oxide thickness, ,sois the permittivity of free space, Emis the relative permittivity of the silicon and .soXis the relative permittivity of the buried oxide. +acc is the surface potential associated with the electron accumulation at the body-buried oxide interface. (It can also be shown that eqn (3) can be arrived at by integrating Poisson’s equation across the structure.) The total system capacitance Cr is equal to the rate of change of gate charge with respect to gate voltage, hence differentiating eqn (2) we have:
OXIDE
Fig. 1. Section through the SOI-capacitor.
2. MEASUREMENT
Snbw2,
bb +
4s=2EE+r
(1)
where N, and Nb are the doping levels in the substrate and body respectively and W,, W, are the depletion distances in the substrate, body. From Gauss’s law the charge on the gate is given by
where C,,, is the capacitance of the gate oxide and Vg is the gate potential with respect to the substrate. The potential +s is the surface potential, with respect to
(5)
of eqn (5) with respect of I$, yields: dV a=l+gNbdwb dA
(6)
C,, -dK’
Substituting for W, in eqn (3), using eqn (l), and differentiating eqn (3) with respect to wb gives:
4%
9Niwts -4Ntibb + -‘Pbwb+ Wa.x
d=-+sos,N,
kEs
so&0X
dW,’
The total charge in the accumulation layer, Q,, the body-buried oxide interface, is given by:
(7) at
09
Q, = d%wt.. Therefore we can write:
W, W, = 4% -dwb
-
dQ,,
4Nb -
C,,Y
(9)
where C,, is the associated interface capacitance. By combining eqns (4), (6), (7) and (9) we arrive at the expression for the system capacitance:
(10) where C,,, is the buried oxide capacitance, Cb and C, are the capacitances associated with the depletion regions in the body and substrate respectively. For the condition where the body is fully depleted the structure becomes equivalent to a conventional MOS capacitor and in this regime the series combination of Cof, C,, C,, and Cob become the effective oxide
Characteristics of silicon-on-insulator capacitors capacitance. It can be shown that the above derivation, for positive gate voltage, yields the same expression as eqn (10) with C, tending to infinity and C, now referring to the gate oxide-body interface capacitance. Note that for capacitors with body thicknesses greater than the maximum depletion distance, eqn (10) yields the capacitance of the buried oxide (if the body doping is known) and so the two-terminal C-V is a useful measurement for all body thicknesses. Figure 2 shows the C-V plot for the two terminal bias arrangement. We identify and discuss three regions A, B and C. A. This is the minimum value of the system capacitance and corresponds to the series combination of gate oxide, fully depleted body, interface, buried oxide and substrate capacitances. The substrate is at its maximum depletion distance as defined by the doping level in that region. In this regime eqn (10) can be applied in its present form. B. This maximum value of system capacitance corresponds to the gate oxide, buried oxide and body-buried interface capacitances in series. Hence the right-hand side of eqn (10) reduces to the sum of the first, third and fourth terms. C. The capacitance at this point corresponds to the gate oxide, fully depleted body, body-buried oxide interface and buried oxide capacitances in series. In this case the right-hand side of eqn (10) becomes equal to the sum of the first four terms. In the present case the minimum value of capacitance associated with the body-buried oxide interface, Ca,, corresponds to the flatband condition at that interface. For a doping level of 5 x lOI cme3 in the body, this debye capacitance is found to be 80 pF. As this capacitance is in series with the system capacitance, whose maximum value is about 4.4 pF (see Fig. 2), good accuracy is still maintained by ignoring this quantity in regions A, B and C. The application of eqn (10) in regions B and C gives
67
directly the capacitance associated with the body and knowing the value of the gate oxide capacitance (from ellipsometry) the thickness of the buried oxide can then be estimated from region B. We note with reference to Fig. 2 that the shift in the C-V plot reflects the poor quality of the body-buried oxide interface and is due to the high level of fixed charge influencing that interface. In the present case the parameters of interest are found to be; buried oxide thickness, t,, = 3300 A, body thickness, t, = 2200 A. Due to the spatial distribution of charge in the body, when the body is fully depleted, there exists a charge centroid effect181which will tend to “smear” out the C-V plot. This effect will only be observed if the body region is fully depleted prior to inversion in the substrate. However in the present case, the body doping is about a factor of 10 higher than the substrate doping hence the centroid effect is not observed as the capacitance is at its minimum value just as the body bcomes fully depleted. The above dimensions were compared with those obtained from independent C-V measurements using the body contact as a third terminal (Fig. 1). Figure 3 is the C-V plot obtained between body and substrate. The maximum value of capacitance for this bias arrangement can be interpreted as that associated with the buried insulator particularly in the presence of oxide charge. The thickness of the buried oxide obtained from this value is 3370 A and is within 2% of that obtained from the proposed two-terminal measurement. The minimum value of capacitance, for positive gate voltage, indicates lateral depletion towards the annular contact surrounding the body. Interpretation of this value in terms of device geometry is meaningless as the effective area of the capacitor is reduced. Figure 4 is the C-V plot obtained between gate and substrate. In this case the body contact was grounded. The maximum value corresponds to the capacitance associated with the gate oxide. The
Cm=) C(Pf=J
5
5
F= 1Ml-k
Fs 1MH-r
t
t
t
(Cl
--1
(A)
J
-3
’
-2
’
-1
0
I
I
I
I
I
I
I
I
I
1
2
3
4
5
6
7
6
9
I
I
I
10 11 12 V IVoltrJ
Fig. 2. Two two-terminal C-V plot between gate and substrate.
e
-3
’
-2
’
-1
I, 0
1
I
I,,,,,,_
2
3
4
5
6
7
8 9 V(VokS)
Fig. 3. The C-V plot taken between the body and substrate.
L. J. MCDA~Det al.
68 C(PF)
F.
through the capacitor. Note that for the two-terminal C-V plot the impedance of the body region is of no consequence to the measurement as this region is open circuit.
1MHz
3. CONCLUSION
VPfOkS)
Fig. 4. The C-V plot taken between the gate and substrate with the body grounded.
equivalent circuit for this conditidn is the gate oxide capacitance in series with the capacitance associated with the depletion region in the body. However, this is only true up until the point when the body becomes fully depleted; indicated by (D) in Fig. 4. It can be shown that after this point the equivalent circuit includes the capacitance associated with the buried oxide, interface states at the body-buried oxide interface and depletion in the substrate. The substrate depletion distance, which is a function of the relative doping densities in the body and substrate and also of the body/buried oxide thicknesses, is determined by inversion beneath the gate oxide. Identifying the point of full depletion, (D) in Fig. 4 and calculating the thickness of the body gave 2100 A which is within 4.5% of that calculated by the two-terminal C-V. Note also from Fig. 4 that the C-V is smeared out prior to full depletion of the body. This is due to states within the band gap situated close to the buried oxide interface and at the interface. Also the high series resistance associated with the thin body region may contribute to this smearing[lO]. However, the effect of this on the measurements was overcome by monitoring the phase angle between the measuring (alternating) voltage and displacement current
A method has been demonstrated to measure nondestructively the electrical thickness of both the body and buried oxide of SO1 material. The method only requires the fabrication of a simple thin-film SOI capacitor and a subsequent routine, two-terminal high-frequency C-V measurement. A simple analysis then gives directly the body thickness. The thickness of the buried oxide can then be estimated (for either fully or partially depleted body), if the thickness of the gate oxide is known. It is important to note that non-uniformities in the doping levels in the capacitor do not affect the measurement as the analysis does not require these parameters. Acknowledgements-The authors wish to thank P. L. F. Hemment and K. Reeson of the University of Surrey for the SIMOX material. Thanks are also due to Mrs S. L. Patridge of GEC (Hirst) Research Laboratories. This work has been carried out with the support of the Alvey directorate. Finally, the authors would like to thank the Directors of the Plessey Company for permission to publish. REFERENCES
1. N. Sasaki and R. Togei, Solid-St. Electron. 22, 417 (1978). 2. E. R.. Worley, Solid-St. Electron. 23, 1107 (1980). 3. H. K. Lim and J. G. Fossum. IEEE Truns. Electron Dev. ED-30, (1983). 4. J. P. Colinge, IEEE Electron Dev. L&r. EDL-7, (1986). 5. J. Whitfield and S. Thomas, IEEE Hecfron Dev. Mt. EDC-7, (1986). 6. Nicollian and Brews, MOS #feral Oxide Semiconducfor) Physics and Technology. Wiley, New York (1982). I. K. Nagai, T. Sekigawa and Y. Hayashi, Solid-St. Electron. 28, 789 (1985).
8. F. T. Brady, S. S. Li and D. E. Burk, Appl. Phys. Lat. 52, (1988). 9. Hall, McDaid, Eccleston and Alderman. To be published. 10. J. D. Wiley and G. L. Miller, IEEE Trans. Electron Dev. ED-22, (1975).