- Email: [email protected]
Introduction to the Special Section on FPGAs Technology and Applications
Computers and Electrical Engineering 49 (2016) 67–68
Contents lists available at ScienceDirect
Computers and Electrical Engineering journal homepage: www.elsevier.com/locate/compeleceng
Editorial
Introduction to the Special Section on FPGAs Technology and Applications
This special issue of Computers and Electrical Engineering provides an insight into current research and development in aspects related to FPGAs Technology and Applications. It is the second one on this topic; the first one was published in May 2014. After a rigorous review process, four papers were accepted out of 17 submitted papers. In the paper entitled ‘‘FPGA Based Accelerated 3D Affine Transform for Real-time Image Processing Applications”, Mondal et al. present a parallel and pipelined architecture that implements a proposed Affine Transform (AT) algorithm. The aim is to accelerate the transform process and reduce the processing time of medical image registration. The architecture is mapped in Field-Programmable Gate Array (FPGA) for prototyping and verification. In the paper entitled ‘‘Optimized FPGA Based Continuous Wavelet Transform”, Qassim et al. address the problem of implementing continuous wavelet transform (CWT) arithmetic operations. The CWT computations were performed in Fourier space and implemented on FPGA following several optimization schemes. The proposed design was tested using EEG data and demonstrated to be suitable for extracting features from the event related potentials. In the paper entitled ‘‘Concurrent Hardware Architecture for Dual-Mode Audio Steganography Processor-based FPGA”, Shahadi et al. present a parallel hardware-architecture for dual-mode audio steganography (DMAS) based FPGA technology. The proposed DMAS reconfigures the same hardware blocks in both hiding and recovery modes to reduce the hardware requirements. Finally, in the paper entitled ‘‘Tree-based String Pattern Matching on FPGAs”, Erdem introduces a tree-based pattern matching (TPM) scheme that comprises a forest of Binary Search Tree (BST) data structures and an accommodating highthroughput multi-pipelined architecture for scalable string matching on hardware. The proposed scheme is implemented on a FPGA device achieving a throughput of 2.7 Gbps. It is our pleasure to express our sincere gratitude to all who contributed in any way to produce this Special Issue. In particular we would like to thank all the reviewers for their valuable time and effort in the review process, and to provide constructive comments to authors. We thank all authors who submitted their manuscripts and sharing their latest research results. We hope that you will find in this Special Issue a valuable source of information to your future research. Guest Editors René Cumplido Computer Science Department, INAOE, Mexico E-mail address: [email protected] Peter Athanas The Bradley Department of Electrical & Computer Engineering, Virginia Tech, USA E-mail address: [email protected] Eduardo de la Torre Center for Industrial Electronics, Technical University of Madrid, Spain E-mail address: [email protected]
http://dx.doi.org/10.1016/j.compeleceng.2015.12.021 0045-7906/Ó 2015 Published by Elsevier Ltd.
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Editorial / Computers and Electrical Engineering 49 (2016) 67–68
René Cumplido holds a BSc degree in Computer Systems from the Queretaro Institute of Technology, Mexico, a MSc in Electrical Engineering from the CINVESTAV, Mexico, and a PhD Electrical Engineering from Loughborough University, UK. Since 2002, he is a professor at the Computer Science Department at INAOE in Puebla, Mexico. His research interests are Reconfigurable Computing for DSP and Digital Communications, FPGA Technologies and Custom Architectures for Scientific Computing. He is co-founder and Chair of the ReConFig international conference and founder editor-in-chief of the International Journal of Reconfigurable Computing. He also serves as associate editor of several international journals.
Peter Athanas is a professor in the Bradley Department of Electrical and Computer Engineering at Virginia Tech. His research interests include high-performance embedded computing, configurable computing, software-defined radios, and signal processing. He received his BS degree in electrical engineering from The University of Toledo, his MS degree in electrical engineering from Rensselaer Polytechnic Institute, his Sc.M. degree in applied mathematics at Brown University, and a Ph.D. degree in electrical engineering from Brown University. His PhD work in 1988 focused on configurable computing architectures and compilers. Prior to academia, he also served as a senior design engineer in the Advanced Technologies Group at United Technologies Hamilton Standard in Windsor Locks, CT. He is currently director of the Virginia Tech Configurable Computing Laboratory and site director of the Center for High-Performance Reconfigurable Computing.
Eduardo de la Torre is an Associate Professor of Electronics since 2002 at the Center for Industrial Electronics of the Technical University of Madrid (UPM), Spain. He obtained his MSC and PhD degrees in Electrical Engineering from UPM in 1989 and 2000, respectively. His main expertise is in FPGA-based design and, in particular, on partial and dynamic reconfiguration of digital systems and emulation platforms for digital communications. He has been Program Co-Chair as well as Program Committee member of several international conferences on reconfigurable architectures, FPGA technology and VLSI design. He is also reviewer of several international journals.
Contents lists available at ScienceDirect
Computers and Electrical Engineering journal homepage: www.elsevier.com/locate/compeleceng
Editorial
Introduction to the Special Section on FPGAs Technology and Applications
This special issue of Computers and Electrical Engineering provides an insight into current research and development in aspects related to FPGAs Technology and Applications. It is the second one on this topic; the first one was published in May 2014. After a rigorous review process, four papers were accepted out of 17 submitted papers. In the paper entitled ‘‘FPGA Based Accelerated 3D Affine Transform for Real-time Image Processing Applications”, Mondal et al. present a parallel and pipelined architecture that implements a proposed Affine Transform (AT) algorithm. The aim is to accelerate the transform process and reduce the processing time of medical image registration. The architecture is mapped in Field-Programmable Gate Array (FPGA) for prototyping and verification. In the paper entitled ‘‘Optimized FPGA Based Continuous Wavelet Transform”, Qassim et al. address the problem of implementing continuous wavelet transform (CWT) arithmetic operations. The CWT computations were performed in Fourier space and implemented on FPGA following several optimization schemes. The proposed design was tested using EEG data and demonstrated to be suitable for extracting features from the event related potentials. In the paper entitled ‘‘Concurrent Hardware Architecture for Dual-Mode Audio Steganography Processor-based FPGA”, Shahadi et al. present a parallel hardware-architecture for dual-mode audio steganography (DMAS) based FPGA technology. The proposed DMAS reconfigures the same hardware blocks in both hiding and recovery modes to reduce the hardware requirements. Finally, in the paper entitled ‘‘Tree-based String Pattern Matching on FPGAs”, Erdem introduces a tree-based pattern matching (TPM) scheme that comprises a forest of Binary Search Tree (BST) data structures and an accommodating highthroughput multi-pipelined architecture for scalable string matching on hardware. The proposed scheme is implemented on a FPGA device achieving a throughput of 2.7 Gbps. It is our pleasure to express our sincere gratitude to all who contributed in any way to produce this Special Issue. In particular we would like to thank all the reviewers for their valuable time and effort in the review process, and to provide constructive comments to authors. We thank all authors who submitted their manuscripts and sharing their latest research results. We hope that you will find in this Special Issue a valuable source of information to your future research. Guest Editors René Cumplido Computer Science Department, INAOE, Mexico E-mail address: [email protected] Peter Athanas The Bradley Department of Electrical & Computer Engineering, Virginia Tech, USA E-mail address: [email protected] Eduardo de la Torre Center for Industrial Electronics, Technical University of Madrid, Spain E-mail address: [email protected]
http://dx.doi.org/10.1016/j.compeleceng.2015.12.021 0045-7906/Ó 2015 Published by Elsevier Ltd.
68
Editorial / Computers and Electrical Engineering 49 (2016) 67–68
René Cumplido holds a BSc degree in Computer Systems from the Queretaro Institute of Technology, Mexico, a MSc in Electrical Engineering from the CINVESTAV, Mexico, and a PhD Electrical Engineering from Loughborough University, UK. Since 2002, he is a professor at the Computer Science Department at INAOE in Puebla, Mexico. His research interests are Reconfigurable Computing for DSP and Digital Communications, FPGA Technologies and Custom Architectures for Scientific Computing. He is co-founder and Chair of the ReConFig international conference and founder editor-in-chief of the International Journal of Reconfigurable Computing. He also serves as associate editor of several international journals.
Peter Athanas is a professor in the Bradley Department of Electrical and Computer Engineering at Virginia Tech. His research interests include high-performance embedded computing, configurable computing, software-defined radios, and signal processing. He received his BS degree in electrical engineering from The University of Toledo, his MS degree in electrical engineering from Rensselaer Polytechnic Institute, his Sc.M. degree in applied mathematics at Brown University, and a Ph.D. degree in electrical engineering from Brown University. His PhD work in 1988 focused on configurable computing architectures and compilers. Prior to academia, he also served as a senior design engineer in the Advanced Technologies Group at United Technologies Hamilton Standard in Windsor Locks, CT. He is currently director of the Virginia Tech Configurable Computing Laboratory and site director of the Center for High-Performance Reconfigurable Computing.
Eduardo de la Torre is an Associate Professor of Electronics since 2002 at the Center for Industrial Electronics of the Technical University of Madrid (UPM), Spain. He obtained his MSC and PhD degrees in Electrical Engineering from UPM in 1989 and 2000, respectively. His main expertise is in FPGA-based design and, in particular, on partial and dynamic reconfiguration of digital systems and emulation platforms for digital communications. He has been Program Co-Chair as well as Program Committee member of several international conferences on reconfigurable architectures, FPGA technology and VLSI design. He is also reviewer of several international journals.