Investigation of the chip to photodetector coupler with subwavelength grating on SOI

Optics & Laser Technology 76 (2016) 79–84

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Investigation of the chip to photodetector coupler with subwavelength grating on SOI Hongqiang Li a,n, Beibei Cui a, Yu Liu a, Hongwei Liu a, Zanyun Zhang a,b, Cheng Zhang a, Chunxiao Tang a, Enbang Li a,c a

School of Electronics and Information Engineering, Tianjin Polytechnic University, Tianjin 300387, China Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China c School of Physics, Faculty of Engineering and Information Sciences, University of Wollongong, Wollongong, NSW 2522, Australia b

art ic l e i nf o

a b s t r a c t

Article history: Received 25 March 2015 Received in revised form 16 June 2015 Accepted 29 July 2015 Available online 7 August 2015

We report on two kinds of investigation of the chip to photodetector coupler (CTPC) with uniform and blazed subwavelength grating (SWG) on silicon-on-insulator (SOI) that were conducted for silicon-based hybrid photodetector integration in an arrayed waveguide grating demodulation integrated microsystem. The theoretical model is presented, 3D FDTD and BPM simulations are used to optimize the coupler design. InP/InGaAs photodetector and SOI wafer were integrated through benzocyclobutene bonding. An efficient high-power absorption for TE mode in a broad band is achieved. The power absorption efficiencies of uniform and blazed SWGs in silicon-based hybrid photodetector integration at 1550 nm reach 73% and 75%, respectively in the simulation and it reaches as high as 25% in the measurement when coupling the TE-polarized 1550 nm light. & 2015 Elsevier Ltd. All rights reserved.

Keywords: Chip to photodetector coupler Silicon-on-insulator Silicon-based hybrid photodetector integration

1. Introduction Photonic integration on a chip has many advantages, which include excellent performance, high reliability, economy of scale, and so on. Based on the trend in micro-electronics, silicon is becoming an important candidate because of its optical functionalities. To date, most silicon photonic devices and circuits are utilized on silicon-on-insulator (SOI) platforms. The large footprint and high price of the fiber Bragg grating (FBG) demodulation systems limit the promotion and application of the optical FBG sensing technology. The results of our previous works on the array waveguide grating (AWG) demodulation system, which is a new kind of optical fiber grating demodulation scheme, show its suitability for optoelectronic integration [1]. The system consists of an on-chip light source, MMI coupler, FBG array, 1
8 AWG [2], output grating couplers (GCs), and InP/InGaAs photodetector array as shown in Fig. 1(a). Among AWG output waveguides, GC has been used to diffract light from the SOI waveguide into the photodetector with a spin-coated benzocyclobutene (BCB) layer in the middle. Fig. 1(b) shows the schematic of a cross section of the silicon-based hybrid photodetector. In order to research the diffract light from the SOI waveguide n Correspondence to: School of Electronics and Information Engineering, Tianjin Polytechnic University, No. 399, Binshuixi Road, Xiqing District, Tianjin 300387, China. Fax: þ86 22 8395 5121. E-mail address: [email protected] (H. Li).

http://dx.doi.org/10.1016/j.optlastec.2015.07.024 0030-3992/& 2015 Elsevier Ltd. All rights reserved.

into the photodetector among AWG output waveguides on the array waveguide grating (AWG) demodulation system, we carried on the study of grating. In the efficient coupling of light into and out of the planar optical system, the grating used is a promising choice because of its small footprint and high coupling efficiency. Recently, waveguide GCs characterized by shallow-etched grooves [3,4], metallic lines [5], and slanted grooves [6] have been used for efficient coupling of optical fibers. However, the use of GCs to optically couple heterogeneous integration of III–V and silicon photonics is rarely reported. Shao [7] designed a T-shaped GC used in silicon-based hybrid photodetector integration. In the study, the power absorption efficiency reaches 70% at 1550 nm in TE mode, but a complicated craft technique was needed. Therefore, creating a simple process that efficiently couples light into and out of the planar optical system is a challenge. Moreover, a subwavelength grating (SWG) [8,9], rather than a conventional waveguide GC [10,11], is the promising choice because it provides an additional degree of freedom in the design of the coupler, enabling the fabrication in which the same photolithography mask and etching process used for SOI waveguides are utilized. In the present study, the investigation of the chip to photodetector coupler (CTPC) on a SOI platform with SWG is designed for silicon-based hybrid photodetector integration in an AWG demodulation integrated microsystem. We assume two types SWG of CTPC, namely, uniform SWG and blazed SWG. The coupler formed by an array of rectangular holes can be fabricated in a single step etched on a large-scale with a 193 nm ultraviolet laser lithography

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layer in the middle to achieve silicon-based hybrid photodetector integration. Fig. 2(b) presents the light diffracted from the SOI waveguide towards the III–V photodetector. The grating period could be calculated through the phase matching condition:

qλ = Λx (neff − ncladding sin (θ ))

Fig. 1. (a) AWG demodulation integrated microsystem based on SOI. (b) Coupling scheme of silicon-based hybrid photodetector integration.

using the standard CMOS technology. We describe a 3D model for the proposed CTPC. The simulation results indicate that these structures have a sufficient coupling efficiency and a better highpower absorption efficiency. The coupling efficiency refers to the coupling efficiency to BCB layer. The absorption efficiency refers to the coupling efficiency to photodetector. When we put the photodetector onto this grating coupler with a spin-coated BCB layer, the InGaAs active layer's absorption efficiency of photodetector is increased because of the reflection and antireflection effects of BCB layer and SiO2 layer. Compared with the previously reported grating couplers, (the two kinds of SWG on CTPC (uniform and blazed) have tolerances of 50 nm in etched depth when the etching depth changes from 70 nm to 120 nm and due to fabrication limitation, we choose 70 nm as the etch depth) the CTPC designed in the present study is highly compact and exhibits a rather large fabrication error tolerance and wider bandwidth of 80 nm (from 1510 nm to 1590 nm) in the silicon-based hybrid photodetector integration.

2. Chip to photodetector coupler design The 3D schematic of the proposed CTPC is shown in Fig. 2(a). The proposed CTPC is designed on a SOI platform with a 220 nm thick silicon layer (nSi ¼3.47) on a 2 μm thick oxide layer ( nSiO2 = 1. 45). CTPC consists of a tapered segment, which adjusts the cross section of the SOI wire waveguide and surface diffraction gratings with SWG. The diffraction grating is produced along the z axis with pitch Λz, and SWG is produced along the x axis with pitch Λx at each period of the diffraction grating. An InP/InGaAs photodetector is coupled with the CTPC with a spin-coated BCB

(1)

where λ is the center wavelength, neff is the effective index of the grating region with the square nanohole array, ncladding is the refractive index of the cladding material (ncladding ¼nBCB ¼ 1.54), θ is the angle of the output light to the surface normal of the SOI wafer, q is the diffraction order (set to 1 for the first-order diffraction), and Λz is the grating period along the beam propagation direction. The diffraction grating operates under TE polarized light. The SWGs along the x axis in each period of the diffraction grating appear like a homogenous medium with an effective refractive index. According to the effective medium theory (EMT), a composite medium comprising two different materials, which are interleaved at the subwavelength scale, can be approximated as a homogenous medium with an effective refractive index. The zeroth-order expressions for anisotropic refractive index are given by:

⎡ 1 − fy fy 1 =⎢ 2 + 2 TE ⎢ nhole n nSi ⎣

(

) ⎤⎥

1/2

⎥ ⎦

2 2 ⎤1/2 nTM = ⎡⎣ f y nhole + 1 − f y nSi ⎦

(

)

(2)

(3)

where nhole is the refractive index of the nanoholes (equal to 1.54), and nSi is the refractive index of the silicon slab (equal to 3.47). The SWGs of the square holes and Λx are smaller than the wavelength of the propagating light, allowing EMT at the zeroth-order to approximate the structure. The zeroth-order approximations are accurate only if the change in the electromagnetic field within a distance of Λx is sufficiently small along any arbitrary direction. With regard to the high detector efficiency of CTPC in siliconbased hybrid photodetector integration, the BCB bonding layer and SiO2 buffer layer were considered to have reflection and anti-reflection effects. The thicknesses of the SiO2 buffer and BCB bonding layers were formed as cavities through the reflection at the BCB/ InP and SiO2/Si substrate interfaces. The thickness of SiO2 layer of the SOI adheres to the following reflection condition [12]:

d SiO 2 ≈ (2b + 1)

λ 4nSiO 2

(4)

where nSiO2 is the refractive index of SiO2 (nSiO2 = 1. 45), and b is an integer. The thickness of the BCB layer, which should serve as an anti-reflection film to assist the light passing into the detector, is given by [12]:

Fig. 2. (a) 3D schematic illustration of proposed CTPC with SWG in lateral direction. (b) Diffracted light from the SOI waveguide towards the III–V photodetector.

H. Li et al. / Optics & Laser Technology 76 (2016) 79–84

dBCB ≈

cλ 2nBCB

(5)

81

a

3. Simulation characterization and measurement results 3.1. Taper simulation Simulation of CTPC was performed using two simulation methods. The tapered part of CTPC was simulated through BPM, and the surface diffraction grating with SWG part was simulated through 3D FDTD. The length of the taper required to create a transition with a negligible loss between the 450 nm wide silicon wire waveguide and grating (W¼10.8 μm) was 300 μm, determined through linear tapering. Fig. 3 shows the input waveguide with tapered part in the BPM simulation region. Part (a) displays the height-coded graph that shows the distribution of the electric field intensity along the propagation direction in the tapered part and input waveguide. The input mode is smoothly distributed across the cross section. Part (b) shows the contour map (x–z plane), 85% of which is from the input optical power, which is 0.71 dB in dB scale. The optical field from BPM simulation at the end of taper was used as the input field of the surface diffraction grating of the FDTD simulation tool.

b

3.2. The simulation of 2D uniform and blazed SWGs The surface diffraction grating with SWG and CTPC parts was simulated through 3D FDTD. FDTD simulation is a long process that depends on the size of the simulation domain. A small simulation domain was used to minimize the computation time. The structure of diffraction grating is periodical along the x axis, in which periodic boundary conditions were used. The size of simulation domain was reduced to one period, as illustrated in Fig. 2. A simple grating without subwavelength microstructures was designed as a reference structure. The fill factor fz and pitch of the reference grating were determined through 2D FDTD simulation in the x–z plane. The SWG is equivalent to the conventional GC when the TE mode propagation along z-axis with a pitch of Λz ¼0.68 μm and a fill factor of fz ¼0.6 are considered. The synthesis of 1D binary blazed GC that employed the design principle and method of 2D GC was used to design the 2D blazed SWG. First, a 1D binary blazed GC was designed. Every period in the 1D binary blazed GC was equally divided into M subperiods with a width of T ¼ Λz/M. The fzi of each subperiod fzi (i¼ 1, 2, 3, …, M) was defined as the ratio of pillar width to the square hole subperiod. The optimum M was set as 3 when the coupling efficiency and fabrication constraint was considered. From the 1D binary blazed GC, phase matching condition, and binary blazed GC equivalent approximation formula, Λz was determined to be

Fig. 4. (a) Relationship between coupling efficiency and wavelength from the waveguide to BCB for 2D uniform gratings. Inset: Schematic diagram showing shallow etched 1D GC and 2D uniform SWG with fill factor fz and fx. (b) Relationships between coupling efficiency and wavelength from the waveguide to BCB for blazed gratings. Inset: Schematic diagram showing shallow etched 1D GC and 2D blazed SWG with indicated fz and fx.

1.23 μm. Fill factors with z direction of the hole are fz1 ¼ 0.861, fz2 ¼ 0.492, and fz3 ¼ 0, and the width of the etched square hole, which were calculated using ai ¼ fi  T, are a1 ¼353 nm, a2 ¼202 nm, and a3 ¼0. The pitch of the grating in the lateral direction is assumed to be Λx r λ/max (neff), the diffraction in the x–z plane is not achieved. In this equation, λ is the free-space wavelength and max (neff) is the maximum effective index of the structure, which in this case is the

Fig. 3. (a) Height-coded intensity of electrical field. (b) Contour map (x–z plane) with optical power along propagation direction.

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effective index of the waveguide at fundamental TE mode (neff ¼2.89). When Λx ¼500 nm and under the condition of implementing the process with ultraviolet 193 nm laser lithography by standard CMOS technology, we obtained fx ¼0.6. The two kinds of SWG corresponding coupling efficiency to BCB versus wavelength are shown in Fig. 4(a) and (b). From Fig. 4(a) and (b), we found that the output coupling efficiency of the 2D uniform SWG and blazed SWG is 62% and 69% at 1550 nm, and the output coupling efficiency of the blazed SWG is better than the 2D uniform SWG in 3D simulation. The two kinds of SWG corresponding coupling efficiency to BCB versus wavelength are shown in Fig. 4(a) and (b). From the inset of Fig. 4(a) and (b), we can find that uniform SWG and blazed SWG have different structure, 2D uniform SWG optimized by the conventional uniform GC and consists of an array of uniform holes. 2D blazed SWG optimized by binary blazed GC and consists of an array of nonuniform holes. The use of the subwavelength grating in the x-direction instead of a conventional waveguide grating provides an additional degree of freedom in the design of the coupler, thus enabling fabrication using the same photolithography mask and etching process as used for the SOI waveguides. By analyzing the simulation results of the two kinds of grating coupler (2D uniform and blazed SWGs), we found that the output coupling efficiency of the 2D uniform SWG and blazed SWG is 62% and 69% at 1550 nm, and the output coupling efficiency of the blazed SWG is better than the 2D uniform SWG in 3D simulation.

a

b

3.3. The influence of grating length and the etching depth for grating Different grating lengths and etching depths have different effects on the grating, so we increased the research on these factors. The relationships between output coupling efficiency and grating length are shown in Fig. 5(a). From Fig. 5(a), we found that the coupling efficiency could reach 67% from the grating length of 20–40 μm, basically remain unchanged. The photosensitive area of the photodetector used in this study is a circle with a diameter of 55 μm. So, according to the wave curve and the results of the photosensitive area of the photodetector, a grating length of 25 μm is chosen. The optical field of the output grating calculated by the FDTD method is shown in inset of Fig. 5(a) when the length of the grating is 25 μm around 1550 nm. The two kinds of SWG on CTPC (uniform and blazed) have tolerances of 50 nm in etched depth, and the coupling efficiency is larger than 60% when the etching depth changes from 70 nm to 120 nm. Due to the fabrication limitation and the tolerances of grating in etched depth, we choose 70 nm as the etch depth as shown in Fig. 5(b). The 2D uniform and blazed SWGs structure model for 3D FDTD simulation is shown in inset of Fig. 5(b). Moreover, no obvious change of the coupling efficiency occurs when etch depth of the 2D blazed SWG varies from 200 nm to 220 nm, and the coupling efficiency is approximate 55%, which means that this structure also can realize a fully-etched grating structure and has a fabrication tolerance of 20 nm in etch depth. In addition, Table 1 shows the efficiency at each stage of grating coupler. From Fig. 5(a) and (b), we found that the different grating length and different etching depth have different effects on the grating. A grating length of 25 μm is chosen according to the wave curve and the results of the photosensitive area of the photodetector. We choose 70 nm as the etch depth due to the fabrication limitation and the tolerances of grating in etched depth. 3.4. The chip to photodetector coupler (CTPC) used in silicon-based hybrid photodetector integration In this section, we add the photodetector on the grating.

Fig. 5. (a) Relationships between output coupling efficiency and grating length. Inset: Optical field of the output grating. (The grating length is 25 μm and coupling efficiency approximately 69% at around 1550 nm.) (b) Relationships between coupling efficiency and etch depth. Inset: 2D uniform and blazed SWGs structure model for 3D FDTD simulation.

Table 1 Coupling efficiency at each stage of grating couplers. 2D uniform SWG Coupling efficiency (%)

2D blazed SWG

Coupling efficiency (%)

Taper Coupler SiO2 layer

Taper Coupler SiO2 layer

85 69 22

85 62 28

Throughout the chip to photodetector coupler (CTPC) simulation of silicon-based hybrid photodetector integration, we assumed that the thickness of both the top and the lower InP layers is 1 μm, and the thickness of the InGaAs absorbing layer is 2 μm. First, SiO2 buffer layer thickness is optimized in a BCB environment without a detector on top. The thickness of the bonding layer play important role in the optical performance of the device, so we increased numerical results about the relationship curve between the output coupling loss and the thickness of SiO2 buffer layer and BCB bonding layer. The thickness of the SiO2 buffer layer is chosen as 2 μm as shown in Fig. 6(a), which accords with the whole arrayed waveguide grating demodulation system with a standard SOI chip. Then the thickness of the BCB layer was optimized to determine the effect the thickness on the power absorption loss of the

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83

a

b

Fig. 8. The experimental environment (a) auto-align system and optical waveguide alignment. (b) Microscope photo of the uniform subwavelength grating (SWG) on the SOI chip. (c) The magnified microscope photo of the SWG. Fig. 6. The relationship curve (a) Relationships between the output coupling loss and the thickness of SiO2 buffer layer. (b) Relationships between the power absorption loss and the thickness of BCB bonding layer.

InP/InGaAs photodetector. Polymer bonding photodetector onto silicon-on-insulator (SOI) wafer has been realized with grating coupler. This grating can effectively couple out TE mode light around 1550 nm when covered with BCB. An InP/InGaAs photodetector is bonded onto the grating with a layer of spin-coated BCB in the middle. Because the thickness of BCB layer has much influence on the power absorption loss of InP/InGaAs photodetector, we need to optimize the thickness of BCB layer. The thickness of the BCB bonding layer is 440 nm as shown in Fig. 6(b). SiO2 buffer layer and BCB layer have reflection and antireflection effects on power absorption efficiency, so we choose the thickness of the SiO2 buffer layer and BCB layer as 2 um and 440 nm respectively, by optimization. The photodetector will be bonded onto this grating coupler with a spin-coated BCB layer in the middle. Fig. 7 shows the relationships between wavelength and power absorption efficiency for the 2D uniform and blazed SWGs when the light from the waveguide in to photodetector. The simulation results of light diffraction at 1550 nm for TE mode are shown in the inset of Fig. 7.

Fig. 7. Relationships between power absorption efficiency and wavelength for 2D uniform and blazed gratings. Inset: Simulation of light diffraction from SOI waveguide toward the InP/InGaAs photodetector at 1550 nm.

In the whole microsystem, the wavelength of source, MMI coupler, InP/InGaAs photodetector array are in 1500–1600 nm. And the center wavelength range of the output channel 1
8 AWG also in 1500–1600 nm. These results indicate that efficient high-power absorption of the InP/InGaAs photodetector can be obtained with a broad band. As a result of the reflection and antireflection effects of BCB layer and SiO2 layer, absorption efficiency of photodetector has increased in InGaAs active layer. The power absorption efficiencies of the investigated CTPC at 1550 nm for uniform and blazed SWGs reach 73% and 75%, respectively. 3.5. Measurement results. The SWG was fabricated in the institute of microelectronics (IME, Singapore) by electron beam exposure and response-coupled plasma technology [13–16]. All devices were fabricated on a 200 mm SOI wafer with a 220 nm thick Si guiding layer on top of a 2 mm buried SiO2 layer. Electron beam lithography (EBL) technology was used to achieve the lithography of the system. The experimental environment and photos of the uniform subwavelength grating (SWG) on the SOI chip are shown in Fig. 8. An auto-align system and optical waveguide alignment are used during testing. A LCD was connected to observe the devices on the SOI chip. In order to analysis the optical power of the uniform subwavelength grating (SWG), the optical spectra of the device is measured as follows. Light from a broadband amplified spontaneous emission source is launched by a polarization preserved single mode fiber and collected by a fiber at the output end, which is connected with the input of grating coupler. When the fiber is perfectly aligned, light can be efficiently coupled and split into the grating. From an infrared microscope with a camera which is connected with the output of grating coupler, we can observe the output of the SWG. Fig. 9 shows the measured fiber-to-fiber normalized optical power of the uniform subwavelength grating (SWG) on the SOI chip. Experimentally, we find (Fig. 9) the optical coupling efficiency as high as 25% in the measurement when coupling the TE-polarized 1550 nm light. The result demonstrates that we are able to design and fabricate the uniform subwavelength grating (SWG) on the SOI chip with predictable spectral response for a fiber Bragg grating demodulation microsystem. The uniform subwavelength grating was fabricated on SOI. As a material used in waveguide devices, SOI displays superiority. It is a well-known platform for microelectronics and optoelectronics.

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was 10.8 μm wide and 25 μm long. Efficient high-power absorption of CTPC at TE mode in a broad band was achieved. Coupling efficiency of 2D uniform SWG and blazed SWG at 1550 nm is 62% and 69%. The absorption efficiency reaches 73% and 75%, respectively. And the optical power reaches as high as 25% in the measurement. The simulation results and theoretical analysis showed that CTPC is useful for integrated optical circuits. The uniform subwavelength grating (SWG) was fabricated and the experimental results in line with the simulation results. Furthermore, it is not difficult to fabricate these gratings by the conventional CMOS technology, which will be useful for integrated optical circuits. The designed CTPC is a promising material for the siliconbased hybrid integration of photodetectors because of its high efficiency and compact structure.

Acknowledgments Fig. 9. The measured fiber-to-fiber normalized optical power of the uniform subwavelength grating (SWG) on the SOI chip.

Extremely small devices can be fabricated on SOI substrates because of the ultrahigh refractive index between Si and SiO2. All devices were fabricated on a 200 mm SOI wafer with a 220 nmthick Si guiding layer on top of a 2 mm-buried SiO2 layer. The refractive indices of the silicon layer and the buried oxide layer were 3.46 and 1.45, respectively. Electron beam lithography (EBL) was used to achieve the lithography of the system because ordinary lithography technology was not applicable in the silicon nanowire processing designed in this work. An approximately 110 nm-thick polymethylmethacrylate-AR-P679.04 photoresist with high resolution, high contrast, and high transmittance rate of visible light was spin-coated on the chip before the EBL exposure. After prebaking, Raith 150 EBL was used for exposure lithography. An Alcatel 601E plasma etching system was used to etch the device. The deepest etching depth of the system was greater than 600 μm, and etching uniformity was less than 72.5%. The conventional multi-step silicon etching rate ranged from 5 μm/min to 10 μm/min. During ICP etching, CHF3 and O2 were selected as the etching gases. To ensure a high-level etching rate and prevent the accumulation of SOI surface sediment during Si etching, the following parameters were set: etching source power, 600 W; bias power, 100 W; CHF3 flow, 100 scem; O2 flow, 10 scem; and pressure of etching reaction chamber, less than 0.1 Pa. Si etching was completed at 0.01 μm/ min. Moreover, helium was used to cool the etching reaction chamber. After 30 min, a 0.22 mm-thick Si layer was finished. The device manufacture was completed after cutting and end face polishing. The simulation results were obtained under a relatively ideal condition, but some contingency conditions and human factors influenced the experimental result. The results were also restricted by experimental equipment accuracy. Therefore, the actual test results were lower than the simulation results. Nevertheless, the experimental results agreed with the simulation results. The result demonstrates that a SWG was designed and fabricated on a SOI chip with predictable spectral response for a fiber Bragg grating demodulation microsystem.

4. Conclusion In this study, we proposed two kinds of SWG on CTPC (uniform and blazed) for silicon-based hybrid photodetector integration in an AWG demodulation integrated microsystem. The grating region

Work supported by the National Natural Science Foundation of China (Nos. 61177078, 61307094, 31271871), the Specialized Research Fund for the Doctoral Program of Higher Education of China (No. 20101201120001), and the Opened Fund of the State Key Laboratory on Integrated Optoelectronics (No. IOSKL2014KF15).

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