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Investigations on the CdS passivated anodic oxide–InP interface for MOS structures
Materials Science and Engineering B56 (1999) 25 – 30
Investigations on the CdS passivated anodic oxide–InP interface for MOS structures R.R. Sumathi, M. Senthil Kumar, N. Dharmarasu, J. Kumar * Crystal Growth Centre, Anna Uni6ersity, Chennai-600 025, India Received 23 June 1998; received in revised form 23 December 1998; accepted 10 February 1999
Abstract Thin layers of cadmium sulfide have been deposited on 111 n-InP using the chemical bath deposition technique at room temperature. X-ray photoelectron spectroscopy (XPS) results show that sulfur in CdS removes native oxide present on the InP surface and forms a chemically stable surface. Anodic oxidation was carried out on the CdS passivated InP surface. XPS results of oxides show the formation of highly stable P2O5. Improved C –V characteristics have been observed on CdS treated MOS diodes. Delay time measurements and bias stress measurements demonstrate the high stability of CdS passivated MOS diodes. NSS values as low as 3 ×1010 cm − 2 eV − 1 were obtained for CdS treated MOS diodes. © 1999 Elsevier Science S.A. All rights reserved. Keywords: Indium phosphide; Cadmium sulfide; Passivation; MOS; Anodic oxide; X-ray photoelectron spectroscopy; Surface state density; Interface
1. Introduction Indium phosphide (InP) is a potentially attractive material for high speed, high power and electro-optic devices because of its high electron mobility and saturated drift velocity. The high density of midgap states on the unpassivated surfaces of InP results in high surface recombination velocities and Fermi-level pinning that limit device performance. The realisation of stable and reliable InP MISFET strongly depends on the passivation process for the InP surface [1]. For any passivation process, the control of the interface formation is of prime importance [2]. Continued efforts have been made on improving the InP surface by: (i) inserting a thin well-controlled interlayer prior to the insulator deposition [3], (ii) surface treatment of InP using sulfides [4,5] and condensed phosphates [1] and (iii) using double-layer dielectrics [6], etc. Eftekhari [7] has showed that the passivation of InP
* Corresponding author. Tel./fax: +91-44-235-2774. E-mail address: [email protected] (J. Kumar)
using sulfur and subsequent rapid thermal annealing of the oxide reduces the fixed charge density and increases the breakdown voltage and resistivity. Recently cadmium sulfide (CdS) has been identified as a very good passivating agent for InP [8]. It has been reported that the epitaxial deposition of CdS films on 111 InP using the chemical bath deposition (CBD) technique improves the photovoltaic properties of InP [9]. Dauplaise et al. [10] have reported that a very thin layer of CdS deposition on 100 InP at a deposition temperature of around 348 K for 3 min using the CBD technique reduces the surface state density at the SiO2/InP interface. The passivation mechanism of CdS on InP is not yet well understood. To our knowledge, no report exists on the effect of anodic oxidation on CdS passivated InP surfaces. In the present work we report on the detailed investigations on the effect of CdS passivation on an anodic oxide/111 InP interface using the CBD technique at room temperature. CdS deposition forms a uniform layer that maintains a chemically stable surface. The performance of this MOS device is demonstrated in terms of the excellent capacitance–voltage (C–V) characteristics.
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2. Experimental details LEC grown 111 oriented undoped n-type InP substrates with a carrier concentration of 2× 1016 cm − 3 have been used for the present investigations. The P faces were chemo-mechanically polished with BCA polishing agent HBr – K2Cr2O7 – H2O in the ratio of 2:2:1 [11]. The samples were then well rinsed with warm trichloroethylyne, acetone and methanol followed by an etching in HF:H2O (1:1) for 1 min. Ohmic contacts were formed on the backside of the samples by evaporating Au:Ge (88:12) alloy under a vacuum of 2× 10 − 6 mbar and annealing the samples at 623 K under an argon atmosphere for 5 min. The chemical bath solution for the deposition of CdS was prepared using 10 ml 0.5 M cadmium salt (3CdSO4·8H2O), 5 ml 1M thiourea (CS(NH2)2), 2.5 ml 7.4 M triethanolamine (C6H15NO3) and 7 ml ammonia solution. The volume of the final solution was made up to 50 ml by adding deionised water. The polished InP substrates were kept vertically inside the chemical bath for CdS deposition. The deposition was carried out for various deposition times of 20, 40, 60, 80 and 100 min.
The anodic oxides were grown on the CdS passivated InP substrates using an electrolyte containing 3% phosphoric acid buffered by NH4OH to give a pH value of 6 and mixed with ethylene glycol in the ratio of 1:2 [12]. The anodisation was carried out at a constant voltage of 100 V for 15 min. Chemical compositions of the oxides have been analysed using X-ray photoelectron spectroscopy (VG scientific). Mg Ka X-ray of energy 1253.6 eV was used for the X-ray photoelectron spectroscopy (XPS) analysis. The analyses were carried out for as-grown and Ar + ion (8 kV) sputtered oxides to analyse the interface. MOS structures were made by evaporating aluminium dots of 7.85×10 − 3 cm2 area on the oxide by thermal evaporation under a vacuum of 2×10 − 6 mbar. C–V (1 MHz) measurements were carried out on the MOS structures using a capacitance meter (Boonton 7200). Delay time measurement and bias stress measurements were also carried out to analyse the stability of the oxides. Surface state densities were calculated from the 1 MHz C –V plot using the Terman method [13].
Fig. 1. XPS spectra of CdS passivated InP: (a) In 3d5/2 peak, (b) P 2p peak, (c) Cd 3d5/2 peak and (d) S 2p peak.
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Fig. 2. XPS spectra of anodic oxide grown on CdS passivated InP for as grown and Ar + sputtered oxide: (a) In 3d5/2 peaks, (b) P 2p peaks, (c) Cd 3d5/2 peaks and (d) S 2p peaks.
Fig. 1 shows the XPS spectra of a CdS layer deposited (for 40 min) on InP. Detailed scans of the indium 3d5/2, phosphorus 2p, cadmium 3d5/2 and sulfur 2p are shown in Fig. 1(a – d). The In 3d5/2 peak at 443.5 eV and P 2p peak at 127.5 eV establish that no native oxide is formed following the CdS growth. The Cd 3d5/2 peak at 405 eV and S 2p peak at 161.5 eV confirm the single crystal nature of the CBD CdS layers [10]. XPS also established that the oxides of sulfur were not formed. Fig. 2(a–d) show In 3d5/2, P 2p, Cd 3d and S 2p peaks of anodic oxide grown on CdS passivated InP for as-grown and Ar + ion sputtered for 3, 5 and 7 min.
it confirms the formation of high resistive oxide InPO4. While the oxide was sputtered with Ar + ion for 3 min, the In 3d5/2 peak shifts to a lower energy of 444.8 eV, which corresponds to In2O3 or In2S3 [14]. The In 3d peak has been found at 443.9 eV for 5 min sputtered oxide and it corresponds to the InP substrate peak. This lower binding energy may be due to the uncontrollable argon ion sputtering [15]. On further sputtering for 2 min with Ar + ion, the In 3d peak is found at 444.8 eV with increase in intensity, which corresponds to In2O3 or In2S3. Since the binding energy shifts in the In 3d5/2 peak for both oxide and sulfide are nearly equal, it is difficult to deconvolve this peak to give relative ratios of these components. But the oxygen 1s peak observed at 530 eV with reduced intensity and the S 2p peak observed at 161.9 eV with increase in intensity confirm the formation of In2S3.
3.1.1. In 3d5/2 The In 3d5/2 peak at 446 eV has been ascribed to indium bonded with phosphate [14]. For our CdS passivated and anodic oxidised InP top surface without sputtering, the In 3d5/2 peak is observed at 446.6 eV and
3.1.2. P 2p As-grown anodic oxide of CdS passivated InP produces its characteristic peak for P 2p of P2O5 at 136.5 eV. For the anodic oxide of InP without CdS, the P 2p peak has been observed at 132.6 eV [16] corresponding to InPO4, which has a lower resistivity than P2O5.
3. Results and discussion
3.1. XPS analysis
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The high resistive oxide (P2O5) formation can be explained as follows: the structure of anodic oxide on InP is composed of P2O5, In2O3 and a combination of In and P oxide (InPO3, InPO4) layers. The sulfur present in CdS dissolves In2O3 thus increasing the P2O5/In2O3 ratio. This may be accomplished by the substitution of oxygen atoms in In2O3 with sulfur atoms [7]. Sputtering of the oxide for 3 min with argon ion and subsequent analysis with XPS produced two peaks at 122.4 and 134 eV with no peak at 136.5 eV illustrating the reduction of oxidation state of phosphorus due to sputtering. The higher binding energy peak is assigned to P 2p of InPO4 and the lower energy peak is assigned to the involvement of the In 4s1/2 shell lying higher to In 3d5/2. Continuing sputtering for another 2 min and doing the above similar analysis produced identical peaks without any shift in the position but with increase in the intensity. The intensity of the In 4s peak further increases and becomes nearly equal to the intensity of P 2p whilst continuing sputtering for another 2 min.
3.1.3. Cd 3d5/2 The Cd 3d5/2 peak was not observed for as-grown oxide. It shows that no Cd is present on the surface of the oxide. Sputtering out the oxide with Ar + for 3 min shows the Cd 3d peak at the higher binding energy of 407.5 eV. This shift towards higher energy may be attributed to the metallic cadmium produced during Ar + sputtering [17], but it is very surprising to find a relatively larger peak shift of 2.5 eV. For further sputtering, the Cd 3d peak shifts towards lower binding energy and is observed at the binding energy of the CdS single crystal.
though the C–V curve shows accumulation, depletion and inversion regions, the accumulation capacitance is lower than the expected insulator layer capacitance. The insulator layer capacitance is estimated to be 250 pF, taking the dielectric constant of native oxide as 3.6 ˚ measured and the thickness of the oxide as 1000 A using ellipsometry [16,18]. As the thickness of the CdS layers is negligible, the dielectric constant or capacitance of CdS layer has not been considered for any calculation. Since the deposition of CdS is carried out at room temperature, the rate of deposition is very slow and controllable when compared to the high temperature deposition rate. The deposition rate was found to be very sensitive to the concentration of NH3, i.e. it decreases when the concentration of NH3 is increased. Triethanolamine present in the solution further reduces the rate of deposition [19]. C–V curves with negligible hysteresis and with very good MIS behaviour were obtained for the passivated diodes, which indicate a low density of fast traps near the conduction band edge. The accumulation capacitance increases for CdS passivated diodes and is nearly equal to the estimated insulator layer capacitance except for the 20 min passivated diode. The 20 min passivated diode shows drift type hysteresis and does not show good C–V characteristics. C–V plots of 100 min passivated diodes also show the drift type hysteresis and the accumulation capacitance increases more than that of the estimated insulator layer capacitance. It may be due to a very thick layer of CdS present at the interface and may change the dielectric constant of the oxide at the interface. C–V (1 MHz) measurements have been carried out for the control and CdS passivated diodes for different sweep
3.1.4. S 2p There is no sulfur peak found for as-grown and 3 min sputtered oxide. The S 2p peak is observed for 5 min sputtered oxide with very low intensity. This shows the presence of sulfur near the interface. For 7 min sputtered oxide, the S 2p peak is observed clearly at 161.9 eV with increasing intensity and shows the presence of sulfur at the interface. Oxides of sulfur were not formed during anodic oxidation of CdS passivated InP. 3.2. C–V characteristics of MOS structures C–V (1 MHz) curves for control (without CdS) and CdS passivated (for different times: 20, 40, 60, 80 and 100 min) MOS diodes are shown in Fig. 3. The C–V curves for the samples have clockwise injection type hysteresis. The C – V curves shift towards the negative side shows the presence of positive fixed charges at the oxide near the interface. For the control diode, the C – V curves have larger hysteresis when compared to CdS passivated diodes. For the control diode, even
Fig. 3. C– V (1 MHz) plot for control and CdS passivated diodes (CdS passivation has been carried out for different time periods of 20, 40, 60, 80 and 100 min).
R.R. Sumathi et al. / Materials Science and Engineering B60 (1999) 25–30
Fig. 4. C – V (1 MHz) plot for: (a) control and (b) CdS passivated diodes for higher bias values.
rates. No drift in hysteresis was observed for CdS passivated diodes while some drift was observed for the control diodes. It clearly shows the stability of the passivated diodes. C –V measurements have been carried out for the higher bias values ( − 5 to + 5 V) also. For higher biases, the control diodes show drift type hysteresis. The passivated diodes show a very good accumulation region also for high values of positive bias (Fig. 4). This shows the instability at the oxide/InP interface of the unpassivated InP surfaces and the highly stable nature of CdS passivated InP interface. To analyse the stability of the oxides further, bias stress measurements were also carried out on the samples. The drift behaviours of MOS diodes under positive bias stress are shown in Fig. 5a for the control and
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in Fig. 5b for the CdS passivated sample. A +2 V accumulation voltage was applied to the sample for time periods of 1–103 s. Following positive bias stress, the left–going C–V curves shift towards higher voltages and the right going curves are all superimposed with the initial curve for the control diodes. This behaviour is consistent with a slow trapping–fast detrapping of conduction electrons by traps located in the interfacial layer and localized at an energy above the conduction band of InP [2]. Slow trapping of electronic states is one of the major problems for drain current drift (DCD) in the fabrication of InP MISFETs. This is attributed to the instabilities of the insulator and/or the insulator–InP interface [20]. The measured drift is 0.5 V for the control diodes. For the passivated diodes there is no significant change in the C–V curve but both the right and left going curves shift slightly towards higher voltages for the stress time of 103 s. Fig. 6 shows the comparison of the experimental C–V curves with the theoretical curve. The surface state density (NSS) values for the control diode have been calculated, using Terman analysis, as 8×1010 cm − 2 eV − 1 at the midgap and 4× 1011 cm − 2 eV − 1 at the conduction band edge. This shows the presence of a high density of fast traps and the non-uniform interface trap distribution. The NSS values calculated for the passivated diodes are around 1010 cm − 2 eV − 1 through the entire band gap which establishes the presence of a low density of traps and uniform interface trap distribution.
4. Conclusions Thin layers of CdS have been deposited on 111 n-InP using the CBD technique. It was found that the deposition rate of CdS is very slow and controllable
Fig. 5. C– V (1 MHz) plot of bias stressed (for 100, 101, 102 and 103 s) (a) control and (b) CdS passivated diodes.
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Acknowledgements The Department of Science and Technology, Government of India is acknowledged for financial support through a major research grant. Miss Sumathi gratefully acknowledges the Council of Scientific and Industrial Research for the award of a Senior Research Fellowship to carry out this work.
References
Fig. 6. Theoretical and experimental high frequency C–V curves for control and CdS passivated diodes for the NSS calculation.
and sensitive to ammonia and triethanolamine present in the solution. The XPS results show that sulfur in CdS removes native oxide present on InP and forms chemically stable surface. Anodic oxidation has been carried out on CdS passivated InP surfaces. The XPS results of oxides show the formation of a highly stable and high resistive P2O5. XPS spectra taken at the interface confirms that sulfur atoms replace oxygen atoms in In2O3 and form In2S3. CdS deposition prior to anodic oxidation improves the electrical properties of MOS diodes. NSS values as low as 3× 1010 cm − 2 eV − 1 were found for CdS treated MOS diodes. Positive bias stress measurements show the high stability of CdS treated MOS diodes. C – V results confirm that the best electrical properties with the lowest density of interface states and the highest stability are obtained for the CdS passivated diodes.
.
[1] Y. Robach, M.P. Besland, J. Joseph, J. Appl. Phys. 71 (1992) 2981. [2] J. Tardy, I. Thomas, P. Viktorovitch, et al., Appl. Surf. Sci. 50 (1991) 383. [3] K.P. Pande, D. Gutierrez, Appl. Phys. Lett. 46 (1985) 416. [4] R. Iyer, R.R. Chang, D. Lile, Appl. Phys. Lett. 53 (1988) 134. [5] A. Kapila, X. Si, V. Malhotra, Mater. Res. Soc. Symp. Proc. 300 (1993) 441. [6] V. Devnath, K.N. Bhat, P.R.S. Rao, IEEE Electron. Device Lett. 18 (1997) 114. [7] G. Eftekhari, J. Elec. Chem. Soc. 141 (1994) 299. [8] K. Vaccaro, H.M. Dauplaise, A. Davis, S.M. Spaziani, J.P. Lorenzo, Appl. Phys. Lett. 67 (1995) 527. [9] D. Lincot, R. Ortega-Borges, Appl. Phys. Lett. 64 (1994) 569. [10] H.M. Dauplaise, K. Vaccaro, A. Davis, G.O. Ramseyer, J.P. Lorenso, J. Appl. Phys. 80 (1996) 2873. [11] J.L. Weyher, R. Fornari, T. Gorog, Mater. Sci. Eng. B28 (1994) 488. [12] A. Yamamoto, M. Yamaguchi, C. Uemura, J. Electrochem. Soc. 129 (1982) 488. [13] L.M. Terman, Solid State Electron. 5 (1962) 285. [14] J. Chastain, Hand Book of X-ray Photoelectron Spectroscopy, Perkin-Elmer, Eden Prairie, 1992. [15] D.T. Clark, T. Fok, Thin Solid Films 70 (1980) 261. [16] R.R. Sumathi, N. Dharmarasu, S. Arulkumaran, P. Jayavel, J. Kumar, J. Electron. Mater. 27 (1998) 1358. [17] J.S. Hammond, S.W. Gaarenstroom, N. Winograd, Anal. Chem. 47 (1975) 2193. [18] Y. Robach, A. Gagnaire, J. Joseph, Thin Solid Films 162 (1988) 81. [19] U.N. Roy, A. Ingale, K.C. Rustagi, Proc. 9th Int. Workshop on Physics of Semiconductor Devices, India, 16 – 20 December 1997, Narosa Publishing, New Delhi, Vol.2, p.1237. [20] K. Hattori, Y. Torii, J. Appl. Phys. 69 (1991) 3130.
Investigations on the CdS passivated anodic oxide–InP interface for MOS structures R.R. Sumathi, M. Senthil Kumar, N. Dharmarasu, J. Kumar * Crystal Growth Centre, Anna Uni6ersity, Chennai-600 025, India Received 23 June 1998; received in revised form 23 December 1998; accepted 10 February 1999
Abstract Thin layers of cadmium sulfide have been deposited on 111 n-InP using the chemical bath deposition technique at room temperature. X-ray photoelectron spectroscopy (XPS) results show that sulfur in CdS removes native oxide present on the InP surface and forms a chemically stable surface. Anodic oxidation was carried out on the CdS passivated InP surface. XPS results of oxides show the formation of highly stable P2O5. Improved C –V characteristics have been observed on CdS treated MOS diodes. Delay time measurements and bias stress measurements demonstrate the high stability of CdS passivated MOS diodes. NSS values as low as 3 ×1010 cm − 2 eV − 1 were obtained for CdS treated MOS diodes. © 1999 Elsevier Science S.A. All rights reserved. Keywords: Indium phosphide; Cadmium sulfide; Passivation; MOS; Anodic oxide; X-ray photoelectron spectroscopy; Surface state density; Interface
1. Introduction Indium phosphide (InP) is a potentially attractive material for high speed, high power and electro-optic devices because of its high electron mobility and saturated drift velocity. The high density of midgap states on the unpassivated surfaces of InP results in high surface recombination velocities and Fermi-level pinning that limit device performance. The realisation of stable and reliable InP MISFET strongly depends on the passivation process for the InP surface [1]. For any passivation process, the control of the interface formation is of prime importance [2]. Continued efforts have been made on improving the InP surface by: (i) inserting a thin well-controlled interlayer prior to the insulator deposition [3], (ii) surface treatment of InP using sulfides [4,5] and condensed phosphates [1] and (iii) using double-layer dielectrics [6], etc. Eftekhari [7] has showed that the passivation of InP
* Corresponding author. Tel./fax: +91-44-235-2774. E-mail address: [email protected] (J. Kumar)
using sulfur and subsequent rapid thermal annealing of the oxide reduces the fixed charge density and increases the breakdown voltage and resistivity. Recently cadmium sulfide (CdS) has been identified as a very good passivating agent for InP [8]. It has been reported that the epitaxial deposition of CdS films on 111 InP using the chemical bath deposition (CBD) technique improves the photovoltaic properties of InP [9]. Dauplaise et al. [10] have reported that a very thin layer of CdS deposition on 100 InP at a deposition temperature of around 348 K for 3 min using the CBD technique reduces the surface state density at the SiO2/InP interface. The passivation mechanism of CdS on InP is not yet well understood. To our knowledge, no report exists on the effect of anodic oxidation on CdS passivated InP surfaces. In the present work we report on the detailed investigations on the effect of CdS passivation on an anodic oxide/111 InP interface using the CBD technique at room temperature. CdS deposition forms a uniform layer that maintains a chemically stable surface. The performance of this MOS device is demonstrated in terms of the excellent capacitance–voltage (C–V) characteristics.
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2. Experimental details LEC grown 111 oriented undoped n-type InP substrates with a carrier concentration of 2× 1016 cm − 3 have been used for the present investigations. The P faces were chemo-mechanically polished with BCA polishing agent HBr – K2Cr2O7 – H2O in the ratio of 2:2:1 [11]. The samples were then well rinsed with warm trichloroethylyne, acetone and methanol followed by an etching in HF:H2O (1:1) for 1 min. Ohmic contacts were formed on the backside of the samples by evaporating Au:Ge (88:12) alloy under a vacuum of 2× 10 − 6 mbar and annealing the samples at 623 K under an argon atmosphere for 5 min. The chemical bath solution for the deposition of CdS was prepared using 10 ml 0.5 M cadmium salt (3CdSO4·8H2O), 5 ml 1M thiourea (CS(NH2)2), 2.5 ml 7.4 M triethanolamine (C6H15NO3) and 7 ml ammonia solution. The volume of the final solution was made up to 50 ml by adding deionised water. The polished InP substrates were kept vertically inside the chemical bath for CdS deposition. The deposition was carried out for various deposition times of 20, 40, 60, 80 and 100 min.
The anodic oxides were grown on the CdS passivated InP substrates using an electrolyte containing 3% phosphoric acid buffered by NH4OH to give a pH value of 6 and mixed with ethylene glycol in the ratio of 1:2 [12]. The anodisation was carried out at a constant voltage of 100 V for 15 min. Chemical compositions of the oxides have been analysed using X-ray photoelectron spectroscopy (VG scientific). Mg Ka X-ray of energy 1253.6 eV was used for the X-ray photoelectron spectroscopy (XPS) analysis. The analyses were carried out for as-grown and Ar + ion (8 kV) sputtered oxides to analyse the interface. MOS structures were made by evaporating aluminium dots of 7.85×10 − 3 cm2 area on the oxide by thermal evaporation under a vacuum of 2×10 − 6 mbar. C–V (1 MHz) measurements were carried out on the MOS structures using a capacitance meter (Boonton 7200). Delay time measurement and bias stress measurements were also carried out to analyse the stability of the oxides. Surface state densities were calculated from the 1 MHz C –V plot using the Terman method [13].
Fig. 1. XPS spectra of CdS passivated InP: (a) In 3d5/2 peak, (b) P 2p peak, (c) Cd 3d5/2 peak and (d) S 2p peak.
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Fig. 2. XPS spectra of anodic oxide grown on CdS passivated InP for as grown and Ar + sputtered oxide: (a) In 3d5/2 peaks, (b) P 2p peaks, (c) Cd 3d5/2 peaks and (d) S 2p peaks.
Fig. 1 shows the XPS spectra of a CdS layer deposited (for 40 min) on InP. Detailed scans of the indium 3d5/2, phosphorus 2p, cadmium 3d5/2 and sulfur 2p are shown in Fig. 1(a – d). The In 3d5/2 peak at 443.5 eV and P 2p peak at 127.5 eV establish that no native oxide is formed following the CdS growth. The Cd 3d5/2 peak at 405 eV and S 2p peak at 161.5 eV confirm the single crystal nature of the CBD CdS layers [10]. XPS also established that the oxides of sulfur were not formed. Fig. 2(a–d) show In 3d5/2, P 2p, Cd 3d and S 2p peaks of anodic oxide grown on CdS passivated InP for as-grown and Ar + ion sputtered for 3, 5 and 7 min.
it confirms the formation of high resistive oxide InPO4. While the oxide was sputtered with Ar + ion for 3 min, the In 3d5/2 peak shifts to a lower energy of 444.8 eV, which corresponds to In2O3 or In2S3 [14]. The In 3d peak has been found at 443.9 eV for 5 min sputtered oxide and it corresponds to the InP substrate peak. This lower binding energy may be due to the uncontrollable argon ion sputtering [15]. On further sputtering for 2 min with Ar + ion, the In 3d peak is found at 444.8 eV with increase in intensity, which corresponds to In2O3 or In2S3. Since the binding energy shifts in the In 3d5/2 peak for both oxide and sulfide are nearly equal, it is difficult to deconvolve this peak to give relative ratios of these components. But the oxygen 1s peak observed at 530 eV with reduced intensity and the S 2p peak observed at 161.9 eV with increase in intensity confirm the formation of In2S3.
3.1.1. In 3d5/2 The In 3d5/2 peak at 446 eV has been ascribed to indium bonded with phosphate [14]. For our CdS passivated and anodic oxidised InP top surface without sputtering, the In 3d5/2 peak is observed at 446.6 eV and
3.1.2. P 2p As-grown anodic oxide of CdS passivated InP produces its characteristic peak for P 2p of P2O5 at 136.5 eV. For the anodic oxide of InP without CdS, the P 2p peak has been observed at 132.6 eV [16] corresponding to InPO4, which has a lower resistivity than P2O5.
3. Results and discussion
3.1. XPS analysis
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The high resistive oxide (P2O5) formation can be explained as follows: the structure of anodic oxide on InP is composed of P2O5, In2O3 and a combination of In and P oxide (InPO3, InPO4) layers. The sulfur present in CdS dissolves In2O3 thus increasing the P2O5/In2O3 ratio. This may be accomplished by the substitution of oxygen atoms in In2O3 with sulfur atoms [7]. Sputtering of the oxide for 3 min with argon ion and subsequent analysis with XPS produced two peaks at 122.4 and 134 eV with no peak at 136.5 eV illustrating the reduction of oxidation state of phosphorus due to sputtering. The higher binding energy peak is assigned to P 2p of InPO4 and the lower energy peak is assigned to the involvement of the In 4s1/2 shell lying higher to In 3d5/2. Continuing sputtering for another 2 min and doing the above similar analysis produced identical peaks without any shift in the position but with increase in the intensity. The intensity of the In 4s peak further increases and becomes nearly equal to the intensity of P 2p whilst continuing sputtering for another 2 min.
3.1.3. Cd 3d5/2 The Cd 3d5/2 peak was not observed for as-grown oxide. It shows that no Cd is present on the surface of the oxide. Sputtering out the oxide with Ar + for 3 min shows the Cd 3d peak at the higher binding energy of 407.5 eV. This shift towards higher energy may be attributed to the metallic cadmium produced during Ar + sputtering [17], but it is very surprising to find a relatively larger peak shift of 2.5 eV. For further sputtering, the Cd 3d peak shifts towards lower binding energy and is observed at the binding energy of the CdS single crystal.
though the C–V curve shows accumulation, depletion and inversion regions, the accumulation capacitance is lower than the expected insulator layer capacitance. The insulator layer capacitance is estimated to be 250 pF, taking the dielectric constant of native oxide as 3.6 ˚ measured and the thickness of the oxide as 1000 A using ellipsometry [16,18]. As the thickness of the CdS layers is negligible, the dielectric constant or capacitance of CdS layer has not been considered for any calculation. Since the deposition of CdS is carried out at room temperature, the rate of deposition is very slow and controllable when compared to the high temperature deposition rate. The deposition rate was found to be very sensitive to the concentration of NH3, i.e. it decreases when the concentration of NH3 is increased. Triethanolamine present in the solution further reduces the rate of deposition [19]. C–V curves with negligible hysteresis and with very good MIS behaviour were obtained for the passivated diodes, which indicate a low density of fast traps near the conduction band edge. The accumulation capacitance increases for CdS passivated diodes and is nearly equal to the estimated insulator layer capacitance except for the 20 min passivated diode. The 20 min passivated diode shows drift type hysteresis and does not show good C–V characteristics. C–V plots of 100 min passivated diodes also show the drift type hysteresis and the accumulation capacitance increases more than that of the estimated insulator layer capacitance. It may be due to a very thick layer of CdS present at the interface and may change the dielectric constant of the oxide at the interface. C–V (1 MHz) measurements have been carried out for the control and CdS passivated diodes for different sweep
3.1.4. S 2p There is no sulfur peak found for as-grown and 3 min sputtered oxide. The S 2p peak is observed for 5 min sputtered oxide with very low intensity. This shows the presence of sulfur near the interface. For 7 min sputtered oxide, the S 2p peak is observed clearly at 161.9 eV with increasing intensity and shows the presence of sulfur at the interface. Oxides of sulfur were not formed during anodic oxidation of CdS passivated InP. 3.2. C–V characteristics of MOS structures C–V (1 MHz) curves for control (without CdS) and CdS passivated (for different times: 20, 40, 60, 80 and 100 min) MOS diodes are shown in Fig. 3. The C–V curves for the samples have clockwise injection type hysteresis. The C – V curves shift towards the negative side shows the presence of positive fixed charges at the oxide near the interface. For the control diode, the C – V curves have larger hysteresis when compared to CdS passivated diodes. For the control diode, even
Fig. 3. C– V (1 MHz) plot for control and CdS passivated diodes (CdS passivation has been carried out for different time periods of 20, 40, 60, 80 and 100 min).
R.R. Sumathi et al. / Materials Science and Engineering B60 (1999) 25–30
Fig. 4. C – V (1 MHz) plot for: (a) control and (b) CdS passivated diodes for higher bias values.
rates. No drift in hysteresis was observed for CdS passivated diodes while some drift was observed for the control diodes. It clearly shows the stability of the passivated diodes. C –V measurements have been carried out for the higher bias values ( − 5 to + 5 V) also. For higher biases, the control diodes show drift type hysteresis. The passivated diodes show a very good accumulation region also for high values of positive bias (Fig. 4). This shows the instability at the oxide/InP interface of the unpassivated InP surfaces and the highly stable nature of CdS passivated InP interface. To analyse the stability of the oxides further, bias stress measurements were also carried out on the samples. The drift behaviours of MOS diodes under positive bias stress are shown in Fig. 5a for the control and
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in Fig. 5b for the CdS passivated sample. A +2 V accumulation voltage was applied to the sample for time periods of 1–103 s. Following positive bias stress, the left–going C–V curves shift towards higher voltages and the right going curves are all superimposed with the initial curve for the control diodes. This behaviour is consistent with a slow trapping–fast detrapping of conduction electrons by traps located in the interfacial layer and localized at an energy above the conduction band of InP [2]. Slow trapping of electronic states is one of the major problems for drain current drift (DCD) in the fabrication of InP MISFETs. This is attributed to the instabilities of the insulator and/or the insulator–InP interface [20]. The measured drift is 0.5 V for the control diodes. For the passivated diodes there is no significant change in the C–V curve but both the right and left going curves shift slightly towards higher voltages for the stress time of 103 s. Fig. 6 shows the comparison of the experimental C–V curves with the theoretical curve. The surface state density (NSS) values for the control diode have been calculated, using Terman analysis, as 8×1010 cm − 2 eV − 1 at the midgap and 4× 1011 cm − 2 eV − 1 at the conduction band edge. This shows the presence of a high density of fast traps and the non-uniform interface trap distribution. The NSS values calculated for the passivated diodes are around 1010 cm − 2 eV − 1 through the entire band gap which establishes the presence of a low density of traps and uniform interface trap distribution.
4. Conclusions Thin layers of CdS have been deposited on 111 n-InP using the CBD technique. It was found that the deposition rate of CdS is very slow and controllable
Fig. 5. C– V (1 MHz) plot of bias stressed (for 100, 101, 102 and 103 s) (a) control and (b) CdS passivated diodes.
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R.R. Sumathi et al. / Materials Science and Engineering B60 (1999) 25–30
Acknowledgements The Department of Science and Technology, Government of India is acknowledged for financial support through a major research grant. Miss Sumathi gratefully acknowledges the Council of Scientific and Industrial Research for the award of a Senior Research Fellowship to carry out this work.
References
Fig. 6. Theoretical and experimental high frequency C–V curves for control and CdS passivated diodes for the NSS calculation.
and sensitive to ammonia and triethanolamine present in the solution. The XPS results show that sulfur in CdS removes native oxide present on InP and forms chemically stable surface. Anodic oxidation has been carried out on CdS passivated InP surfaces. The XPS results of oxides show the formation of a highly stable and high resistive P2O5. XPS spectra taken at the interface confirms that sulfur atoms replace oxygen atoms in In2O3 and form In2S3. CdS deposition prior to anodic oxidation improves the electrical properties of MOS diodes. NSS values as low as 3× 1010 cm − 2 eV − 1 were found for CdS treated MOS diodes. Positive bias stress measurements show the high stability of CdS treated MOS diodes. C – V results confirm that the best electrical properties with the lowest density of interface states and the highest stability are obtained for the CdS passivated diodes.
.
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