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Ion implant testing for production control
World Abstracts on Microelectronics and Reliability developed by using an interfacial layer-thermionic-diffusion model. Assuming a Gaussian distribution for the implanted profile, the barrier-height enhancement and ideality factor have been derived analytically. Using low energy (25 KeV) arsenic implantation with the dose ranged form 8 × 101°cm -2 to 1012cm 2, A l - n - p silicon Schottky barrier diodes have been fabricated and characterized. Comparisons between the experimental measurements and the results of computer simulations have been performed and satisfactory agreements between these comparisons have been obtained, The reverse I-V characteristics of the fabricated A1 n-p silicon Shottky barrier diodes can also be well simulated by the developed model, Latch-up and timing failure analysis of CMOS VLSI using electron beam techniques. S. M. DAVIDSON.IEEE 21st Ann. Proc. Reliab. Phys. 130 (1983). An electron beam testing system has been established for CMOS failure analysis. Problems studied include leakage, latch-up, timing, short circuits, crystallographic defects and step coverage. Two applications are described in detail. Synchronous voltage contrast and EBIC imaging techniques have allowed latchup paths in input protection diode structures and output drivers to be located. Voltage contrast waveform measurements have analysed timing spreads in ULAs; these have been shown to be related to the cell design and the layout,
Leakage currents in ion implantation systems. C. B. YARLING. Semiconductor Int. 110 (August 1983). Leakage-caused errors in wafer MOSFET current and voltage measurements can be avoided by knowing how to locate the leakage.
597
Analytical solutions for threshold voltage calculations in ionimplanted IGFETS. K. SHENALSolid-St. Electron. 26 (8) 761 (1983).Analytical expressions for threshold voltages are obtained for ion-implanted IGFETs having Gaussian impurity profiles. The results are based on a closed-form solution of the static Poisson's equation in the depletion layer. The substrate bias dependence of the threshold voltage has been derived. A comparison of the results from the present calculations to the previously published data for profiles centered near the Si s i n 2 interface shows excellent agreement with some changes in the doping parameters. Modelling of threshold voltages for short channel devices is presented by defining an equivalent box profile. These results will be quite useful in the design of implanted devices for VLSt applications where it is expected that highly nonlinear charge profiles will be obtained by the use of very shallow ion implants andminimal high temperature processing.
Noise measurements in ion implanted MOSFETs. H. S. PARK and A. VAN DERZIEL. Solid-St. Electron. 26 (8) 747 (1983). An example is given for 1/f noise in MOSFETs caused by a non-uniform channel that is noisiest at the drain. The device is an ion implanted unit and therefore the noise shows generation-recombination bumps superimposed on a 1If noise background. A similar device shows a very sharp peak in the noise at saturation, followed by a new peak beyond saturation. The noise is of the l / f type with some indication of generation-recombination noise bumps at the highest drain voltage. Non-ion implanted devices do not show these effects.
Planar, ion-implanted bipolar devices in GaAs. K. V.
Ion implant testing for production control. GILBERT A.
VAIDYANATHAN,R. A. JULLENS,C. L. ANDERSONand H.L. DUNLAP. Solid-St. Electron~ 26 (8) 717 (1983). Selected-area ion implantation using heavy metal masks to define the device geometry has been used to fabricate doubly implanted n-p n bipolar transistors and planar, isolated p-n junction devices in GaAs. The bipolar transistors exhibited commonemitter current gains as high as 25. Collector-base breakdown voltages of 45V were observed. The junction diodes (~ 200 lam dia.) exhibited sub-nanoampere leakage currents at 15 V of reverse bias. Surface leakage appears to be the dominant mechanism responsible for the observed leakage currents. The diode forward current is limited by recomination in the space charge region,
GRUBER.Solid St. Technol. 159 (August 1983). Even with the inherent reproducibility and uniformity of ion implantation, it is still subject to the same operational errors, equipment malfunctions and process variables associated with other silicon device and circuit fabrication processes. This is especially true when many implants having different species, doses and energies are done on a few implanters. This paper discusses how production control has been achieved by implementation of an in-process testing procedure that uses V/I and CV measurements backed up by spreading resistance profiles to monitor the implant process. The result has been improved efficiency, increased awareness and a direct yield improvement of 2.1%.
Leakage currents in ion implantation systems. C. B. YARLING. Semiconductor Int. 110 (August 1983). Leakage-caused errors in wafer MOSFET current and voltage measurements can be avoided by knowing how to locate the leakage.
597
Analytical solutions for threshold voltage calculations in ionimplanted IGFETS. K. SHENALSolid-St. Electron. 26 (8) 761 (1983).Analytical expressions for threshold voltages are obtained for ion-implanted IGFETs having Gaussian impurity profiles. The results are based on a closed-form solution of the static Poisson's equation in the depletion layer. The substrate bias dependence of the threshold voltage has been derived. A comparison of the results from the present calculations to the previously published data for profiles centered near the Si s i n 2 interface shows excellent agreement with some changes in the doping parameters. Modelling of threshold voltages for short channel devices is presented by defining an equivalent box profile. These results will be quite useful in the design of implanted devices for VLSt applications where it is expected that highly nonlinear charge profiles will be obtained by the use of very shallow ion implants andminimal high temperature processing.
Noise measurements in ion implanted MOSFETs. H. S. PARK and A. VAN DERZIEL. Solid-St. Electron. 26 (8) 747 (1983). An example is given for 1/f noise in MOSFETs caused by a non-uniform channel that is noisiest at the drain. The device is an ion implanted unit and therefore the noise shows generation-recombination bumps superimposed on a 1If noise background. A similar device shows a very sharp peak in the noise at saturation, followed by a new peak beyond saturation. The noise is of the l / f type with some indication of generation-recombination noise bumps at the highest drain voltage. Non-ion implanted devices do not show these effects.
Planar, ion-implanted bipolar devices in GaAs. K. V.
Ion implant testing for production control. GILBERT A.
VAIDYANATHAN,R. A. JULLENS,C. L. ANDERSONand H.L. DUNLAP. Solid-St. Electron~ 26 (8) 717 (1983). Selected-area ion implantation using heavy metal masks to define the device geometry has been used to fabricate doubly implanted n-p n bipolar transistors and planar, isolated p-n junction devices in GaAs. The bipolar transistors exhibited commonemitter current gains as high as 25. Collector-base breakdown voltages of 45V were observed. The junction diodes (~ 200 lam dia.) exhibited sub-nanoampere leakage currents at 15 V of reverse bias. Surface leakage appears to be the dominant mechanism responsible for the observed leakage currents. The diode forward current is limited by recomination in the space charge region,
GRUBER.Solid St. Technol. 159 (August 1983). Even with the inherent reproducibility and uniformity of ion implantation, it is still subject to the same operational errors, equipment malfunctions and process variables associated with other silicon device and circuit fabrication processes. This is especially true when many implants having different species, doses and energies are done on a few implanters. This paper discusses how production control has been achieved by implementation of an in-process testing procedure that uses V/I and CV measurements backed up by spreading resistance profiles to monitor the implant process. The result has been improved efficiency, increased awareness and a direct yield improvement of 2.1%.