Microelectronic Engineering 57–58 (2001) 145–153 www.elsevier.com / locate / mee
Ion projection lithography: status of tool and mask developments b ¨ Rainer Kaesmaier a , *, Albrecht Ehrmann a , Hans Loschner a
b
Infineon Technologies AG, Munich, Germany IMS — Ionen Mikrofabrikations Systeme GmbH, A-1020 Vienna, Austria
Abstract As part of the European MEDEA project on ion projection lithography (IPL), the ion optical system of a process development tool (PDT-IOS) has been designed and integrated at IMS Vienna. The ion optics system (PDT-IOS) includes in situ metrology systems. The different PDT-IOS subsystems, including in situ diagnostics and metrology, were switched on in the fourth quarter of 2000 so that detailed testing should start in the first quarter of 2001. In parallel to integration of the PDT ion optics, a test bench for a vertical vacuum wafer stage has been realized by Leica. Operation of magnetic bearing supported stage movement has already been demonstrated. An ASML vacuum-compatible optical wafer alignment system has been integrated to this stage test bench system recently. In air, an X /Y alignment repeatability of less than 3 nm (3s) has been shown. Parallel to the IPL tool activities, intensive development of IPL stencil masks is ongoing at Infineon Technologies Mask House and the Institute for Microelectronics Stuttgart with success in producing 150 and 200 mm stencil masks. An overview of the stencil mask development is provided. 2001 Published by Elsevier Science B.V. Keywords: Next generation lithography; Ion projection lithography; Stencil mask
1. Introduction In 1997, the semiconductor industry started the so-called next generation lithography (NGL) development programs all over the world, which should secure the ongoing procedure of frequently reducing the structure size for integrated circuits (Moore’s law). Compared with the other NGL techniques (X-ray, EUV, EPL, EBDW), ion projection lithography (IPL) offers the smallest (particle) wavelength (5310 25 nm for 100 keV He 1 ions). Implementing wide field electrostatic ion beam optics IPL is the only technique maintaining multi-generational stepper instead of much more complicated scanner exposure principles into the sub-100 nm regime [1]. Over the last 4 years key developments for a 43 projection system has been built up, as well as the knowledge for manufacturing IPL stencil masks. The awaited exposures are expected to show that the developed IPL tool and masks work together in such a way that the forecasted potential of IPL as a cost-effective lithography technology for 50-nm nodes and below can be demonstrated. * Corresponding author. Tel.: 149-89-2345-0885; fax: 149-89-2342-3029. E-mail address:
[email protected] (R. Kaesmaier). 0167-9317 / 01 / $ – see front matter PII: S0167-9317( 01 )00506-8
2001 Published by Elsevier Science B.V.
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Fig. 1. First lens electrodes of PDT 43 reduction ion optical column.
2. IPL process development tool As noted above, IMS Vienna has concentrated its activities on the integration of the ion-optical system of the IPL process development tool (PDT-IOS). In Q4 / 99, the lens electrodes of the condenser system and the Leica mask changer have been mounted [1], while in Q1 / 00 the lens electrodes of the 43 reduction ion optics have been integrated (Fig. 1), several of them realized as FCL (field composable lens [1]) electrodes (Fig. 2). The inner contours with shining interference colors demonstrate the excellent diamond finish of the aluminum lens electrodes. In Q2 / 00, the pattern lock [1] system and in situ metrology [1] stage have been added (Fig. 3).
Fig. 2. FCL (field composable lens [1]) electrode.
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Fig. 3. Pattern lock system and in situ metrology stage integrated to PDT-IOS.
Furthermore, the LBNL co-axial multi-cusp ion source [2] has been tested and improved by IMS Vienna through careful engineering. A sophisticated ion beam extraction system has been designed, realized and tested using the IMS ion source test bench. Excellent agreement between simulated extraction and experimental results have been achieved. Using a retarding field spectrometer, an energy spread of the extracted 5 keV helium ion beam current of 1.7 eV FWHM has been measured, low enough to be able to achieve the 50-nm resolution target within the 12.5-mm field of the PDT ion-optical column. At the end of Q2 / 00 this characterized source has been added to the PDT system (Fig. 4). In Q2 / 00 and Q3 / 00, integration of high voltage feed-throughs and power supplies has been finalized. Three optical lens electrode positioning systems [1] have also been added (Fig. 5). As a next step, the different subsystems of the PDT-IOS will be tested and afterwards detailed ion-optical performance tests can commence. As noted in the introduction, a wafer stage test bench has been realized consisting of a Leica vertical vacuum stage (for up to 300 mm wafer size) integrated to a vacuum housing ring. This vacuum wafer stage should be mounted in the PDT-IOS of IMS Vienna once all feasibility tests of the ion-optical column of the PDT-IOS are completed. Recently, an ASML vacuum-compatible optical wafer alignment system has been integrated to this test bench (Fig. 6). In air, this ASML system has shown alignment precision of 3 nm (3s). The next steps are now alignment and metrology tests of the Leica stage with the integrated ASML optical wafer alignment system.
3. Stencil mask The basic know-how for manufacturing IPL stencil masks has existed for some time within the MEDEA project [9]. The recent focus within the mask process is on stress engineering as well as on the integration of more and more functionalities in IPL stencil masks. For the overlay test masks, ion-optical pre-distortion [3] has been carried out. Design split for memory and logic layers, as well as
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Fig. 4. LBNL co-axial multi-cusp ion source integrated to PDT-IOS.
local FE modeling, is being developed. Both the ion-optical correction shift and the layer stresses do not induce CD changes.
3.1. Overlay test masks For the PDT-IOS exposure tool tests, 150-mm stencil masks have been manufactured using SOI mask-wafer blanks and the established wafer flow fabrication process [4,5]. The design of these masks contains an array of overlay measurement structures (crosses of 40 mm size and 2 mm linewidth). In addition, resolution test patterns (dense and isolated features) are part of the mask design (Fig. 7). For in situ metrology measurements [1], an array of L-marks is used. The pattern lock system uses 12 ion reference beams originating from stencil openings (pattern lock marks) which are placed circumferentially 12 times at a radius of |100 mm. This are displayed in Fig. 8. In order to adjust the ion-optical image, the mask has to have a pre-distortion [3]. This task has been accomplished using the AISS software tool developed for the IPL mask data post-processing [6]. In Fig. 9, the pre-distortion of a fabricated stencil mask pattern is displayed by LMS IPRO measurement results. The radial character of the pre-distortion is clearly recognizable. The maximum value for the pre-distortion is 5.9 mm across the maximum pattern field distance of 71 mm. Scaled down to a feature size of 100 nm at the wafer, the corresponding magnification (CD change) is ,0.25 nm. This can be neglected for CD budget considerations. Structures which had originally Manhattan-structures
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Fig. 5. PDT-IOS at IMS Vienna, status 5 September 2000.
Fig. 6. ASML vacuum compatible optical wafer alignment system integrated to wafer stage test bench system at Leica — Jena.
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Fig. 7. SEM graph of 400-nm resolution test patterns (dense and isolated) of overlay test mask.
are altered by the pre-distortion. The maximum angle variations are of the order of 0.18. Angles other than 0, 90 or 458 are difficult to handle in mask patterning. So, the solution is to keep these 0, 45 and 908 angles and to include steps (grid size of mask patterning system). This does not cause problems, as (i) the critical structures do not contain very long clear areas or lines (patterns of some critical layers like contact holes are small themselves or patterns of layers like gate or metal lines are split into two complementary masks) and (ii) the grid of the designs shrinks rapidly down to a few nm so that design-induced steps in oblique lines are smoothed out by processing.
3.2. Split designs and local distortion Both memory and logic designs are used to test and improve the split software. Fig. 10 shows a cutting of a memory and of a logic design. The memory gate layer, originally incorporates long lines. These lines are split in parts of an aspect ratio of 1:10. At the endings, they have square structures of
Fig. 8. SEM graph of detail of pattern lock marks of overlay test mask.
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Fig. 9. Characteristic pattern shift of ion-optical correction. The data is collected from the entire membrane field. In the 50350-mm design pattern area the maximum shift is 5.9 mm.
about half of the feature size. These endings facilitate the stitching by enlarging the process window [3]. To compensate the distortions caused by the bulk silicon removal, which is done after patterning [7], the shifts before and after bulk silicon removal are predicted by FE modeling. This FE modeling is to be incorporated into the AISS software tool. As not all the structures of the real split design can be included in the FE calculations, an equivalent model [8] is to be used. To further improve the existing model [6], careful FE modeling of characteristic parts of the real design has been performed. In Fig. 11, a plot is displayed which reflects the result of a calculation to extract the equivalent stiffness of the cutted part of the design. By simulating forces (stress) on the right side (red) it is possible to calculate the equivalent stiffness of this particular part of the design. In addition, these simulations give information on local distortions and CD changes due to stresses. For the Si membrane stresses below 10 MPa, which are used for IPL stencil masks, the maximum local CD change for these kind of situations is of 4 nm for a 280-nm stencil opening pattern.
4. Conclusions In comparison to the last paper on the IPL MEDEA project [1], the integration of the ion-optical part of the process development tool involved the major step of getting all hardware parts together and extract the beam from the source. First beam-on date was 4th August 2000. With the pattern-lock and the in situ metrology system, the two key parts could be integrated successfully. Within the parallel
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Fig. 10. (a) Cutting from memory gate layer (|10-mm scale). (b) Cutting from logic gate layer (|3-mm scale, current design).
Fig. 11. FE simulation of a cutting of a DRAM layer: internal stresses of 10 MPa lead to CD changes of 1.5% (nominal feature size 280 nm).
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activities of the vacuum wafer stage development with the integrated alignment system, the hardware integration of the Leica wafer-stage with the ASML alignment system was fulfilled. Manufacturing of the test masks, which are needed once the process development tool is ready for exposures, has started. The first overlay test-mask shows good functionality of the used mask processing software, which incorporates pre-distortion into the mask structure positions, needed to match the ion-optical distortion and thus to achieve distortion-free wafer exposures. The additional feature of the mask processing software, the pattern split for complementary masks, has been tested by using actual DRAM and logic designs. Furthermore, FE modeling to predict distortion during mask processing has been improved by also using actual designs. Acknowledgements The excellent contributions of all IPL partners and their effort on the existing status of IPL tool and mask development is greatly acknowledged. Thanks to T. Struck, J. Butschke, F. Letzkus, R. Springer and E. Cekan working on the realization of the test-masks, and to E. Haugeneder, F.-M. Kamm, S. Schunck and A. Petraschenko for their excellent mask software work. The project is supported by the Austrian, the German and the Dutch governments under the label of MEDEA. References ¨ [1] R. Kaesmaier, H. Loschner, Proc. SPIE 3997 (2000) 1. ¨ [2] Y. Lee, K.N. Leung, M.D. Williams, W.H. Bruenger, W. Fallmann, H. Loschner, G. Stengl, in: Proceedings of 1999 IEEE Particle Accelerator Conference, New York, 29 March–2 April, 1999, pp. 2575–2577. ¨ [3] H. Loschner, R. Kaesmaier, P.W.H. de Jager, B. Mertens, White Paper on Ion Projection Lithography, submitted to International SEMATECH November 1999 (unpublished). [4] J. Butschke, A. Ehrmann, E. Haugeneder, M. Irmscher, R. Kaesmaier, K. Kragler, F. Letzkus, H. Loeschner, J. Mathuni, I.W. Rangelow, C. Reuter, F. Shi, R. Springer, P. Reinhard, Proceedings of 15th European Conference on Mask Technology ’98, Proc. SPIE 3665 (1999) 20–29. ¨ [5] F. Letzkus, J. Butschke, B. Hofflinger, M. Irmscher, C. Reuter, R. Springer, A. Ehrmann, J. Mathuni, MNE ’99 Rome, Microelectron. Eng. 53 (2000) 609–612. ¨ [6] H. Hartmann, A. Petrashenko, S. Schunck, R. Steinmetz, E. Haugeneder, H. Loschner, Proceedings 16th European Conference on Mask Technology ’99, Proc. SPIE 3996 (2000) 105–107. ¨ [7] A. Ehrmann, S. Huber, R. Kasmaier, A. Oelmann, T. Struck, Proc. SPIE 3546 (1998) 194–205. [8] A. Fisher, R. Engelstad, E. Lovell, Proc. SPIE 3331 (1998) 559–567. ¨ [9] T. Struck, A. Ehrmann, E. Haugeneder, H. Loschner, J. Butschke, F. Letzkus, R. Springer, Proc. SPIE 3997 (2000) 373–384.