Knowledge-based system tool for high-level BIST design

Knowledge-based system tool for high-level BIST design ASIC designers are not usually experienced enough to incorporate built-in self-test into a design. N A Jones and K Baker present a knowledge-based CAD tool that facilitates the process

The paper describes a knowledge-based computer-aided design (CAD) tool to plan the use of built-in self-test (BIST) in VLSl design. Software is being developed using the usP object-oriented programming system (LOOPS), a multiparadigm programming environment on Xerox 1108 workstations. The software employs object-oriented, rulebased and procedural programming to model various aspects of the system. The knowledge on which the system is based has been derived from a study group of design-fortestability (DFT) experts drawn from a consortium of five UK companies working under the Alvey VLSI programme. The motivation for the tool is that BIST is expected to have a positive impact on test costs. A range of artificial intelligence techniques are used, including rule-based systems and planning. VLSI design

built-in self-test

knowledge-basedsystems

ASICs

Test is recognized as an important issue in the design of VLSI application-specific ICs (ASICs). In recent years, developments in design for testability have focussed on the concept of BIST as a solution to the problems of VLSI test. These developments have provided a great variety of methods, but with very few being widely applicable. Unfortunately, true VLSl is complex and varied in form, and so classical structured BIST methods are only suitable for circuit designs where a rigid design method and silicon overhead are acceptable. Structured BIST schemes have been proposed in the area of digital signal processing and two good examples have been developed in the UK 1' 2. Both schemes rely on the designer accepting either a bit serial or bit parallel design methodology where BIST can be overlaid. Neither scheme permits the designer to mix the bit serial and bit parallel methodologies. The solution to this problem is to apply a wide variety of BIST techniques in an optimal manner. However, this requires a high degree of expertise and is thought to be GEC Research Ltd, Hirst Research Centre, East Lane, Wembley, Middx HA9 7PP, UK ©1986 IEEE. Reproduced with permission from IEEE International Test Conference, Washington, DC, USA (8-11 Sept. 1986)

beyond the capabilities of most ASIC designers. An experienced custom designer or DFT expert can plan testability into a design at an early stage in the design process, aided by the use of manual test planning aids such as GDFT-Nets 3. These tools, which verify the correctness of proposed plans, are only useful if the designer has a good background knowledge of BIST and other DFT techniques. To provide the ASIC designer with the advantages of BISTwhile avoiding its many pitfalls can be difficult. It can be done by consultation with a BIST expert, but this is often impractical. The solution could lie in the use of knowledge-based system (KBS) techniques to provide BIST expertise as an integrated part of the VLSI design system. Others have proposed tools based on KBS methods that attempt to plan the application of testability with special emphasis on BIST. The most relevant of these to the present work is the TDES system developed at the University of Southern California, USA4. This system is oriented towards the concept of 'design styles', where well known architectural features can be matched to testability schemes. These testability schemes, known as testable design methodologies (TDMs), work within a framework of knowledge that relates structural, behavioural, quantitative and qualitative aspects of the circuit. The TDM is thus a template for DFT schemes such as scan path, BILBO, LSSD or the variety of BIST methods proposed for programmable logic arrays and RAMs. The aim of the tool is to partition a structural block description of the IC into a set of kernels or testable units, each with one or more TDMs. Identifying testable units within the design is the first task. This is followed by matching of units to TDMs. To achieve matching it is necessary to use the concept of 'I' paths, which are simple transparent paths that can be used to link testable units to test resources. The software is based on the use of frames and has been implemented in LISP as part of Adam, an advanced design automation system developed at the University of Southern California s. Of the other approaches to KBS test strategy planning, the Excat system 6 seems to follow a similar approach to TDES, using PROLOGas the programming paradigm. A third system proposed by GTE Laboratories is oriented towards a silicon compiler called Silc. This approach permits a

0141-9331/87/01035-06 $03.00 © 1987 Butterworth & Co. (Publishers) Ltd Vol 11 No 1 January/February 1987

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much closer link between the DFT methods used and the synthesis of the IC. In particular, features such as programmable logic arrays are implemented as cells with self-test built in at the cell level. A system known as Testpert is used to support the proposed DFT method 7. The BIST expert system reported here is based on a high-level circuit description that is available early in the design process. This enables the designer to incorporate test equipment into the design before specifying the lowlevel implementation, rather than making ad hoc alterations to an otherwise complete design. Another important feature is that the use of floor-plan-level circuit descriptions enables designers to specify any block in terms of its complete behaviour. This approach prevents the imposition of a rigid design methodology, whilst being general enough to allow for special cases, e.g. where a particular set of vectors can be shown to provide a complete test. STRATEGY

As an initial step the tool examines the test needs of the cells within the circuit and identifies the internal test resources that exist or could be inserted at low cost. The principal resources considered are registers, which may be converted to other forms with test capabilities, such as built-in logic block observers (BILBOs), multiple-input shift registers (MISRs) and linear feedback shift registers (LFSRs). From the knowledge derived, various plans can be formulated for the test of cells within the circuit. The plans are based on matching the test needs of a cell to the resources available with reference to measures of the global utility of each resource. The plans are constructed to meet the constraints imposed by the designer and achieve a balance between area penalty and test time, each plan satisfying the constraints in different ways (Figure 1). From the population of possible plans, proposals for design modifications are given to the designer. From these the designer can select a suitable proposal that best matches other-design considerations.

object-oriented, rule-based, procedurai and ~i({~,.-~.oriented programming. The object-oriented paradigm is implemented as ar~ inheritance hierarchy of class definitions in which classes contain variables (data) and methods (program). Variables and methods are inherited by descendants of the (:lass which holds their definition, and variables may be given default values, which are also inherited. An objectoriented system operates by creating multiple instances of classes and sending messages between them. When a message is received by an instance of a class it invokes one of its methods, which is either a set of production rules or a piece of LISPcode. Methods may examine or change the values of variables, do some processing or send new messages.

I M P L E M E N T A T I O N IN LOOPS

The BIST design tool has been developed in a modular and incremental fashion (Figure 2) and is based on the object-oriented paradigm described above, which was used to model the block library (Figure 3). Instances of classes in the library are used to represent the physical structure of circuits. Their methods represent block behaviour, including how they are tested and how they propagate tests. Circuits and tests are represented at a high level of abstraction. Circuit descriptions are at the floor plan level with no low-level implementation details. Tests are

User

H

Circuit design

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J Search routines O V E R V I E W OF LOOPS

The LISPobject-oriented programming system (LOOPS) 8 is a multiparadigm programming environment supporting

FT~ Population of legaltest plans !!!!!!!'~'! Populationof planspresentedby system to designer

J Time andarea constraints

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d Test time b Constraints on time and area overhead

Figure 2.

Major components of the system

Microprocessors and Microsystems

ALUs

the tests for the multiplier are found by sending the message

Buses

Joins Multipliers MUXes RAMs

(<-MULTIPLIER SelectTests)

~ Library

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/

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Figure 3. A portion of the inheritance hierarchy for the block library specified in terms of test types or 'test tokens', e.g. exhaustive or pseudorandom. This is in line with the test tokens used in GDFT-Nets 3 to represent test data in symbolic form, rather than in terms of actual vector sequences. Individual blocks in a circuit can be sent messages to find which test tokens can be applied to them and whether they can propagate a particular test token between their inputs and outputs. Instances of a new class, 'Circuits', record which blocks are in a particular circuit description and provide highlevel control; to distinguish between a 'circuit' as a structural description in terms of individual blocks and a 'Circuit' as an instance of a class capable of viewing the relationships between the blocks, the latter will be referred to with an initial capital letter. A Circuit can ask blocks how they can be tested and knows how to apply these tests to blocks by searching for test resources. The search process involves propagating test tokens through the circuit, noting the resources found. Test resources are registers which can be used to generate test data or collect signatures. Primary ports to the circuits may also be used as test resources, allowing the use of some external test equipment as specified by the user. Registers that cannot be used in their current form may be transformed to blocks with different BIST properties, e.g. BILBOs, LFSRsor MISRs, although primary ports have no transformations that can be applied to them.

resulting in a list of appropriate tests for the block. One of these is a pseudorandom test which is applied by propagating pseudorandom test tokens through the circuit from the input connected to T (IN1) and the input connected to D-Bus (IN2) in turn, noting each resource which can generate the test tokens. The tokens resulting from applying a pseudorandom test to IN1 and IN2 must also be propagated from the output of the multiplier (OUT) to a collector via P. The tokens can be propagated until either the maximum depth of search is reached or propagation is attempted through a block not translucent or transparent to the token. The maximum depth of search limits the distance that test resources can be from the block under test and is expressed in terms of the number of functional blocks through which tests must be propagated. Translucency implies a one-to-one mapping between the vectors which compose the token applied to the inputs and those appearing on the outputs. This is taken to mean that translucency to, for example, pseudorandom tokens ensures that if pseudorandom sequences are applied to the inputs to a block, pseudorandom sequences will appear on its outputs. Transparency, a special case of translucency, indicates that the input vectors will be reproduced in identical sequence on the outputs, possibly after some delay. The concept of translucency is a significant extension to the simple transparency associated with the I paths of the TDES system 4. Each block in the search path is examined to see if it could be a useful test resource and, if so, the results are stored in a test record. This shows the path between the resource and the port under test and the transformations which could be applied to the resource, e.g. conversion of a register to a BILBO. Also stored is a measure of the desirability of using the resource to test the port in question, based on the distance from the port. In the example circuit, the potential resources are T, P, AR0, AR1, Data, Address and Acc. In propagating pseudorandom vectors from port IN1 of the multiplier, the Circuit will search from the port to T,

/

16

tl6 T([6) Multiplier

ARI (t6)[

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DataRAM (144x [6) INITIAL CIRCUIT ANALYSIS In analysing a circuit description, a Circuit interrogates each block in turn to find which types of test could be applied to it. Each test in this list is applied to the block, which involves propagation of appropriate tokens through the circuit from each port of the block, noting appropriate resources which are found. In the circuit shown in Figure 4

Vol 11 No 1 January/February 1987

Data I Shifter,(0'1'41 IJ,16 tl6Data (0] bus Figure 4. A typical circuit block diagram (adapted from Reference 9)

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noting that T could be used as a resource by producing a test record of the form Resource :T Path : (Multiplier T) Weighting :5 Transformations : (BILBO LFSR) This indicates that T could be used and has a high weighting with respect to port IN1. It also indicates, through the presence of suggested transformations, that the resource would need to be altered to perform the necessaw function. The Circuit now attempts to propagate the token further, finding AR0 and AR1 via the D-bus, before propagating to Acc. (a resource) and ALU. If the limit on the depth of search has now been reached the Circuit backtracks until further paths are found which have not yet been explored. In this case the search would carry on through Shifter(0, 1, 4) and on to Acc. again. The Circuit creates a further record, backtracks to the D-bus once again and searches forward to the final resource to be discovered, which is Data. This gives a total of five potential resources, recorded by six test records, which may be used to generate a 16-bit pseudorandom test token for IN1. The sixth test record indicates two alternative paths for reaching Acc., one being longer than the other, giving rise to a lower weighting. The Circuit next examines IN2 and attempts to propagate pseudorandom tokens from this port. The results for this port are very similar to those for IN1 except that T cannot be used, so five records are obtained instead of six. The search for a test collector for the results appearing on OUT examines P (a resource), the multiplexer, the ALU and Acc. (a resource) before reaching the D-bus. At this point the system finds itself facing the problem of trying to propagate a 32-bit vector along a 16bit bus; it is unable to cope with this so it backtracks to try the other route through the shifter, with the same result. All possible paths have now been explored and the search is finished, with just two test records having been created. A complete test list for a block shows the test token applied, its length in terms ofthe number of test vectors to be applied and a list of test records for each port of the block. For the example given above this will be Test : pseudorandom Length : 2^ 16 Generate:(IN1 L1 IN2 L2) Collect : (OUT L3) where L1 is a list of the six test records found during the search, L2 a list of five records and L3 a list of two. Each block using a resource to generate or collect a particular test token contributes exactly once to a global weighting, which is a measure of how many different blocks could make use of the resource. In the example the multiplier would contribute just once to the global weighting showing Acc. to be a generator of pseudorandom tests, although Acc. appears in four of the test records, two for IN1 and two for IN2. In addition, the weighting as a collector would be increased as Acc. appears in the test records for OUT. Each resource may have several global weightings as a generator of different test tokens as well as a single weighting as a collector, since different types of resource may be needed to generate different tokens; in the signature analysis technique, however, a single resource may collect responses to any test token. These weightings

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may be combined effectively during test plan construction be selecting a transformation capable of performing alJ required functions. For example, a particular register ma~+ have a weighting for use as a pseudorandom test generator, a separate weighting as a generator of exhaustive tests and a third weighting as a test collector. Each block which can potentially use the resource in one of these capacities will contribute once only to that weighting, regardless of the number of individual test records for the block naming the resource in that capacity. This gives a measure of the global utility of the resources and some indication of the potential for minimizing area overhead.

BUILDING CIRCUIT TEST PLANS After the initial analysis the system must make proposals on how to incorporate BIST into the circuit. There are a number of possible approaches and one area of study during the present project has been an examination of appropriate methods for doing this, with particular reference to artificial intelligence (AI) planning techniques 1°. These include Interplan ~1, Waldinger's system 12, Molgen 13 and Nonlin TM. The first method developed is presented below and concentrates largely on the BILBO-based style of testing. In parallel with this work we have also been looking at the incorporation of alternative BIST strategies based on scan path and microprogrammed test techniques. Prior to the construction of test plans, the user must specify constraints on test time and the maximum area penalty for incorporating BIST equipment into the circuit. The general aim of the system is to minimize the amount of additional BIST equipment and to balance this against the desirability of a high degree of concurrent testing. The system should be able to present a range of test plans which satisfy these aims in different ways, some offering low test times with high area overhead and some with low area overhead but long test times (Figure 1). All will satisfy the user's design constraints. A member of this population of test plans is developed by selecting a seed resource on the basis of the global weightings calculated previously. This resource is chosen with reference to the block requiring the longest test time as it has the highest potential for concurrent testing. The test records for this block are examined to find which potentially useful resource has the highest global weighting. Once the individual test plan has been seeded with a test record, other records are inserted until the test plan contains one record for each port to the block. The insertion of a test record into an individual plan is constrained by the competition between all ports for paths and resources, as determined by comparison of the named paths with the protection set on each block already used in the test. In the above example the block with the longest test time is the arithmetic logic unit (ALU); this has just three test records associated with it for a pseudorandom test -P could be used to generate vectors for IN2, Acc. for IN1, and Acc. could be used to collect vectors from OUT. As both IN1 and OUT attempt to use Acc. (the resource with both the highest global and highest local weighting) and there are no other possibilities, the conflict indicates that a new resource must be added to the circuit. The Circuit must decide between Acc. as a generator and Acc. as a collector, and the solution is based on the fact that

Microprocessors and Microsystems

\ I

t

it,6

l6

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t

l6

T(16)

I

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II

P(32)

I

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32 / 32

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~32 Acc. 32

I

• 32

I

/

Shift C), I ,4

16

D - bus

Figure 5. A BIST proposal, with insertion of register 'New' to test the ALU and IN1. ARO and Tare converted to LFSRs and Acc. is converted to an MISR

inserting a generator is cheaper than inserting a collector. The system proposes an extra register multiplexed onto IN1 to generate the vectors and converts Acc. to an MISR (Figure 5). This solution leads to a commitment to use P as a pseudorandom generator, with a minimum requirement of converting it to an LFSR,which results in a contribution to area overhead. If the proposal would violate the constraint the user has set on area overhead then the system must either find an alternative solution or, as in the present case, indicate that no solution can be found. Having made a commitment to a particular set of resources the system increases the global weighting for each of them, to increase the chances of using the resources to test other blocks. Each individual test plan is added to the circuit plans subject to similar constraints on resource sharing, except that in the present case it is test concurrency that is determined by degree of sharing. If the plan developed is not acceptable to the user then some other plan will be developed by selecting seed resources having lower global weightings. The next stage for this example is to select the remaining block with the longest test time, here the multiplier. The test for this makes use of Acc. as a collector, removing the need for additional area overhead but increasing the overall test time due to sharing of resources, which prevents the ALU and multiplier from being tested concurrently. The multiplier also uses T and ARO to generate tests, converting them to other forms. At this point, 'smarter' test strategies would allow for concurrent testing of the multiplier and ALU by noting

Vol 11 No 1 January/February 1987

that the multiplier can be tested almost as a side effect of testing the ALU. A typical strategy would allow for T to be expanded to a 32-bit LFSR to generate pseudorandom tokens for both INI and IN2 of the multiplier, with the insertion of an LFSR as above for INI of the ALU. The results of testing both blocks would be collected as a single signature using converted Acc. (Figure 6).

FUTURE WORK Additional work will involve a study of the relationship between the distribution of measures of global usefulness mentioned in the previous section and the suitability of circuits for BIST. Longer-term plans will aim to integrate the tool with other CAD systems through the use of some common hardware description language (HDL). Circuit capture would then be done using the HDL and the description would be translated into a form suitable for the systems presented. After proposals on design changes are accepted the modified circuit would be translated back to the HDL for processing by other tools. A likely method for performing this translation will be to attach standard HDL descriptions to the classes in the block library. An analysis of the original H DL at the highest level of abstraction will produce a description suitable for processing by the BIST tool. After the circuit has been modified to produce a self-testing version, the HDL descriptions attached to the library will be used to translate the circuit back for processing by other CAD tools which use the HDL.

\ l6 tT(32)

,16

Ii

Shift

._J L 16 n

."

P(32)

32 /

32

32

"

I

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~32 ~32

Acc.

I ~32I g-t sp,, 2 t---

/"

D- bus

Figure 6. A BIST proposal' with insertion of register "New' to test the ALU and IN1. T is converted to a 32-bit LFSRand Ace. to an MISR, allowing for concurrent testing of the multiplier and ALU

39

As part of the UK's Alvey programme a major demonstrator based on an original digital signal processing IC will be studied 15. It is hoped that the published results of this work will include a detailed analysis of the economics of self-test related to previous work 16.

CONCLUSIONS The system presented would have a major impact on the test costs associated with chip production by enabling BIST to be integrated into designs with little effort from the designer. The use of BIST based on the generation of pseudorandom and exhaustive test patterns means that the test generation costs normally incurred are reduced. By incorporating BIST equipment into the circuit, the sophistication and cost of the external test equipment needed is reduced. These factors alone reduce test costs but, in addition, the design process itself may be faster as there is potential for the rejection of untestable designs by test engineers, resulting in fewer design iterations. By approaching the problem at a very high level the tools can be used to plan the application of BIST. The system offers a high degree of flexibility and so avoids imposing a rigid design methodology. This is facilitated by the use of the multiparadigm LOOPS environment to operate on an integrated description of circuits in terms of both their structure and their behaviour. In particular, the description of circuits in terms of both the individual components and the circuit as a whole enables the system to formulate test plans atthe local level in terms of their global context. The implications of this are that the system will be able to achieve a balance between the need for low area penalties for introducing BIST equipment into the circuit and the desirability of maximizing test concurrency to reduce test times.

A C K N O W L E D G E M ENTS The work presented has been carried out as part of Alvey project CAD 004. The authors would like to acknowledge the contributions made by P Varma of GEC Research, UK, K Totten of British Telecom Research Laboratories, Ipswich, UK, P Mossom of STL, Harlow, UK, and S Hodgson of ICL, Manchester, UK. Acknowledgement is also made to the director of research at British Telecom for permission to publish the paper.

REFERENCES 1 Murray, A F, Denyer, P B and Renshaw, D 'Selftesting in bit serial VLSI parts: high fault coverage at low cost' Proc. 1983 ITC IEEE, Washington, USA (1983) pp 260-268 2 Smith, K 'Plessey custom chips will test themselves' Electronics Week. (25 March 1985) pp 17-18 3 Croft, R M and Baker, K 'Global testability tools for CATE' lEE Colloq. DFT, London, UK (November 1985) 4 Abadir, M S and Breuer, M A 'A knowledge-based system for designing testable VLSI chips' IEEE Des. Test Comput. Vol 2 No 4 (August 1985) pp 56-69 5 Granacki, J, Knapp, D and Parker, A 'The ADAM advanced design automation system: overview, planner and natural-language interface' Proc. 22nd Design Automation Conf., Las Vegas, NV, USA (June 1985)

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6 Mangir, T E 'EXCAT: an expert system t~r testabi~ , design of VLSr 1985 Int. Symp. VLSI fechnology. Systems and Applications, Papier, Taiwan (May 1985) 7 Fung, H S and Hirschorn, S 'An automatic DFT system for the SILC silicon compiler' IEEE Des. Test Comput. Vol 3 No 1 (February 1986) pp 45-57 8 Bobrow, D G and Stefik, M The LOOPS manual Xerox, Palo Alto, CA, USA (1983) 9 TMS32010 users guide Texas Instruments, Houston, TX, USA 10 Cohen, P R and Feigenbaum, E A The handbook of artificial intelligence, Vol 3 Pitman, London, UK (1982) 11 Tale, A 'INTERPLAN: a plan generation system which can deal with interactions between goals' Memorandum MIP-R-109 Machine Intelligence Research Unit, University of Edinburgh, UK 12 Waldinger, R 'Achieving several goals simultaneously' in Elcock, E W and Michie, D (Eds) Machine intelligence 8 Ellis Horwood, London, UK (1977) 13 Slefik, M 'Planning with constraints' Artificial Intelligence, 16 (1981) pp 111-140 14 Tale, A 'Project planning using a hierarchic nonqinear planner' Research Report No 25 Dept of Artificial Intelligence, University of Edinburgh, UK 15 Pickvance, R E 'Digital signal processor nimbly jumps over CPU overhead hurdles' Electron. Des. (20 September 1984) pp 261-72 16 Varma, P, Ambler, A P and Baker, K 'An analysis of the economics of self-test' 1984 Int. Test Conf. Philadelphia, PA, USA (October 1984) pp 20-30

N A Jones graduated with honours in psychology from Sheffield University, UK, in 1983. He went on to complete an MSc in information technology (intelligent knowledge based systems) with the Department of Artificial Intelligence, University of Edinburgh, UK, in 1984. He joined GEC Hirst Research Centre, UK, in 1984 as a member of the Artificial Intelligence Group and later joined the CAD Research Group in the Integrated Systems Design Laboratory. Since this time he has been involved mainly with the application of advanced programming techniques to the design of self-testing VLSI. .....................................

K Baker graduated with honours in electrical and electronic engineering from Kingston Polytechnic, UK, in 1979 while on an undergraduate apprenticeship with EMI Electronics, and completed an MSc by dissertation in medical electronics at the ~ University of Essex, UK, in 1980. He joined the GEC Hirst Research Centre, UK, in 1981 to work on various aspects of VLSI design and testing. Since 1984 he has been a group leader responsible for CAD research and design testability.

Microprocessors and Microsystems