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Lag compensation errors in active power filters based on DSP controllers
M INING SCIENCE AND TECHNOLOGY Mining Science and Technology 20 (2010) 0312–0316
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Lag compensation errors in active power filters based on DSP controllers WANG Xuedan1,2,*, JIANG Jianguo1, GAO Baichen2 1
2
School of Information and Electrical Engineering, China University of Mining & Technology, Xuzhou 221008, China School of Electrical and Information Engineering, Heilongjiang Institute of Science and Technology, Harbin 150027, China
Abstract: The growing problems of harmonic pollution on coal mine power lines caused by high-power DC drive systems has increased the use of active power filters. We analyzed compensation errors caused by the time lag in the detecting circuits of an active power filter based on DSP control. We derived a mathematical model for the compensation error starting from the error estimation when a single distortion frequency is present. This model was then extended to the case where multiple frequencies are present in the distortion. A formula for a general theory of compensation error with fixed load and fixed lag time is presented. The theoretical analysis and experimental results show that the delay time of an active power filter mainly arises from the sampling time. Lower sampling frequencies introduce larger compensation errors in the active power filter reference current. Keywords: active power filter; digital signal processing; modeling; compensation error
1
Introduction
Power line harmonics and reactive currents in coal mine power systems present serious problems in terms of power quality and grid stability and safety. Poor quality power can damage various electronic devices used in the mine. High power DC drives fed by converters are the most important source of harmonics and reactive currents on the grid. An Adaptive Power Filter (APF) may be used to attenuate harmonics and neutralize reactive currents through dynamic compensation. This is the best choice for a power grid[1-9]. The use of a Digital Signal Processor (DSP) to calculate the reference current provides many advantages for APF design[10-11]. The lag time involved when the DSP is detecting and processing signals is usually ignored because of the high working clock frequency and small sampling time. But in practice some lag time is caused by the sampling, calculating and A/D conversion that can not be ignored. If the lag is ignored a step input will have a lag after being converted into the output signal. Lower sampling frequencies cause bigger lags. But improReceived 02 August 2009; accepted 15 October 2009 *Corresponding author. Tel: 86 13895787729 E-mail address: [email protected] doi: 10.1016/S1674-5264(09)60204-0
ving the sampling time, thus increasing the number of samples, will decrease the processing speed. The actual compensation signals lag an ideal signal and will cause unsatisfactory system compensation or will reduce the capability of the system to compensate the power line noise[12-16]. We derived mathematical models of compensating error theory starting from a single distortion frequency and extended to error estimation for multiple distortion frequencies. We present a formula for calculating general compensation errors with fixed loads and fixed lag time. We also analyzed the influence on the APF compensation caused by a DSP digital controller’s processing lag time. Finally, experimental results show the validity of the error model.
2 Theoretical estimation of compensation error Some assumptions: the system used is a 3-ij balanced line; calculations may be done on a single phase; the system is in a steady state and dynamic changes can be neglected; there exists a single-phase and frequency voltage source; all distortions are caused by a fundamental, or higher multiple, frequency current source; and, the impedance of the power source and the transmission line can be ignored. The dynamic compensator is modeled by a
Lag compensation errors in active power filters based on DSP controllers
current source and the reference compensating current signals are superposed with no errors. 2.1
Error estimation for a single distortion frequency
A given supply voltage is:
u1 (t ) = sin(2ʌft )
(1)
The distortion current with k-order harmonics is: ih (t ) = sin(2ʌfht ) (2) According to Fryze power theory the compensation current ic(t) required to compensate ih(t) is:
ic (t ) = −ih (t ) = − sin(2ʌfht )
This shows that the assumption of only a single harmonic voltage source is correct and that ignoring the impedance of the power source and transmission line is appropriate. Using Eq.(9) to find the error percentage given different harmonics and time lags provides the data shown in Fig. 1. Consider point A: the 21st harmonic compensation has a lag time of 90 ȝs and the corresponding error percentage is 60%, which means only 40% of the reactive power caused by harmonics is compensated.
(3)
The reference compensation current, icd, of the compensator has a lag time, td, relative to the actual compensation current, ic. The current generated by the compensator is:
icd (t ) = − sin(2ʌfht − ϕ h )
(4)
where ϕh is the phase lag time td of the h order harmonics in a system with a 50 Hz fundamental frequency.
ϕh =
2ʌhtd 0.02
rad
iline (t ) = ih (t ) + icd (t ) + cos(2ʌfht ) ⋅ sinϕh
1 T (u1 (t )) 2 ⋅ (ih (t )) 2 ⋅ dt = 0.5 T ³0
I n = ( I1 ) 2 + (I 5 ) 2 + (I 7 ) 2
1 T (u1 (t )) 2 ⋅ (iline (t )) 2 ⋅ dt T ³0 2
N after ⋅ 100 = 2 − 2 ⋅ cos ϕ h ⋅ 100 N before
(10)
where I1 is the RMS value of the fundamental frequency current, which has a 90° phase relative to the voltage source; I5 the RMS value of the 5th harmonic current; and I7 the RMS value of the 7th harmonic current. The magnitudes of I5 and I7 are respectively:
I5 =
I1 I1 , I7 = K7 K5
(11)
The compensation error may then be calculated by the following formula:
(8)
So the compensation error percentage is: %error =
Compensation error estimation for multifrequency distortion
(7)
The reactive power after compensation is:
= 0.5 ⋅ (1 − cos ϕh ) + (sin ϕh )
2.2
(6)
According to Fryze power theory the compensation error can be defined as the proportion of reactive power after compensation to reactive power before compensation. The reactive power before compensation is:
2
Fig. 1 Error percentage for different harmonics and different lag times
The RMS value of a reactive current, In, is given by:
= sin(2ʌfht ) ⋅ (1 − cosϕh )
N after =
(ȝs)
(5)
The line current after compensation is the mixed distortion and compensator currents:
N before =
313
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WANG Xuedan et al
(9)
According to Eq.(9) the compensation error percentage is the Root-Mean-Square (RMS) value of the active power current after compensation divided by the RMS of the distortion current before compensation.
%error = 100
(2 − 2cos ϕ1 ) +
2 − 2cos ϕ5 2 − 2cos ϕ7 + ( K5 )2 ( K 7 )2 2
§ 1 · § 1 · 1+ ¨ ¸ + ¨ ¸ © K5 ¹ © K 7 ¹
2
(12) The total compensation error is the square of the summation of the various frequency components divided by the RMS value of the magnitude of the different currents.
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Analysis and calculations of the data acquisition system
A block diagram of the data acquisition system is shown as Fig. 2. &DOFXODWLRQXQLW
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Fig. 2 Block diagram of the data acquisition system
3.1 Algorithms of data acquisition and processing The active power, P, is the average value of the digital load current multiplied by the voltage. The RMS value of the load voltage is Urms and for a single phase we have:
P=
1 N
U rms =
N −1
¦ u(n)i(n)
(13)
n =0
1 N
N −1
¦ (u (n))
2
(14)
n=0
The active power current can be calculated by Eqs.(15) and (16), where Ge is the effective conductance of the loads and ia(n) is the digital active power current: Ge =
2 U rms (n) = U rms (n − 1) −
(18)
1 2 (u (n) − u 2 (n − N )) N
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P 2 U rms
i a ( n ) = Ge u ( n )
(15) (16)
P and Urms are sampled 128 times during a period, so N in Eqs.(13) and (14) is 128. These values (including Ge and ia) will be recalculated after each sample and so they will set up a moving window or a continuous value. To compensate the variable load as rapidly as possible the compensation error current should be the load current minus the active damping current. So the reference compensation current (only in a single phase) is:
ic (n) = i (n) − ia (n)
(17) The continuous value should have the nature of a real-time signal in the digital processor. Only the newest sample and oldest sample (of the historical 128 samples) are used to renew Ge and Urms at each sampling. The recurrence formula is:
The lag time caused by signal detection and processing consists of several parts: the optically isolated detector (a Hall effect sensor) provides a signal with a 10 μs delay; the A/D transfer requires 12.5 μs; calculation of the TMS320F240 reference signal requires 4 μs; the D/A transfer ring has a 2 μs delay. The total processing time requires 28.5 μs, which is denoted by Tp. If the sampling time is 6.4 kHz there will be 128 samples during one period of a 50 Hz line cycle. The sampling period itself is 156 μs and is denoted by Ts. The reference compensation current in the processor renews once each sampling period (the sampling period at 6.4 kHz is 156 μs). To avoid the time delay of one period caused by sensing the voltage, the reference value is obtained by detecting the current and subtracting the active power current. The reference value is constant during the sampling period (156 μs) and so the reference output is a step function updated every 156 μs. The liner approximation of the sampling process is shown in Fig. 3. An ideal compensation current in a high di/dt area is shown in Fig. 3 where it is denoted by ic*(t). The sampling time of the load current (the line current without compensation) and the voltage are denoted by the vertical lines along the time axis. The calculation of compensating current reference signals can only be done after each sampling. After this calculation the digital reference appears at the output terminal, which is denoted in Fig. 3a by a dashed line. The sampling period is Ts and the processing time is Tp. The delayed reference output is denoted by the dashed line in Fig. 3b. The delay error may be defined as the vertical distance between the load current and lagging reference (a difference in current magnitudes). The reason why we can do this is that, in this case, it is assumed that all the currents are compensated. Because the reference has a step characteristic the error will change between a maximum and minimum value as shown in Fig. 3b. These errors can be calculated as:
emin = r ⋅ Tp emax = r ⋅ (Ts + Tp )
(20)
(21) where r is the slope of the load current being sampled.
WANG Xuedan et al
Lag compensation errors in active power filters based on DSP controllers
after compensation. The line current after compensation, the line to neutral voltage and the frequency spectrum of the line current are shown in Fig. 5 for three different delay times.
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Fig. 3 Corresponding error between the lagging reference output and time
2
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Results and discussion
The experiment equipmental was a three-phase 380 V Insulated Gate Bipolar Transistor (IGBT) and a 10 kVA Pulse-Width Modulation (PWM) converter. The loads were devices with low di/dt capability, which makes it easy to follow the reference compensation current from the converter as accurately as possible. The time delay compensation error from detection and calculation are separated from the error caused by the dynamic limitations of the power converters themselves. The loads were three filters that can compensate 3rd, 7th or 9th harmonics. During the experiment slight changes of the processing time and sampling frequency were made so that three lag times were observed. These were approximately 70, 90 and 140 μs. This allowed a theoretical check for errors caused by different delay times. The line condition before compensation, which is the load current and the voltage of the line referred to the neutral point, are shown in Fig. 4a. The corresponding frequency spectrum of the current is shown in Fig. 4b. The 50 Hz current component leads the voltage by almost 90 degrees. Hence reactive power is the total line current, or the line current should be 0
7LPH V
+DUPRQLFVRUGHU
(a) 70 ȝs delay
(b) 90 ȝs delay
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Ts + 2Tp
The step reference signal will generate an average error after filtering of: e + emin eave = max (22) 2 The average lag time will then be: tave =
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(c) 140 ȝs delay
Fig. 5 During compensation
The results of the three average lag times are shown in Table 1 for convenient analysis and comparison. The harmonic magnitude, relative to the fundamental frequency current, and the theoretical errors calculated by Eq.(9) for the three delay times are given in Table 1. The total theoretical error calculated by Eq.(12) and the total experimental error (the RMS value of harmonics detected by experimental equipment) are given in Table 2.
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Mining Science and Technology
Table 1 Relative amplitudes and theoretical errors for different harmonics
5
Relative time 0.1173
Error (70 ȝs) (%) 11
Error (90 ȝs) (%) 14.1
Error (140 ȝs) (%) 21.9
7
0.0895
15.4
19.8
30.7
9
0.1588
19.8
25.4
39.3
h
Table 2 Total theoretical and experimental errors Lag time (ȝs)
Theoretical values (%)
Observed values (%)
70
16.9
17.7
90
21.7
25.7
140
33.6
39.2
The experimental results show that the larger the delay time the lower the compensation efficiency. The experimental total compensation errors are almost equal to the theoretically estimated values, which mean that the compensator can compensate 82.3% of the reactive power with a 70 μs time delay. But only 60.8% of the reactive power can be compensated a 140 μs time delay. The frequency spectrum in Fig. 5c shows that the magnitude of the 9th harmonic increases significantly as the delay becomes longer.
5
Acknowledgements Financial support for this work, provided by the National Basic Research Program of China (No.
No.2
2005CB221505), is gratefully acknowledged.
References [1]
[2]
[3]
[4] [5] [6]
[7]
Conclusions
1) A mathematical model of compensation error was presented. The compensation error at a single distortion frequency can be calculated as the RMS value of the reactive current after compensation divided by the RMS value of the reactive current before compensation. The total compensation error for multiple frequency distortion can be calculated as the square of sums of all the different frequency components divided by the RMS value of the different current magnitudes. 2) The lag time of an APF based on a DSP is mainly caused by the sampling time: the lower the sampling frequency the bigger the error in compensation relative to the APF reference current. 3) A radical solution to the problem has not been found but a method of quantitative analysis of compensation error from time delays due to detection and calculation was presented. The validity of active power compensation when considering the design of digital signal processing systems was illustrated. This is important for the design of digital signal processing equipment.
Vol.20
[8]
[9]
[10] [11]
[12]
[13] [14]
[15] [16]
Sun J P, Ma F Y, Li C. Improved complex filter applied in enhancing EFT/B immunity at a coal mine monitoring substation. Mining Science and Technology, 2008, 18(1): 22-26. Zhang W, Han X, Sun J P. Mathematical model of electric hydraulic and powered support control system at a plough mining face. Mining Science and Technology, 2008, 18(1): 55-58. Lin H C. Intelligent neural-network-based adaptive power-line conditioner for real-time harmonics filtering. In: IEE Proceedings-Generation, Transmission and Distribution, 2004, 151(5): 561-567. Sun Z, Wang N C, Xu W B. Parallel hybrid active power filter with good cost performance. In: Proceedings of the CSEE, 2007, 27(36): 79-84. (In Chinese) Tan T Y, Luo A, Tang X, Tu C M. Development of high-capacity hybrid power filter. In: Proceedings of the CSEE, 2004, 24(3): 41-45. (In Chinese) Yu K C, Watson N R, Arrillaga J. An adaptive kalman filter for dynamic harmonic state estimation and harmonic injection tracking. IEEE Transactions on Power Delivery, 2005, 20(2): 1577-1584. Snaae R, Loi N, Xu J. Perofmrnace evaluation of hnnaonies detection methods appilied to harmonies compensation in persene of common power quality problems. Mathematics and Computers in Simulation, 2003, 63(3): 363-375. Jintakosonwit P, Fujita H, Akagi H. Control and performance of a fully digital controlled shunt active filter for installation on a power distribution system. IEEE Transactions Power Electronics, 2002, 17(1): 132-140. Wadan K, Fujita H, Akagi. Consideration of a shunt active filter based on voltage detection for installation on a long distribution feeder. IEEE Transactions Industry Applications, 2002, 38(4): 1123-1130. Cui J X, Cai W H. Direct torque control of asynchronous machine and its application using DSP. Journal of China Coal Society, 2007, 32(9): 1002-1005. (In Chinese) Marshall D A. Compensation of Distortion in Three Phase Electric Power Networks by Hybrid Dynamic Filters [Ph.D. dissertation]. Johannesburg: Rand Afrikaans University, 1990. Soliman S A, Mantaway A H, El-Hawary M E. Simulated annealing optimization algorithm for power systems quality analysis. International Journal of Electrical Power and Energy Systems, 2004, 36(2): 1-36. Depenbrock M. The FBD-method, a general applicable tool for analyzing power relations. IEEE Trans Power System, 1993, 5(8): 381-387. Depenbrock M, Marshall D A, Wyk J D van. Formulating requirements for a universally applicable power theory as control algorithm in power consumption. ETEP, 1994, 7(4): 445-454. Roux W le, Wyk J D van. Modeling of distortion compensation ineffectivity in filters for nonactive power. IEEE Trans Industrial Electronics, 2001, 1(48): 91-100. Wang J H, Li H D, Wang L M. Direct power control system of three phase boost type PWM rectifiers. Proceedings of the CSEE, 2006, 26(18): 54-60. (In Chinese)
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Lag compensation errors in active power filters based on DSP controllers WANG Xuedan1,2,*, JIANG Jianguo1, GAO Baichen2 1
2
School of Information and Electrical Engineering, China University of Mining & Technology, Xuzhou 221008, China School of Electrical and Information Engineering, Heilongjiang Institute of Science and Technology, Harbin 150027, China
Abstract: The growing problems of harmonic pollution on coal mine power lines caused by high-power DC drive systems has increased the use of active power filters. We analyzed compensation errors caused by the time lag in the detecting circuits of an active power filter based on DSP control. We derived a mathematical model for the compensation error starting from the error estimation when a single distortion frequency is present. This model was then extended to the case where multiple frequencies are present in the distortion. A formula for a general theory of compensation error with fixed load and fixed lag time is presented. The theoretical analysis and experimental results show that the delay time of an active power filter mainly arises from the sampling time. Lower sampling frequencies introduce larger compensation errors in the active power filter reference current. Keywords: active power filter; digital signal processing; modeling; compensation error
1
Introduction
Power line harmonics and reactive currents in coal mine power systems present serious problems in terms of power quality and grid stability and safety. Poor quality power can damage various electronic devices used in the mine. High power DC drives fed by converters are the most important source of harmonics and reactive currents on the grid. An Adaptive Power Filter (APF) may be used to attenuate harmonics and neutralize reactive currents through dynamic compensation. This is the best choice for a power grid[1-9]. The use of a Digital Signal Processor (DSP) to calculate the reference current provides many advantages for APF design[10-11]. The lag time involved when the DSP is detecting and processing signals is usually ignored because of the high working clock frequency and small sampling time. But in practice some lag time is caused by the sampling, calculating and A/D conversion that can not be ignored. If the lag is ignored a step input will have a lag after being converted into the output signal. Lower sampling frequencies cause bigger lags. But improReceived 02 August 2009; accepted 15 October 2009 *Corresponding author. Tel: 86 13895787729 E-mail address: [email protected] doi: 10.1016/S1674-5264(09)60204-0
ving the sampling time, thus increasing the number of samples, will decrease the processing speed. The actual compensation signals lag an ideal signal and will cause unsatisfactory system compensation or will reduce the capability of the system to compensate the power line noise[12-16]. We derived mathematical models of compensating error theory starting from a single distortion frequency and extended to error estimation for multiple distortion frequencies. We present a formula for calculating general compensation errors with fixed loads and fixed lag time. We also analyzed the influence on the APF compensation caused by a DSP digital controller’s processing lag time. Finally, experimental results show the validity of the error model.
2 Theoretical estimation of compensation error Some assumptions: the system used is a 3-ij balanced line; calculations may be done on a single phase; the system is in a steady state and dynamic changes can be neglected; there exists a single-phase and frequency voltage source; all distortions are caused by a fundamental, or higher multiple, frequency current source; and, the impedance of the power source and the transmission line can be ignored. The dynamic compensator is modeled by a
Lag compensation errors in active power filters based on DSP controllers
current source and the reference compensating current signals are superposed with no errors. 2.1
Error estimation for a single distortion frequency
A given supply voltage is:
u1 (t ) = sin(2ʌft )
(1)
The distortion current with k-order harmonics is: ih (t ) = sin(2ʌfht ) (2) According to Fryze power theory the compensation current ic(t) required to compensate ih(t) is:
ic (t ) = −ih (t ) = − sin(2ʌfht )
This shows that the assumption of only a single harmonic voltage source is correct and that ignoring the impedance of the power source and transmission line is appropriate. Using Eq.(9) to find the error percentage given different harmonics and time lags provides the data shown in Fig. 1. Consider point A: the 21st harmonic compensation has a lag time of 90 ȝs and the corresponding error percentage is 60%, which means only 40% of the reactive power caused by harmonics is compensated.
(3)
The reference compensation current, icd, of the compensator has a lag time, td, relative to the actual compensation current, ic. The current generated by the compensator is:
icd (t ) = − sin(2ʌfht − ϕ h )
(4)
where ϕh is the phase lag time td of the h order harmonics in a system with a 50 Hz fundamental frequency.
ϕh =
2ʌhtd 0.02
rad
iline (t ) = ih (t ) + icd (t ) + cos(2ʌfht ) ⋅ sinϕh
1 T (u1 (t )) 2 ⋅ (ih (t )) 2 ⋅ dt = 0.5 T ³0
I n = ( I1 ) 2 + (I 5 ) 2 + (I 7 ) 2
1 T (u1 (t )) 2 ⋅ (iline (t )) 2 ⋅ dt T ³0 2
N after ⋅ 100 = 2 − 2 ⋅ cos ϕ h ⋅ 100 N before
(10)
where I1 is the RMS value of the fundamental frequency current, which has a 90° phase relative to the voltage source; I5 the RMS value of the 5th harmonic current; and I7 the RMS value of the 7th harmonic current. The magnitudes of I5 and I7 are respectively:
I5 =
I1 I1 , I7 = K7 K5
(11)
The compensation error may then be calculated by the following formula:
(8)
So the compensation error percentage is: %error =
Compensation error estimation for multifrequency distortion
(7)
The reactive power after compensation is:
= 0.5 ⋅ (1 − cos ϕh ) + (sin ϕh )
2.2
(6)
According to Fryze power theory the compensation error can be defined as the proportion of reactive power after compensation to reactive power before compensation. The reactive power before compensation is:
2
Fig. 1 Error percentage for different harmonics and different lag times
The RMS value of a reactive current, In, is given by:
= sin(2ʌfht ) ⋅ (1 − cosϕh )
N after =
(ȝs)
(5)
The line current after compensation is the mixed distortion and compensator currents:
N before =
313
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WANG Xuedan et al
(9)
According to Eq.(9) the compensation error percentage is the Root-Mean-Square (RMS) value of the active power current after compensation divided by the RMS of the distortion current before compensation.
%error = 100
(2 − 2cos ϕ1 ) +
2 − 2cos ϕ5 2 − 2cos ϕ7 + ( K5 )2 ( K 7 )2 2
§ 1 · § 1 · 1+ ¨ ¸ + ¨ ¸ © K5 ¹ © K 7 ¹
2
(12) The total compensation error is the square of the summation of the various frequency components divided by the RMS value of the magnitude of the different currents.
314
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Mining Science and Technology
Analysis and calculations of the data acquisition system
A block diagram of the data acquisition system is shown as Fig. 2. &DOFXODWLRQXQLW
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Fig. 2 Block diagram of the data acquisition system
3.1 Algorithms of data acquisition and processing The active power, P, is the average value of the digital load current multiplied by the voltage. The RMS value of the load voltage is Urms and for a single phase we have:
P=
1 N
U rms =
N −1
¦ u(n)i(n)
(13)
n =0
1 N
N −1
¦ (u (n))
2
(14)
n=0
The active power current can be calculated by Eqs.(15) and (16), where Ge is the effective conductance of the loads and ia(n) is the digital active power current: Ge =
2 U rms (n) = U rms (n − 1) −
(18)
1 2 (u (n) − u 2 (n − N )) N
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P 2 U rms
i a ( n ) = Ge u ( n )
(15) (16)
P and Urms are sampled 128 times during a period, so N in Eqs.(13) and (14) is 128. These values (including Ge and ia) will be recalculated after each sample and so they will set up a moving window or a continuous value. To compensate the variable load as rapidly as possible the compensation error current should be the load current minus the active damping current. So the reference compensation current (only in a single phase) is:
ic (n) = i (n) − ia (n)
(17) The continuous value should have the nature of a real-time signal in the digital processor. Only the newest sample and oldest sample (of the historical 128 samples) are used to renew Ge and Urms at each sampling. The recurrence formula is:
The lag time caused by signal detection and processing consists of several parts: the optically isolated detector (a Hall effect sensor) provides a signal with a 10 μs delay; the A/D transfer requires 12.5 μs; calculation of the TMS320F240 reference signal requires 4 μs; the D/A transfer ring has a 2 μs delay. The total processing time requires 28.5 μs, which is denoted by Tp. If the sampling time is 6.4 kHz there will be 128 samples during one period of a 50 Hz line cycle. The sampling period itself is 156 μs and is denoted by Ts. The reference compensation current in the processor renews once each sampling period (the sampling period at 6.4 kHz is 156 μs). To avoid the time delay of one period caused by sensing the voltage, the reference value is obtained by detecting the current and subtracting the active power current. The reference value is constant during the sampling period (156 μs) and so the reference output is a step function updated every 156 μs. The liner approximation of the sampling process is shown in Fig. 3. An ideal compensation current in a high di/dt area is shown in Fig. 3 where it is denoted by ic*(t). The sampling time of the load current (the line current without compensation) and the voltage are denoted by the vertical lines along the time axis. The calculation of compensating current reference signals can only be done after each sampling. After this calculation the digital reference appears at the output terminal, which is denoted in Fig. 3a by a dashed line. The sampling period is Ts and the processing time is Tp. The delayed reference output is denoted by the dashed line in Fig. 3b. The delay error may be defined as the vertical distance between the load current and lagging reference (a difference in current magnitudes). The reason why we can do this is that, in this case, it is assumed that all the currents are compensated. Because the reference has a step characteristic the error will change between a maximum and minimum value as shown in Fig. 3b. These errors can be calculated as:
emin = r ⋅ Tp emax = r ⋅ (Ts + Tp )
(20)
(21) where r is the slope of the load current being sampled.
WANG Xuedan et al
Lag compensation errors in active power filters based on DSP controllers
after compensation. The line current after compensation, the line to neutral voltage and the frequency spectrum of the line current are shown in Fig. 5 for three different delay times.
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(23)
Results and discussion
The experiment equipmental was a three-phase 380 V Insulated Gate Bipolar Transistor (IGBT) and a 10 kVA Pulse-Width Modulation (PWM) converter. The loads were devices with low di/dt capability, which makes it easy to follow the reference compensation current from the converter as accurately as possible. The time delay compensation error from detection and calculation are separated from the error caused by the dynamic limitations of the power converters themselves. The loads were three filters that can compensate 3rd, 7th or 9th harmonics. During the experiment slight changes of the processing time and sampling frequency were made so that three lag times were observed. These were approximately 70, 90 and 140 μs. This allowed a theoretical check for errors caused by different delay times. The line condition before compensation, which is the load current and the voltage of the line referred to the neutral point, are shown in Fig. 4a. The corresponding frequency spectrum of the current is shown in Fig. 4b. The 50 Hz current component leads the voltage by almost 90 degrees. Hence reactive power is the total line current, or the line current should be 0
7LPH V
+DUPRQLFVRUGHU
(a) 70 ȝs delay
(b) 90 ȝs delay
%ROWDJHFXUUHQW N9$
4
Ts + 2Tp
The step reference signal will generate an average error after filtering of: e + emin eave = max (22) 2 The average lag time will then be: tave =
/1YROWDJH
0DJ RI IXQGDPHQWDO
HPD[
0DJ RI IXQGDPHQWDO
&XUUHQW HUURU PDJQLWXGH
D
(c) 140 ȝs delay
Fig. 5 During compensation
The results of the three average lag times are shown in Table 1 for convenient analysis and comparison. The harmonic magnitude, relative to the fundamental frequency current, and the theoretical errors calculated by Eq.(9) for the three delay times are given in Table 1. The total theoretical error calculated by Eq.(12) and the total experimental error (the RMS value of harmonics detected by experimental equipment) are given in Table 2.
316
Mining Science and Technology
Table 1 Relative amplitudes and theoretical errors for different harmonics
5
Relative time 0.1173
Error (70 ȝs) (%) 11
Error (90 ȝs) (%) 14.1
Error (140 ȝs) (%) 21.9
7
0.0895
15.4
19.8
30.7
9
0.1588
19.8
25.4
39.3
h
Table 2 Total theoretical and experimental errors Lag time (ȝs)
Theoretical values (%)
Observed values (%)
70
16.9
17.7
90
21.7
25.7
140
33.6
39.2
The experimental results show that the larger the delay time the lower the compensation efficiency. The experimental total compensation errors are almost equal to the theoretically estimated values, which mean that the compensator can compensate 82.3% of the reactive power with a 70 μs time delay. But only 60.8% of the reactive power can be compensated a 140 μs time delay. The frequency spectrum in Fig. 5c shows that the magnitude of the 9th harmonic increases significantly as the delay becomes longer.
5
Acknowledgements Financial support for this work, provided by the National Basic Research Program of China (No.
No.2
2005CB221505), is gratefully acknowledged.
References [1]
[2]
[3]
[4] [5] [6]
[7]
Conclusions
1) A mathematical model of compensation error was presented. The compensation error at a single distortion frequency can be calculated as the RMS value of the reactive current after compensation divided by the RMS value of the reactive current before compensation. The total compensation error for multiple frequency distortion can be calculated as the square of sums of all the different frequency components divided by the RMS value of the different current magnitudes. 2) The lag time of an APF based on a DSP is mainly caused by the sampling time: the lower the sampling frequency the bigger the error in compensation relative to the APF reference current. 3) A radical solution to the problem has not been found but a method of quantitative analysis of compensation error from time delays due to detection and calculation was presented. The validity of active power compensation when considering the design of digital signal processing systems was illustrated. This is important for the design of digital signal processing equipment.
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[8]
[9]
[10] [11]
[12]
[13] [14]
[15] [16]
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