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Large step-down DC–DC converters with reduced current stress
Energy Conversion and Management 50 (2009) 232–239
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Energy Conversion and Management journal homepage: www.elsevier.com/locate/enconman
Large step-down DC–DC converters with reduced current stress Esam H. Ismail * Department of Electrical Engineering, College of Technological Studies, P.O. Box 35007, 36051 Al-Shaab, Kuwait
a r t i c l e
i n f o
Article history: Received 5 March 2008 Accepted 30 September 2008
Keywords: DC–DC power converters Quadratic converters Step-down converters Switched mode power supplies (SMPS)
a b s t r a c t In this paper, several DC–DC converters with large voltage step-down ratios are introduced. A simple modification in the output section of the conventional buck and quadratic converters can effectively extend the duty-cycle range. Only two additional components (an inductor and diode) are necessary for extending the duty-cycle range. The topologies presented in this paper show an improvement in the duty-cycle (about 40%) over the conventional buck and quadratic converters. Consequently, they are well suited for extreme step-down voltage conversion ratio applications. With extended duty-cycle, the current stress on all components is reduced, leading to a significant improvement of the system losses. The principle of operation, theoretical analysis, and comparison of circuit performances with other step-down converters is discussed regarding voltage and current stress. Experimental results of one prototype rated 40-W and operating at 100 kHz are provided in this paper to verify the performance of this new family of converters. The efficiency of the proposed converters is higher than the quadratic converters. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction DC–DC converters with extreme step-down voltage conversion ratios are required in newly emerging power electronics applications, such as automotive power systems, telecommunication power systems, data communications systems, industrial controls, and distributed power systems. For example, the emergence of 42 V automotive power systems call for a large step-down converter to supply the newly integrated circuits (3.3 V or 1.5 V) [1–2]. The conventional buck converter has difficulty in coping with very low voltage conversion ratios because it would require designing the converter to operate with a very low duty-cycle (e.g. less than 10%). Such operations become unacceptable since it leads to poor utilization of components as well as it degrades the system efficiency and impairs transient response [3]. A high switching frequency operation reduces the switch conduction time even shorter and gives rise to an objectionable increase in switching losses and it increases the control complexity. Thus, not only does it degrade the efficiency of the converter, but it also puts an upper-bound limit on the switching frequency. Moreover, consider, for example, a buck converter stepping a 340 V into a 3.3 V output voltage, operating at 100 kHz would require a switch-on-time of 97 ns, which is below the physical limitation of some of the low cost pulse-width modulation (PWM) controller’s minimum on-time. Thus, in an effort to further decrease the voltage conversion ratio and extend the duty-cycle range, a number of converter topol* Tel.: +965 9978 8776; fax: +965 2538 1284. E-mail addresses: [email protected], [email protected] 0196-8904/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.enconman.2008.09.041
ogies have been proposed in the literature. Cascading two or more converters can significantly extend the voltage conversion ratios [4–6]. However, this scheme requires more switching devices; hence, the overall conversion efficiency of the system is reduced due to the losses in the switching devices. Alternatively, using a large step-down ratio transformer would not solve the problem. Utilizing a transformer introduces several problems, such as the leakage inductance and the parasitic capacitance formed by the secondary winding of the transformer, which causes voltage and current spikes and increases loss and noise that can significantly degrade the system’s performance and damage circuit components [3]. Moreover, the presence of the transformer increases the system cost, weight, and complexity which are not tolerable especially for applications where galvanic isolation is not required. As a matter of fact, topologies based on a coupledinductor or tapped-inductor (TI) provides better performance than transformer based topologies. Moreover, it has been shown that by controlling the tapped winding ratio, the switch duty-cycle can be extended to a favorable range [7–13]. However, the TI topologies suffer from a voltage spike across the active switch caused by the leakage inductance between the coupled windings and the switch parasitic capacitance. Furthermore, the magnetic structure in these topologies is relatively complex and the conducted electromagnetic interference (EMI) in these topologies is also a concern. Therefore, the tapped-inductor topologies are almost infeasible without utilizing soft-switching techniques which increase the circuit complexity [8,11,14–21]. On the other hand, converters with quadratic dependence on the duty-cycle [22–23], can provide larger step-down conversion
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E.H. Ismail / Energy Conversion and Management 50 (2009) 232–239
ratios than other topologies, with a moderate duty-cycle operation. These converters are derived by cascading two conventional converters with an advantage of utilizing a single active switch instead of two. However, the single active switch in the quadratic converters is subjected to a higher voltage and current stress than its conventional counterpart. Therefore, the active switch in these converters is utilized very poorly. Some methods to improve the circuit performance of the quadratic buck converter are proposed in [24–25]. A simple and attractive solution for this problem is to use an inductor-diode voltage divider cell (known as hybrid switchedinductor cell) which can eliminate some of the above mentioned drawbacks, and improve the system efficiency [26]. In this paper, a general transformation procedure is introduced for incorporating a switched-inductor (SL) cell to the common DC–DC converters. As a result, several new single-switch DC–DC converters, suitable for wide input range extreme step-down applications, are proposed. The proposed converters allow the high switching frequency operation with a significantly larger step-down voltage conversion ratio for the same duty-cycle D of the conventional step-down quadratic converters in [23] and the hybrid step-down Cuk/Sepic/Zeta proposed in [26]. The proposed converters employ an additional inductor and diode compared to the conventional buck and quadratic converters. The topologies presented in this paper show a remarkable improvement in the duty-cycle range (about 40% gain) over the conventional buck and quadratic converters. Due to the extended duty-cycle, the current stress in the power stages is reduced; thereby, the circuit efficiency can be improved by reducing the conduction losses. Improved switch utilization and reduced current on circuit components could be cited as the merits of the proposed converters over the conventional quadratic converters.
V bd D ¼ V ac 1 þ D0
a
Do b
S
Lo Lo
-
b b
-V Lo
Do
V
Lo Do
ð1Þ
Lo
+ VLo S
DC–DC converters featuring the basic switching cell shown in Fig. 1 can be simply transformed into a large step-down DC–DC converter by replacing the three terminal basic switching cell of Fig. 1 with an appropriate switched-inductor (SL) cell, Fig. 2. According to Fig. 2, the proposed large step-down switching cell is formed by a single-switch S, two diodes, and two energy storage inductors. The terms, non-inverting and inverting, imply that the input/output voltage polarity is either the same or opposite, respectively. The power switch S and the two diodes D0 operate in a complementary way. The proposed SL-cell functions as an ‘‘inductor-diode voltage divider”, in which two energy storage inductors L0 are charged in series during the switch-on-time and discharge in parallel through the load when both diodes D0 are forward biased. Thus, by applying volt–second balance on L0, the relation between the input voltage and the output voltage for the SLcell can be obtained as follows:
+
a
2. Proposed large step-down DC–DC converters
where D0 ¼ 1 D is the normalized switch-off time and D is the switch duty cycle. A new class of single-switch DC–DC converters can be generated by incorporating the SL-cell to the common DC–DC PWM converters. Fig. 3 shows several examples of the generated large stepdown DC–DC converters, and others can be constructed following the same procedure. By spreading the output current among the two inductors, the stress on the individual components of the
Fig. 1. Basic three-terminal PWM switching cell.
a
Moreover, when compared to other step-down topologies, the component count in the proposed converters is relatively high, which might be considered as a drawback. However, their impact becomes less significant when compared to the gained advantages. The remainder of the paper is organized as follows. In Section 2, the generation of the new large step-down converters is given. Theoretical analyzes of each topology are given in Section 3. Comparison with other large step-down converters is presented in Section 4. Simulation and experimental results are shown in Section 5. The paper concludes with some final remarks, given in Section 6.
+
Lo
d
d
c Do
- VLo +
d
S
b
Lo
a
Do b
S
Lo Lo +
Do
VL
Do
+
- VLo + a
o
-V
c
Lo
c
-
c
Lo d + VLo -
c
d Do
Fig. 2. Proposed switched-inductor (SL) cell. Non-inverting SL-cell (a and b). Inverting SL-cell (c and d).
E.H. Ismail / Energy Conversion and Management 50 (2009) 232–239
+ VLo Ig
S
b Io
Lo
L1
+ Do
Vg
Do
Vo
Co
RL
+ VLo -
+ VL1 + S VC -
C
Ig D2
-
+ Do
Do Co
D1
Vg
Lo
+ Lo
-
Ig L1
RL
S
D2 C + VL1 -
VC +
f Io
Lo Do
Do
Ig Vo
Co
S
RL
g
+
- VC + D1
Do Co
S
+ VLo -
- VLo +
+ VL1 Ig L1
RL
+ VLo -
D3
VC +
Vo -
Lo
D1
Io
Lo
L1
Lo
D2
Vg
D2
+ V Lo -
D3
Do Vg
+
Vg
RL
-
+ VL1 -
-
Ig L1
Vo
Do
- VLo +
D1
Co
Vg
+ Do
e
+
+
o
D1
Vg
Io Lo Lo Lo
VL
Vo
Do
VC +
C + VL1 -
-
Co
D1
-V
Lo Lo
+
Ig D2
-
Lo
Io
+ S VC -
C
D2
d
-V
L1
RL
- VLo +
Do
+ VL1 -
Vo
Lo
- VLo +
c
Io
Lo
V
a
+
234
Io
Lo + Do
Do Co
S
Vo
RL
Lo - VLo + Fig. 3. Proposed large step-down DC–DC converters.
power converter is reduced. Fig. 3a shows a buck derived topology, while Fig. 3b shows a quadratic buck derived topology. The other topologies shown in Fig. 3c–e are derived from the quadratic converters presented in [23]. Topologies with galvanic isolation can be also obtained from the presented topologies. Fig. 3f shows the isolated version of the quadratic buck converter of Fig. 3b, while Fig. 3g shows an isolated version of the converter of Fig. 3e. Note that the input part of the circuit of Fig. 3d and e (i.e., L1, C, D1, and S) resembles a buckboost converter. Thereby, these converters are well suited for universal input voltage (85–265 V) active power factor correction (PFC) applications. It should be mentioned here that topologies based on the Cuk, Sepic, and Zeta converter are not presented in this study since they
were formerly reported in [26]. Therefore, the proposed transformation scheme in this paper shows a more general way to realize such a topology. The proposed converters in Fig. 3 can be divided into three categories according to their DC-characteristics. The first category will be denoted as Type 1 converter which includes only the buck derived topology, Fig. 3a. The second category will be denoted as Type 2 converter, which includes the quadratic buck derived topology, Fig. 3b, and a buck + buckboost derived topology, Fig. 3c. Finally, the third category will be denoted as Type 3 converter, which includes a quadratic buckboost derived topology, Fig. 3d, and a buckboost + buck derived topology, Fig. 3e. Therefore, only converters of Fig. 2a,b, and d will be analyzed in the following section.
E.H. Ismail / Energy Conversion and Management 50 (2009) 232–239
D ¼ M ¼ DB 1 þ D0
3. Principle of operation The basic converter analysis and DC characteristics of each of the proposed topologies are given in this section. To simplify the analysis, it is assumed that the converter is operating in continuous conduction mode (CCM) and the following assumptions are made during one switching cycle: (1) the input voltage is pure DC. (2) All components are ideal, thus the efficiency is 100%. (3) All capacitors are sized to have a relatively small voltage ripple at the switching frequency fs. (4) Inductor current ripple is negligible compared with its average value. Based on these assumptions, circuit operations in one switching cycle Ts is given next. 3.1. Type-1 large step-down converter
M¼
V0 D ¼ V g 1 þ D0
+ VLo S
Io
iLo Lo
+ Do
Vg
Do Co
Vo
RL
Lo - VLo + + VLo Ig Vg
S
Io
iLo Lo
+ Do
Do Co
Vo
RL
Lo - VLo + Fig. 4. Topological stages for Type-1 converter. (a) Switch-on topology. (b) Switchoff topology.
ð4Þ
ð5Þ
where IL0 and DiL0 are given by
I L0 ¼
I0 1 þ D0
DiL0 ¼
ðV g V 0 ÞDT s ; 4L0
ð6Þ
ð7Þ
respectively. Substituting (6) and (7) into (5) and using (2) yields the inductance value required for the CCM operation and it is given by
1 RLmax T s D0 ð1 þ D0 Þ 2
ð8Þ
where RLmax is the maximum load resistance (minimum load power). 3.2. Type-2 large step-down converter The converters of Fig. 2b and c (hereafter called Type-2 converter) have the same DC characteristics. Therefore, only the converter of Fig. 3b, which is derived from the quadratic buck topology, will be analyzed. The additional components in Type-2 converter allow it to operate differently from the conventional quadratic buck converter. In the CCM, the converter goes through two periodically switched operating states within each switching period Ts: (1) during the switch S on-time, S and D1 are on, while D2 and D0 are off, (2) during the switch-off-time, D2 and D0 are on, while S and D1 are off. The topological stages during the switch-on-time and offtime are shown in Fig. 5a and b, respectively. Referring to Fig. 5a and b, the ideal voltage conversion ratio M can be found from the volt– second relationship of the inductor L1 and L0, which gives
M¼
b
2DB 1 þ DB
Thus, it is clear from (4) that D in Type-1 converter is always greater than DB. This is an attractive feature for low DC voltage gain applications, since the conventional buck converter must operate at extremely low duty-cycle ratios. When the converter is designed to operate in CCM, the average value of the inductor current must be greater than its peak current ripple, i.e.
L0 >
a Ig
D¼
ð2Þ
Eq. (2) shows that the voltage gain M for Type-1 converter is lower than the voltage gain of the conventional buck converter by a factor of 1=ð1 þ D0 Þ. In other words, for the same voltage conversion ratio M, Type-1 converter operates at higher duty ratio compared to the conventional buck converter. The relation between the respective duty ratios D and DB (the duty ratio in the buck converter) is obtained from
ð3Þ
Solving for D in (3) gives
IL0 > DiL0
The buck topology of Fig. 3a (hereafter called Type-1 converter) is analyzed next. The additional components in Type-1 converter allow it to operate differently from the conventional buck converter. In the CCM, the converter goes through two periodically switched operating states within each switching period Ts. The topological stages during switch-on-time and off-time are shown in Fig. 4a and b, respectively. Referring to Fig. 4a and b, the ideal voltage conversion ratio M can be found from the volt–second relationship of inductor L1 and it is given by
235
V0 D2 ¼ V g 1 þ D0
ð9Þ
Similar to the Type-1 converter, (9) shows that the voltage gain M for Type-2 converter is lower than the voltage gain of the quadratic buck converter by a factor of 1/(1+D0 ). Thus, for the same voltage conversion ratio M, Type-2 converter operates at a higher duty ratio compared to the conventional quadratic buck converter. The relationship between their respective duty ratios D and DQB (the duty ratio in the quadratic buck converter) is given by the following relation
" sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi# D2QB D2 8 2 ¼ M ¼ DQB ) D ¼ 1 þ 1 þ 2 2 1 þ D0 DQB
ð10Þ
It is interesting to note that the difference between D and DQB becomes more pronounced for low values of M. For example, for M = 0.01, then D is 36.5% higher than DQB. This makes Type-2 converter more suitable for extreme low voltage conversion applications.
E.H. Ismail / Energy Conversion and Management 50 (2009) 232–239
Vo
Co
D1
Vg
Ig L1 iL1
RL
+ Vo
Co
D1
Vg
Ig L1 iL1
RL
Lo
+ Co
iLo
S
Vg
-
Lo Lo +
Do
Io
VC +
C + VL1 -
-
Io
Do
Lo
iLo L o
D1
D2
Lo
Ig D2
b
Do
RL
-
-V
+ S VC -
iL1 L1 C
Vo
Do
+ VLo -
+ VL1 -
Co
iLo
- VLo +
b
+ -
S
Vg
-
Lo
+
Do
Lo Lo Lo
+ Do
Io
VC +
C + VL1 -
Lo
Ig D2
Io
iLo Lo
-V
+ S VC -
C
Do
D1
V
L1
D2
+
iL1
a
+ VLo -
+ VL1 -
V
a
+
236
Vo
RL
-
Do
- VLo + Fig. 5. Topological stages for Type-2 converter. (a) Switch-on topology. (b) Switchoff topology.
Fig. 6. Topological stages for Type-3 converter. (a) Switch-on topology. (b) Switchoff topology.
When the converter is designed to operate in CCM, both inductor currents, iL1 and iL0 , must have small current ripples compared to their average DC values. The condition for the output inductor L0 to achieve CCM operation is similar to (8). Whereas, the inductance value of L1 required for CCM operation can be determined following the same procedure presented in the previous subsection, and it is given by
to operate differently from its conventional counterpart. In the CCM, the converter goes through two periodically switched operating states within each switching period Ts. The switch and diodes states during each switching period are similar to Type-2 converter. The topological stages during the switch-on-time and off-time are shown in Fig. 6a and b, respectively. Referring to Fig. 6a and b, the ideal voltage conversion ratio M can be found from the volt–second relationship of the inductor L1 and L0, which gives
L1 >
2 1 1 þ D0 RLmax T s D0 2 D
ð11Þ
3.3. Type-3 large step-down converter The converters of Fig. 2d and e (hereafter called Type-3 converter) have the same DC characteristics. Therefore, only the converter of Fig. 3d, which is derived from the quadratic buckboost topology, will be analyzed. The additional components in Type-3 converter allow it
M¼
V0 D2 ¼ 0 V g D ð1 þ D0 Þ
06D6
2 3
ð12Þ
It is clear from (12) that when D 2=3, the output voltage is greater than the input voltage. As a result, diode D2 is always in the on-state and diode D0 is always off. The voltage conversion ratio in this case is given by
M¼
V 0 2D 1 ¼ Vg D0
2 6D61 3
ð13Þ
Table 1 Comparison between large step-down converters Type1
Type 2
Type 3*
Type-0 (Converters of Figs. 4, 6 and 7 in [26])
Quadratic Buck
Quadratic converters Fig. 4 in [23]
Quadratic converters with M ¼ D2 =D02 Fig. 7 in [23]
D2 1þD0 2þD 1þD0
D 2D0 1 D0
1+D
D2 D0 1 D0
V D1 PK
–
1
–
1
1
V D2 PK
–
1
–
1
V D0 PK Isrms
1 1þD0 pffiffiffi D 1þD0
1 2D0 pffiffiffi D 2D0
D pffiffiffiffi D
1 D0 D D0 pffiffiffi D D0
ID1 avg ¼ ID2 avg
–
–
DD0
D
D2 D02 1 D0 12D D02 1 D0 D 02 D pffiffiffi D D02 D 0 D
ID0 avg
D0 1þD0
D 1þD0 pffiffiffi D 1þD0 DD0 1þD0 D0 1þD0 pffiffiffiffiffiffi0 DD 1þD0 pffiffiffiffiffiffi0 DD 1þD0
D2 D0 ð1þD0 Þ 1 D0 23D D0 ð1þD0 Þ 1 D0 D D0 ð1þD0 Þ pffiffiffi D 0 D ð1þD0 Þ D 0 1þD D0 1þD0 qffiffiffiffi 1 D 1þD0 D0 pffiffiffiffiffiffi0 DD 1þD0
D2
VsPk
D 1þD0 2 1þD0
1 2 qffiffiffiffi
D0 pffiffiffiffiffiffiffiffi0 DD
D0 qffiffiffiffi
M
ICrms IC1 rms Silicon utilization factor *
– pffiffiffiffiffiffi0
DD 1þD0 pffiffiffi D 2 ð1
0
þDÞ
ð1þD0 ÞðDÞ3=2 2þD
0
D ðDÞ
3=2
1 2 1 2
D D0
qffiffiffiffi D D0
pffiffiffiffi D D 0
Valid for 0 D 2=3. Voltages are normalized to Vg, while currents are normalized to I0.
0 ðDÞ3=2 1þD
1
D D0
1 D0
qffiffiffiffi
qffiffiffiffi
D D0
D D0
0 0
3=2
D ðDÞ
D ðDÞ3=2 0
237
E.H. Ismail / Energy Conversion and Management 50 (2009) 232–239
It should be mentioned here that the quadratic buckboost converter presented in [23] operates properly only when D 0:5 with M being equal to D2 =D02 . When D 0:5, the output voltage V0 is clamped to the input voltage Vg so that the step-up mode is not possible. Thus, the proposed converter of Fig. 3d has two distinct advantages over the quadratic buckboost converter [23], namely it provides extended duty-cycle in step-down mode, and step-up
function capability. Moreover, the Type-3 converters operate at a higher duty ratio compared to their conventional counterparts provided that M is the same for both converters. The relationship between the duty ratio D for the converter of Fig. 3d and DQBB (the duty ratio in the quadratic buckboost converter) is given by the following relation:
D2 ¼M¼ D ð1 þ D0 Þ
0
DQBB 1 DQBB
2
)D¼
h pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffii 1 3 þ 1 þ 8De 2ðDe 1Þ ð14Þ
where
De ¼
2 1 DQBB DQBB
ð15Þ
The Type-3 converters are more suitable for extreme low voltage conversion ratio than the quadratic buckboost converters. For example, consider M = 0.01, then according to (14), the value of D is 40.6% higher than DQBB, which is an attractive feature. Similar to the Type-2 converters, both the input inductor L1 and the output inductor L0 must be carefully selected to ensure CCM operation. The condition for the output inductor L0 to achieve CCM operation is similar to (8), whereas the inductance value of L1 required for CCM operation is given by
L1 > Fig. 7. Ideal voltage conversion ratio M as a function of duty-cycle D.
a
b
c
d
0 2 1 D ð1 þ D0 Þ RLmax T s 2 D
Fig. 8. Normalized switch and output diode (D0) voltage and current stress as a function of voltage conversion ratio M.
ð16Þ
238
E.H. Ismail / Energy Conversion and Management 50 (2009) 232–239
4. Topologies comparison Table 1 summarizes the DC voltage gain and the switch and diodes stresses for the proposed converters as well as for other previously proposed single-switch large step-down topologies. The voltage gain for these converters is graphically illustrated in Fig. 7. It can be seen from Fig. 7 that both Type-2 and Type-3 converters have an advantage of extended duty-cycle range, i.e., for the same duty-cycle, they provide the lowest voltage gain compared to other topologies. This high step-down conversion ratio makes the proposed converters suitable for applications with a high difference between the input and output voltage. Note that the Type-1 converter and Type-0 converters (converters of Fig. 4, 6 and 7 in [26]) are not suitable for very extreme step-down voltage conversion ratio applications since it requires designing the converter for a very low duty-cycle operation which will decrease the switching frequency limits as well as it degrades the overall system efficiency. Besides the extended duty-cycle, the proposed converters also reduce the voltage and current stress on the output rectifier diode D0 as shown in Fig. 8a and b. This allows using lower voltage rated diodes; hence, the conduction loss and switching loss could be reduced leading to efficiency improvement. The normalized switch peak voltage and rms current stresses are shown in Fig. 8c and d, respectively. It is clear from Fig. 8c that Type-2 and Type-3 converters are subjected to a higher voltage stress compared to their conventional quadratic converters counterparts. On the other hand, Fig. 8d shows that the switch current stress for Type-2 and Type-3 are lower than their conventional quadratic converters. Therefore, it is useful to compare the switch performance for these converters in terms of active switch utilization (U) [3]. The active switch utilization factor, which is defined as the converter output power divided by the product of the active switch peak voltage times its rms current, represents how well a circuit topology uses the capability of its switches to achieve the output power. Converters having high values of U factor implies the power that a switching device processes for a given output is reduced, which can alleviate conduction and switching loss; hence, it operates with a relatively higher efficiency. Thereby, evaluating U factor is a good tool to compare different converter topologies. Fig. 9 shows the U factor for the proposed topologies as well as for other previously presented large step-down topologies. Referring to Fig. 9, it can be seen that Type-1 converter exhibits the best switch utilization, and therefore it has the lowest conduction loss compared to other topologies. As a matter of fact, for low values of M, the active switch in Type-1 converter is utilized better than
Fig. 9. Active switch utilization factor U as a function of voltage conversion ratio, M.
the active switch in the conventional buck converter. Recall that, the U factor in the conventional buck converter is equal to (M)1/2. Moreover, Fig. 9 also shows that the U factor for Type-2 and Type-3 converters is higher than their conventional counterparts. From Table 1, one can also show that the current stress through the capacitor C, and diodes D1 and D2 for the proposed topologies are less than their conventional counterparts. However, the current stress in the output capacitor C0 in all the topologies shown in Table 1 (except for the quadratic buck and the converter of Fig. 4 in [23]) is relatively high. Therefore, the output capacitor needs to have a low equivalent-series-resistance (ESR) to ensure a high efficiency and low ripple voltage.
5. Experimental results A type 2 converter, Fig. 3b, has been constructed for M = 0.1 to demonstrate feasibility. The prototype was built using the following parameter set:
Fig. 10. Experimental waveforms for the converter of Fig. 3(b). (Vg = 100 V, V0 = 10 V, Pout = 40 W).
E.H. Ismail / Energy Conversion and Management 50 (2009) 232–239
Vg = 100 V, V0 = 10 V, Pout = 40 W L1 = 1 mH, L0 = 330 lH, C = C0 = 220 lF Switch S: FQA48N20 (200 V/48 A, RDSon = 37 mX typical and 50 mX maximum) Diodes D1 and D2: SDP10S30 (300 V/10 A) Diodes D0: MBR2080CT (80 V/10 A) The converter is switched at 100 kHz with a duty ratio of 0.4 (according to (9)). The experimental waveforms at full-load are depicted in Fig. 10. Referring to Fig. 10a, the measured DC output voltage V0 is 9.65 V. The switch S and diode D1 blocking voltage are shown in Fig. 10b, whereas Fig. 10c shows the voltage across diodes D0 and D2. It is clear from Fig. 10 that the measured results are in a good agreement with the theoretical results shown in Table 1. The measured full-load efficiency of the prototype converter is about 90.9%. 6. Conclusions This paper has presented a new family of single-switch PWM converters suitable for step-down application – in particular for high frequency applications where the wide voltage ranges between the input and output call for an extremely step-down conversion ratio. The operation principle in CCM and boundary operating condition are presented. The proposed converters are regulated by the conventional PWM technique at a constant frequency. Comparison with other step-down topologies shows that the proposed converters have better characteristics over the conventional DC–DC converters with respect to the wide duty-cycle range, reduced current stress, and semiconductor utilization. Consequently, the system efficiency gets improved. The experimental result with a 40-W hardware prototype is also included to support the validity of the proposed concept. Finally, the extended duty-cycle property makes some of the proposed topologies as a good candidate for universal-line power factor correction applications. References [1] Kassakian JG, Miller JM, Traub N. Automotive electronics power up. IEEE Spectrum 2000;37(5):34–9. [2] Graf A. Semiconductors in the 42V PowerNet. In: Intertech-42V automotive systems conference; 2001. p. 1–11. [3] Erickson RW, Makismovic D. Fundamentals of power electronics. 2nd ed. USA: Kluwer Academic Publishers; 2001. [4] Matsuo H, Harada K. The cascade connection of switching regulators. IEEE Trans Ind Appl 1976;12(2):192–8.
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[5] Middlebrook RD. Transformerless DC-to-DC converters with large conversion ratios. IEEE Trans. Power Electron 1988;3(4):484–8. [6] Morales-Saldaña JA, Carbajal-Gutiérrez EE, Leyva-Ramos J. Modelling of switch-mode DC–DC cascade converters. IEEE Trans Aerospace Electron Syst 2002;38(1):295–9. [7] Rico M, Uceda J, Sebastian J, Aldana F. Static and dynamics modelling of tapped-inductor DC-to-DC converters. In: IEEE power electronics specialists conference; 1987. p. 281–88. [8] Lethellier PR. Buck converter with inductive turn ratio optimization. US Patent 6 094 038; July 2000. [9] Lenk R. Introduction to the tapped buck converter. In: High freq. power conversion (HFPC); 2000. p. 155–66. [10] Grant DA, Darroman Y. Extending the tapped-inductor DC-to-DC converter family. Electron Lett 2001;37(3):145–6. [11] Wei J, Xu P, Wu H-P, Lee FC, Yao K, Ye M. Comparison of three topology candidates for 12 V VRM. In: IEEE applied power electronics conference; 2001. p. 245–51. [12] Xu P, Wei J, Yao K, Meng Y, Lee FC. Investigation of candidate topologies for 12V VRM. In: IEEE applied power electronics conference; 2002. p. 686–92. [13] Darroman Y, Ferré A. 42-V/3-V Watkins–Johnson converter for automotive use. IEEE Trans Power Electron 2006;21(3):592–602. [14] Xu P, Wei J, Lee FC. The active-clamp couple-buck converter-a novel high efficiency voltage regulator module. In: IEEE applied power electronics conference; 2001. p. 252–57. [15] Kingston J, Morrison R, Egan MG, Hallissey G. Application of a passive lossless snubber to a tapped inductor buck DC/DC converter. In: IEEE power electronics, machines drives; 2002. p. 445–50. [16] Qian J. Voltage regulator with clamping circuit. US Patent 6507174; January 2003. [17] Yao K, Ye M, Xu M, Lee FC. Tapped-inductor buck converter for highstep-down DC–DC conversion. IEEE Trans Power Electron 2005;20(4): 775–80. [18] Yao K, Qiu YM, Xu M, Lee FC. A novel winding-coupled buck converter for highfrequency, high-step-down DC–DC conversion. IEEE Trans Power Electron 2005;20(5):1017–24. [19] Xu P, Wei J, Lee FC. Multiphase coupled-buck converter – a novel high efficient 12 V voltage regulator module. IEEE Trans Power Electron 2003;18(1):74–82. [20] Park J-H, Cho B-H. The zero voltage switching (ZVS) critical conduction mode (CRM) buck converter with tapped-inductor. IEEE Trans Power Electron 2005;20(4):762–74. [21] Park J-H, Cho B-H. Nonisolation soft-switching buck converter with tappedinductor for wide-input extreme step-down applications. IEEE Trans Circ SystI: Regular Papers 2007;54(8):1809–18. [22] Birca-Galateanu S. Buck-flyback DC–DC converter. IEEE Trans Aerospace Electron Syst 1988;24(6):800–7. [23] Makdmovic D, Cuk S. Switching converters with wide DC conversion range. IEEE Trans Power Electron 1991;6(1):151–7. [24] Barbosa L, Vieira JB, de Freitas LC, Vilela MS, Farias VJ. A buck quadratic PWM soft-switching converter using a single active switch. IEEE Trans Power Electron 1999;14(3):445–53. [25] Pacheco VM, Do Nascimento AJ, Farias VJ, Vieira JB, de Freitas LC. A quadratic buck converter with lossless commutation. IEEE Trans Ind Electron 2000;47(2):264–72. [26] Axelrod B, Berkovich Y, Ioinovici A. Switched-capacitor (SC)/switched inductor (SL) structures for getting hybrid step-down Cuk/Sepic/Zeta converters. IEEE Int Symp Circ Syst (ISCAS) 2006:5063–6.
Contents lists available at ScienceDirect
Energy Conversion and Management journal homepage: www.elsevier.com/locate/enconman
Large step-down DC–DC converters with reduced current stress Esam H. Ismail * Department of Electrical Engineering, College of Technological Studies, P.O. Box 35007, 36051 Al-Shaab, Kuwait
a r t i c l e
i n f o
Article history: Received 5 March 2008 Accepted 30 September 2008
Keywords: DC–DC power converters Quadratic converters Step-down converters Switched mode power supplies (SMPS)
a b s t r a c t In this paper, several DC–DC converters with large voltage step-down ratios are introduced. A simple modification in the output section of the conventional buck and quadratic converters can effectively extend the duty-cycle range. Only two additional components (an inductor and diode) are necessary for extending the duty-cycle range. The topologies presented in this paper show an improvement in the duty-cycle (about 40%) over the conventional buck and quadratic converters. Consequently, they are well suited for extreme step-down voltage conversion ratio applications. With extended duty-cycle, the current stress on all components is reduced, leading to a significant improvement of the system losses. The principle of operation, theoretical analysis, and comparison of circuit performances with other step-down converters is discussed regarding voltage and current stress. Experimental results of one prototype rated 40-W and operating at 100 kHz are provided in this paper to verify the performance of this new family of converters. The efficiency of the proposed converters is higher than the quadratic converters. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction DC–DC converters with extreme step-down voltage conversion ratios are required in newly emerging power electronics applications, such as automotive power systems, telecommunication power systems, data communications systems, industrial controls, and distributed power systems. For example, the emergence of 42 V automotive power systems call for a large step-down converter to supply the newly integrated circuits (3.3 V or 1.5 V) [1–2]. The conventional buck converter has difficulty in coping with very low voltage conversion ratios because it would require designing the converter to operate with a very low duty-cycle (e.g. less than 10%). Such operations become unacceptable since it leads to poor utilization of components as well as it degrades the system efficiency and impairs transient response [3]. A high switching frequency operation reduces the switch conduction time even shorter and gives rise to an objectionable increase in switching losses and it increases the control complexity. Thus, not only does it degrade the efficiency of the converter, but it also puts an upper-bound limit on the switching frequency. Moreover, consider, for example, a buck converter stepping a 340 V into a 3.3 V output voltage, operating at 100 kHz would require a switch-on-time of 97 ns, which is below the physical limitation of some of the low cost pulse-width modulation (PWM) controller’s minimum on-time. Thus, in an effort to further decrease the voltage conversion ratio and extend the duty-cycle range, a number of converter topol* Tel.: +965 9978 8776; fax: +965 2538 1284. E-mail addresses: [email protected], [email protected] 0196-8904/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.enconman.2008.09.041
ogies have been proposed in the literature. Cascading two or more converters can significantly extend the voltage conversion ratios [4–6]. However, this scheme requires more switching devices; hence, the overall conversion efficiency of the system is reduced due to the losses in the switching devices. Alternatively, using a large step-down ratio transformer would not solve the problem. Utilizing a transformer introduces several problems, such as the leakage inductance and the parasitic capacitance formed by the secondary winding of the transformer, which causes voltage and current spikes and increases loss and noise that can significantly degrade the system’s performance and damage circuit components [3]. Moreover, the presence of the transformer increases the system cost, weight, and complexity which are not tolerable especially for applications where galvanic isolation is not required. As a matter of fact, topologies based on a coupledinductor or tapped-inductor (TI) provides better performance than transformer based topologies. Moreover, it has been shown that by controlling the tapped winding ratio, the switch duty-cycle can be extended to a favorable range [7–13]. However, the TI topologies suffer from a voltage spike across the active switch caused by the leakage inductance between the coupled windings and the switch parasitic capacitance. Furthermore, the magnetic structure in these topologies is relatively complex and the conducted electromagnetic interference (EMI) in these topologies is also a concern. Therefore, the tapped-inductor topologies are almost infeasible without utilizing soft-switching techniques which increase the circuit complexity [8,11,14–21]. On the other hand, converters with quadratic dependence on the duty-cycle [22–23], can provide larger step-down conversion
233
E.H. Ismail / Energy Conversion and Management 50 (2009) 232–239
ratios than other topologies, with a moderate duty-cycle operation. These converters are derived by cascading two conventional converters with an advantage of utilizing a single active switch instead of two. However, the single active switch in the quadratic converters is subjected to a higher voltage and current stress than its conventional counterpart. Therefore, the active switch in these converters is utilized very poorly. Some methods to improve the circuit performance of the quadratic buck converter are proposed in [24–25]. A simple and attractive solution for this problem is to use an inductor-diode voltage divider cell (known as hybrid switchedinductor cell) which can eliminate some of the above mentioned drawbacks, and improve the system efficiency [26]. In this paper, a general transformation procedure is introduced for incorporating a switched-inductor (SL) cell to the common DC–DC converters. As a result, several new single-switch DC–DC converters, suitable for wide input range extreme step-down applications, are proposed. The proposed converters allow the high switching frequency operation with a significantly larger step-down voltage conversion ratio for the same duty-cycle D of the conventional step-down quadratic converters in [23] and the hybrid step-down Cuk/Sepic/Zeta proposed in [26]. The proposed converters employ an additional inductor and diode compared to the conventional buck and quadratic converters. The topologies presented in this paper show a remarkable improvement in the duty-cycle range (about 40% gain) over the conventional buck and quadratic converters. Due to the extended duty-cycle, the current stress in the power stages is reduced; thereby, the circuit efficiency can be improved by reducing the conduction losses. Improved switch utilization and reduced current on circuit components could be cited as the merits of the proposed converters over the conventional quadratic converters.
V bd D ¼ V ac 1 þ D0
a
Do b
S
Lo Lo
-
b b
-V Lo
Do
V
Lo Do
ð1Þ
Lo
+ VLo S
DC–DC converters featuring the basic switching cell shown in Fig. 1 can be simply transformed into a large step-down DC–DC converter by replacing the three terminal basic switching cell of Fig. 1 with an appropriate switched-inductor (SL) cell, Fig. 2. According to Fig. 2, the proposed large step-down switching cell is formed by a single-switch S, two diodes, and two energy storage inductors. The terms, non-inverting and inverting, imply that the input/output voltage polarity is either the same or opposite, respectively. The power switch S and the two diodes D0 operate in a complementary way. The proposed SL-cell functions as an ‘‘inductor-diode voltage divider”, in which two energy storage inductors L0 are charged in series during the switch-on-time and discharge in parallel through the load when both diodes D0 are forward biased. Thus, by applying volt–second balance on L0, the relation between the input voltage and the output voltage for the SLcell can be obtained as follows:
+
a
2. Proposed large step-down DC–DC converters
where D0 ¼ 1 D is the normalized switch-off time and D is the switch duty cycle. A new class of single-switch DC–DC converters can be generated by incorporating the SL-cell to the common DC–DC PWM converters. Fig. 3 shows several examples of the generated large stepdown DC–DC converters, and others can be constructed following the same procedure. By spreading the output current among the two inductors, the stress on the individual components of the
Fig. 1. Basic three-terminal PWM switching cell.
a
Moreover, when compared to other step-down topologies, the component count in the proposed converters is relatively high, which might be considered as a drawback. However, their impact becomes less significant when compared to the gained advantages. The remainder of the paper is organized as follows. In Section 2, the generation of the new large step-down converters is given. Theoretical analyzes of each topology are given in Section 3. Comparison with other large step-down converters is presented in Section 4. Simulation and experimental results are shown in Section 5. The paper concludes with some final remarks, given in Section 6.
+
Lo
d
d
c Do
- VLo +
d
S
b
Lo
a
Do b
S
Lo Lo +
Do
VL
Do
+
- VLo + a
o
-V
c
Lo
c
-
c
Lo d + VLo -
c
d Do
Fig. 2. Proposed switched-inductor (SL) cell. Non-inverting SL-cell (a and b). Inverting SL-cell (c and d).
E.H. Ismail / Energy Conversion and Management 50 (2009) 232–239
+ VLo Ig
S
b Io
Lo
L1
+ Do
Vg
Do
Vo
Co
RL
+ VLo -
+ VL1 + S VC -
C
Ig D2
-
+ Do
Do Co
D1
Vg
Lo
+ Lo
-
Ig L1
RL
S
D2 C + VL1 -
VC +
f Io
Lo Do
Do
Ig Vo
Co
S
RL
g
+
- VC + D1
Do Co
S
+ VLo -
- VLo +
+ VL1 Ig L1
RL
+ VLo -
D3
VC +
Vo -
Lo
D1
Io
Lo
L1
Lo
D2
Vg
D2
+ V Lo -
D3
Do Vg
+
Vg
RL
-
+ VL1 -
-
Ig L1
Vo
Do
- VLo +
D1
Co
Vg
+ Do
e
+
+
o
D1
Vg
Io Lo Lo Lo
VL
Vo
Do
VC +
C + VL1 -
-
Co
D1
-V
Lo Lo
+
Ig D2
-
Lo
Io
+ S VC -
C
D2
d
-V
L1
RL
- VLo +
Do
+ VL1 -
Vo
Lo
- VLo +
c
Io
Lo
V
a
+
234
Io
Lo + Do
Do Co
S
Vo
RL
Lo - VLo + Fig. 3. Proposed large step-down DC–DC converters.
power converter is reduced. Fig. 3a shows a buck derived topology, while Fig. 3b shows a quadratic buck derived topology. The other topologies shown in Fig. 3c–e are derived from the quadratic converters presented in [23]. Topologies with galvanic isolation can be also obtained from the presented topologies. Fig. 3f shows the isolated version of the quadratic buck converter of Fig. 3b, while Fig. 3g shows an isolated version of the converter of Fig. 3e. Note that the input part of the circuit of Fig. 3d and e (i.e., L1, C, D1, and S) resembles a buckboost converter. Thereby, these converters are well suited for universal input voltage (85–265 V) active power factor correction (PFC) applications. It should be mentioned here that topologies based on the Cuk, Sepic, and Zeta converter are not presented in this study since they
were formerly reported in [26]. Therefore, the proposed transformation scheme in this paper shows a more general way to realize such a topology. The proposed converters in Fig. 3 can be divided into three categories according to their DC-characteristics. The first category will be denoted as Type 1 converter which includes only the buck derived topology, Fig. 3a. The second category will be denoted as Type 2 converter, which includes the quadratic buck derived topology, Fig. 3b, and a buck + buckboost derived topology, Fig. 3c. Finally, the third category will be denoted as Type 3 converter, which includes a quadratic buckboost derived topology, Fig. 3d, and a buckboost + buck derived topology, Fig. 3e. Therefore, only converters of Fig. 2a,b, and d will be analyzed in the following section.
E.H. Ismail / Energy Conversion and Management 50 (2009) 232–239
D ¼ M ¼ DB 1 þ D0
3. Principle of operation The basic converter analysis and DC characteristics of each of the proposed topologies are given in this section. To simplify the analysis, it is assumed that the converter is operating in continuous conduction mode (CCM) and the following assumptions are made during one switching cycle: (1) the input voltage is pure DC. (2) All components are ideal, thus the efficiency is 100%. (3) All capacitors are sized to have a relatively small voltage ripple at the switching frequency fs. (4) Inductor current ripple is negligible compared with its average value. Based on these assumptions, circuit operations in one switching cycle Ts is given next. 3.1. Type-1 large step-down converter
M¼
V0 D ¼ V g 1 þ D0
+ VLo S
Io
iLo Lo
+ Do
Vg
Do Co
Vo
RL
Lo - VLo + + VLo Ig Vg
S
Io
iLo Lo
+ Do
Do Co
Vo
RL
Lo - VLo + Fig. 4. Topological stages for Type-1 converter. (a) Switch-on topology. (b) Switchoff topology.
ð4Þ
ð5Þ
where IL0 and DiL0 are given by
I L0 ¼
I0 1 þ D0
DiL0 ¼
ðV g V 0 ÞDT s ; 4L0
ð6Þ
ð7Þ
respectively. Substituting (6) and (7) into (5) and using (2) yields the inductance value required for the CCM operation and it is given by
1 RLmax T s D0 ð1 þ D0 Þ 2
ð8Þ
where RLmax is the maximum load resistance (minimum load power). 3.2. Type-2 large step-down converter The converters of Fig. 2b and c (hereafter called Type-2 converter) have the same DC characteristics. Therefore, only the converter of Fig. 3b, which is derived from the quadratic buck topology, will be analyzed. The additional components in Type-2 converter allow it to operate differently from the conventional quadratic buck converter. In the CCM, the converter goes through two periodically switched operating states within each switching period Ts: (1) during the switch S on-time, S and D1 are on, while D2 and D0 are off, (2) during the switch-off-time, D2 and D0 are on, while S and D1 are off. The topological stages during the switch-on-time and offtime are shown in Fig. 5a and b, respectively. Referring to Fig. 5a and b, the ideal voltage conversion ratio M can be found from the volt– second relationship of the inductor L1 and L0, which gives
M¼
b
2DB 1 þ DB
Thus, it is clear from (4) that D in Type-1 converter is always greater than DB. This is an attractive feature for low DC voltage gain applications, since the conventional buck converter must operate at extremely low duty-cycle ratios. When the converter is designed to operate in CCM, the average value of the inductor current must be greater than its peak current ripple, i.e.
L0 >
a Ig
D¼
ð2Þ
Eq. (2) shows that the voltage gain M for Type-1 converter is lower than the voltage gain of the conventional buck converter by a factor of 1=ð1 þ D0 Þ. In other words, for the same voltage conversion ratio M, Type-1 converter operates at higher duty ratio compared to the conventional buck converter. The relation between the respective duty ratios D and DB (the duty ratio in the buck converter) is obtained from
ð3Þ
Solving for D in (3) gives
IL0 > DiL0
The buck topology of Fig. 3a (hereafter called Type-1 converter) is analyzed next. The additional components in Type-1 converter allow it to operate differently from the conventional buck converter. In the CCM, the converter goes through two periodically switched operating states within each switching period Ts. The topological stages during switch-on-time and off-time are shown in Fig. 4a and b, respectively. Referring to Fig. 4a and b, the ideal voltage conversion ratio M can be found from the volt–second relationship of inductor L1 and it is given by
235
V0 D2 ¼ V g 1 þ D0
ð9Þ
Similar to the Type-1 converter, (9) shows that the voltage gain M for Type-2 converter is lower than the voltage gain of the quadratic buck converter by a factor of 1/(1+D0 ). Thus, for the same voltage conversion ratio M, Type-2 converter operates at a higher duty ratio compared to the conventional quadratic buck converter. The relationship between their respective duty ratios D and DQB (the duty ratio in the quadratic buck converter) is given by the following relation
" sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi# D2QB D2 8 2 ¼ M ¼ DQB ) D ¼ 1 þ 1 þ 2 2 1 þ D0 DQB
ð10Þ
It is interesting to note that the difference between D and DQB becomes more pronounced for low values of M. For example, for M = 0.01, then D is 36.5% higher than DQB. This makes Type-2 converter more suitable for extreme low voltage conversion applications.
E.H. Ismail / Energy Conversion and Management 50 (2009) 232–239
Vo
Co
D1
Vg
Ig L1 iL1
RL
+ Vo
Co
D1
Vg
Ig L1 iL1
RL
Lo
+ Co
iLo
S
Vg
-
Lo Lo +
Do
Io
VC +
C + VL1 -
-
Io
Do
Lo
iLo L o
D1
D2
Lo
Ig D2
b
Do
RL
-
-V
+ S VC -
iL1 L1 C
Vo
Do
+ VLo -
+ VL1 -
Co
iLo
- VLo +
b
+ -
S
Vg
-
Lo
+
Do
Lo Lo Lo
+ Do
Io
VC +
C + VL1 -
Lo
Ig D2
Io
iLo Lo
-V
+ S VC -
C
Do
D1
V
L1
D2
+
iL1
a
+ VLo -
+ VL1 -
V
a
+
236
Vo
RL
-
Do
- VLo + Fig. 5. Topological stages for Type-2 converter. (a) Switch-on topology. (b) Switchoff topology.
Fig. 6. Topological stages for Type-3 converter. (a) Switch-on topology. (b) Switchoff topology.
When the converter is designed to operate in CCM, both inductor currents, iL1 and iL0 , must have small current ripples compared to their average DC values. The condition for the output inductor L0 to achieve CCM operation is similar to (8). Whereas, the inductance value of L1 required for CCM operation can be determined following the same procedure presented in the previous subsection, and it is given by
to operate differently from its conventional counterpart. In the CCM, the converter goes through two periodically switched operating states within each switching period Ts. The switch and diodes states during each switching period are similar to Type-2 converter. The topological stages during the switch-on-time and off-time are shown in Fig. 6a and b, respectively. Referring to Fig. 6a and b, the ideal voltage conversion ratio M can be found from the volt–second relationship of the inductor L1 and L0, which gives
L1 >
2 1 1 þ D0 RLmax T s D0 2 D
ð11Þ
3.3. Type-3 large step-down converter The converters of Fig. 2d and e (hereafter called Type-3 converter) have the same DC characteristics. Therefore, only the converter of Fig. 3d, which is derived from the quadratic buckboost topology, will be analyzed. The additional components in Type-3 converter allow it
M¼
V0 D2 ¼ 0 V g D ð1 þ D0 Þ
06D6
2 3
ð12Þ
It is clear from (12) that when D 2=3, the output voltage is greater than the input voltage. As a result, diode D2 is always in the on-state and diode D0 is always off. The voltage conversion ratio in this case is given by
M¼
V 0 2D 1 ¼ Vg D0
2 6D61 3
ð13Þ
Table 1 Comparison between large step-down converters Type1
Type 2
Type 3*
Type-0 (Converters of Figs. 4, 6 and 7 in [26])
Quadratic Buck
Quadratic converters Fig. 4 in [23]
Quadratic converters with M ¼ D2 =D02 Fig. 7 in [23]
D2 1þD0 2þD 1þD0
D 2D0 1 D0
1+D
D2 D0 1 D0
V D1 PK
–
1
–
1
1
V D2 PK
–
1
–
1
V D0 PK Isrms
1 1þD0 pffiffiffi D 1þD0
1 2D0 pffiffiffi D 2D0
D pffiffiffiffi D
1 D0 D D0 pffiffiffi D D0
ID1 avg ¼ ID2 avg
–
–
DD0
D
D2 D02 1 D0 12D D02 1 D0 D 02 D pffiffiffi D D02 D 0 D
ID0 avg
D0 1þD0
D 1þD0 pffiffiffi D 1þD0 DD0 1þD0 D0 1þD0 pffiffiffiffiffiffi0 DD 1þD0 pffiffiffiffiffiffi0 DD 1þD0
D2 D0 ð1þD0 Þ 1 D0 23D D0 ð1þD0 Þ 1 D0 D D0 ð1þD0 Þ pffiffiffi D 0 D ð1þD0 Þ D 0 1þD D0 1þD0 qffiffiffiffi 1 D 1þD0 D0 pffiffiffiffiffiffi0 DD 1þD0
D2
VsPk
D 1þD0 2 1þD0
1 2 qffiffiffiffi
D0 pffiffiffiffiffiffiffiffi0 DD
D0 qffiffiffiffi
M
ICrms IC1 rms Silicon utilization factor *
– pffiffiffiffiffiffi0
DD 1þD0 pffiffiffi D 2 ð1
0
þDÞ
ð1þD0 ÞðDÞ3=2 2þD
0
D ðDÞ
3=2
1 2 1 2
D D0
qffiffiffiffi D D0
pffiffiffiffi D D 0
Valid for 0 D 2=3. Voltages are normalized to Vg, while currents are normalized to I0.
0 ðDÞ3=2 1þD
1
D D0
1 D0
qffiffiffiffi
qffiffiffiffi
D D0
D D0
0 0
3=2
D ðDÞ
D ðDÞ3=2 0
237
E.H. Ismail / Energy Conversion and Management 50 (2009) 232–239
It should be mentioned here that the quadratic buckboost converter presented in [23] operates properly only when D 0:5 with M being equal to D2 =D02 . When D 0:5, the output voltage V0 is clamped to the input voltage Vg so that the step-up mode is not possible. Thus, the proposed converter of Fig. 3d has two distinct advantages over the quadratic buckboost converter [23], namely it provides extended duty-cycle in step-down mode, and step-up
function capability. Moreover, the Type-3 converters operate at a higher duty ratio compared to their conventional counterparts provided that M is the same for both converters. The relationship between the duty ratio D for the converter of Fig. 3d and DQBB (the duty ratio in the quadratic buckboost converter) is given by the following relation:
D2 ¼M¼ D ð1 þ D0 Þ
0
DQBB 1 DQBB
2
)D¼
h pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffii 1 3 þ 1 þ 8De 2ðDe 1Þ ð14Þ
where
De ¼
2 1 DQBB DQBB
ð15Þ
The Type-3 converters are more suitable for extreme low voltage conversion ratio than the quadratic buckboost converters. For example, consider M = 0.01, then according to (14), the value of D is 40.6% higher than DQBB, which is an attractive feature. Similar to the Type-2 converters, both the input inductor L1 and the output inductor L0 must be carefully selected to ensure CCM operation. The condition for the output inductor L0 to achieve CCM operation is similar to (8), whereas the inductance value of L1 required for CCM operation is given by
L1 > Fig. 7. Ideal voltage conversion ratio M as a function of duty-cycle D.
a
b
c
d
0 2 1 D ð1 þ D0 Þ RLmax T s 2 D
Fig. 8. Normalized switch and output diode (D0) voltage and current stress as a function of voltage conversion ratio M.
ð16Þ
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4. Topologies comparison Table 1 summarizes the DC voltage gain and the switch and diodes stresses for the proposed converters as well as for other previously proposed single-switch large step-down topologies. The voltage gain for these converters is graphically illustrated in Fig. 7. It can be seen from Fig. 7 that both Type-2 and Type-3 converters have an advantage of extended duty-cycle range, i.e., for the same duty-cycle, they provide the lowest voltage gain compared to other topologies. This high step-down conversion ratio makes the proposed converters suitable for applications with a high difference between the input and output voltage. Note that the Type-1 converter and Type-0 converters (converters of Fig. 4, 6 and 7 in [26]) are not suitable for very extreme step-down voltage conversion ratio applications since it requires designing the converter for a very low duty-cycle operation which will decrease the switching frequency limits as well as it degrades the overall system efficiency. Besides the extended duty-cycle, the proposed converters also reduce the voltage and current stress on the output rectifier diode D0 as shown in Fig. 8a and b. This allows using lower voltage rated diodes; hence, the conduction loss and switching loss could be reduced leading to efficiency improvement. The normalized switch peak voltage and rms current stresses are shown in Fig. 8c and d, respectively. It is clear from Fig. 8c that Type-2 and Type-3 converters are subjected to a higher voltage stress compared to their conventional quadratic converters counterparts. On the other hand, Fig. 8d shows that the switch current stress for Type-2 and Type-3 are lower than their conventional quadratic converters. Therefore, it is useful to compare the switch performance for these converters in terms of active switch utilization (U) [3]. The active switch utilization factor, which is defined as the converter output power divided by the product of the active switch peak voltage times its rms current, represents how well a circuit topology uses the capability of its switches to achieve the output power. Converters having high values of U factor implies the power that a switching device processes for a given output is reduced, which can alleviate conduction and switching loss; hence, it operates with a relatively higher efficiency. Thereby, evaluating U factor is a good tool to compare different converter topologies. Fig. 9 shows the U factor for the proposed topologies as well as for other previously presented large step-down topologies. Referring to Fig. 9, it can be seen that Type-1 converter exhibits the best switch utilization, and therefore it has the lowest conduction loss compared to other topologies. As a matter of fact, for low values of M, the active switch in Type-1 converter is utilized better than
Fig. 9. Active switch utilization factor U as a function of voltage conversion ratio, M.
the active switch in the conventional buck converter. Recall that, the U factor in the conventional buck converter is equal to (M)1/2. Moreover, Fig. 9 also shows that the U factor for Type-2 and Type-3 converters is higher than their conventional counterparts. From Table 1, one can also show that the current stress through the capacitor C, and diodes D1 and D2 for the proposed topologies are less than their conventional counterparts. However, the current stress in the output capacitor C0 in all the topologies shown in Table 1 (except for the quadratic buck and the converter of Fig. 4 in [23]) is relatively high. Therefore, the output capacitor needs to have a low equivalent-series-resistance (ESR) to ensure a high efficiency and low ripple voltage.
5. Experimental results A type 2 converter, Fig. 3b, has been constructed for M = 0.1 to demonstrate feasibility. The prototype was built using the following parameter set:
Fig. 10. Experimental waveforms for the converter of Fig. 3(b). (Vg = 100 V, V0 = 10 V, Pout = 40 W).
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Vg = 100 V, V0 = 10 V, Pout = 40 W L1 = 1 mH, L0 = 330 lH, C = C0 = 220 lF Switch S: FQA48N20 (200 V/48 A, RDSon = 37 mX typical and 50 mX maximum) Diodes D1 and D2: SDP10S30 (300 V/10 A) Diodes D0: MBR2080CT (80 V/10 A) The converter is switched at 100 kHz with a duty ratio of 0.4 (according to (9)). The experimental waveforms at full-load are depicted in Fig. 10. Referring to Fig. 10a, the measured DC output voltage V0 is 9.65 V. The switch S and diode D1 blocking voltage are shown in Fig. 10b, whereas Fig. 10c shows the voltage across diodes D0 and D2. It is clear from Fig. 10 that the measured results are in a good agreement with the theoretical results shown in Table 1. The measured full-load efficiency of the prototype converter is about 90.9%. 6. Conclusions This paper has presented a new family of single-switch PWM converters suitable for step-down application – in particular for high frequency applications where the wide voltage ranges between the input and output call for an extremely step-down conversion ratio. The operation principle in CCM and boundary operating condition are presented. The proposed converters are regulated by the conventional PWM technique at a constant frequency. Comparison with other step-down topologies shows that the proposed converters have better characteristics over the conventional DC–DC converters with respect to the wide duty-cycle range, reduced current stress, and semiconductor utilization. Consequently, the system efficiency gets improved. The experimental result with a 40-W hardware prototype is also included to support the validity of the proposed concept. Finally, the extended duty-cycle property makes some of the proposed topologies as a good candidate for universal-line power factor correction applications. References [1] Kassakian JG, Miller JM, Traub N. Automotive electronics power up. IEEE Spectrum 2000;37(5):34–9. [2] Graf A. Semiconductors in the 42V PowerNet. In: Intertech-42V automotive systems conference; 2001. p. 1–11. [3] Erickson RW, Makismovic D. Fundamentals of power electronics. 2nd ed. USA: Kluwer Academic Publishers; 2001. [4] Matsuo H, Harada K. The cascade connection of switching regulators. IEEE Trans Ind Appl 1976;12(2):192–8.
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[5] Middlebrook RD. Transformerless DC-to-DC converters with large conversion ratios. IEEE Trans. Power Electron 1988;3(4):484–8. [6] Morales-Saldaña JA, Carbajal-Gutiérrez EE, Leyva-Ramos J. Modelling of switch-mode DC–DC cascade converters. IEEE Trans Aerospace Electron Syst 2002;38(1):295–9. [7] Rico M, Uceda J, Sebastian J, Aldana F. Static and dynamics modelling of tapped-inductor DC-to-DC converters. In: IEEE power electronics specialists conference; 1987. p. 281–88. [8] Lethellier PR. Buck converter with inductive turn ratio optimization. US Patent 6 094 038; July 2000. [9] Lenk R. Introduction to the tapped buck converter. In: High freq. power conversion (HFPC); 2000. p. 155–66. [10] Grant DA, Darroman Y. Extending the tapped-inductor DC-to-DC converter family. Electron Lett 2001;37(3):145–6. [11] Wei J, Xu P, Wu H-P, Lee FC, Yao K, Ye M. Comparison of three topology candidates for 12 V VRM. In: IEEE applied power electronics conference; 2001. p. 245–51. [12] Xu P, Wei J, Yao K, Meng Y, Lee FC. Investigation of candidate topologies for 12V VRM. In: IEEE applied power electronics conference; 2002. p. 686–92. [13] Darroman Y, Ferré A. 42-V/3-V Watkins–Johnson converter for automotive use. IEEE Trans Power Electron 2006;21(3):592–602. [14] Xu P, Wei J, Lee FC. The active-clamp couple-buck converter-a novel high efficiency voltage regulator module. In: IEEE applied power electronics conference; 2001. p. 252–57. [15] Kingston J, Morrison R, Egan MG, Hallissey G. Application of a passive lossless snubber to a tapped inductor buck DC/DC converter. In: IEEE power electronics, machines drives; 2002. p. 445–50. [16] Qian J. Voltage regulator with clamping circuit. US Patent 6507174; January 2003. [17] Yao K, Ye M, Xu M, Lee FC. Tapped-inductor buck converter for highstep-down DC–DC conversion. IEEE Trans Power Electron 2005;20(4): 775–80. [18] Yao K, Qiu YM, Xu M, Lee FC. A novel winding-coupled buck converter for highfrequency, high-step-down DC–DC conversion. IEEE Trans Power Electron 2005;20(5):1017–24. [19] Xu P, Wei J, Lee FC. Multiphase coupled-buck converter – a novel high efficient 12 V voltage regulator module. IEEE Trans Power Electron 2003;18(1):74–82. [20] Park J-H, Cho B-H. The zero voltage switching (ZVS) critical conduction mode (CRM) buck converter with tapped-inductor. IEEE Trans Power Electron 2005;20(4):762–74. [21] Park J-H, Cho B-H. Nonisolation soft-switching buck converter with tappedinductor for wide-input extreme step-down applications. IEEE Trans Circ SystI: Regular Papers 2007;54(8):1809–18. [22] Birca-Galateanu S. Buck-flyback DC–DC converter. IEEE Trans Aerospace Electron Syst 1988;24(6):800–7. [23] Makdmovic D, Cuk S. Switching converters with wide DC conversion range. IEEE Trans Power Electron 1991;6(1):151–7. [24] Barbosa L, Vieira JB, de Freitas LC, Vilela MS, Farias VJ. A buck quadratic PWM soft-switching converter using a single active switch. IEEE Trans Power Electron 1999;14(3):445–53. [25] Pacheco VM, Do Nascimento AJ, Farias VJ, Vieira JB, de Freitas LC. A quadratic buck converter with lossless commutation. IEEE Trans Ind Electron 2000;47(2):264–72. [26] Axelrod B, Berkovich Y, Ioinovici A. Switched-capacitor (SC)/switched inductor (SL) structures for getting hybrid step-down Cuk/Sepic/Zeta converters. IEEE Int Symp Circ Syst (ISCAS) 2006:5063–6.