- Email: [email protected]
LePix—A high resistivity, fully depleted monolithic pixel detector
Nuclear Instruments and Methods in Physics Research A 732 (2013) 91–94
Contents lists available at ScienceDirect
Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
LePix—A high resistivity, fully depleted monolithic pixel detector P. Giubilato a,b,n, D. Bisello a,b, P. Chalmet e, P. Denes f, K. Kloukinas d, S. Mattiazzo a,b, A. Marchioro d, H. Mugnier e, D. Pantano a,b, A. Potenza a,c, A. Rivetti a, J. Rousset e, W. Snoeys d, C. Tindall f a
INFN Padova, Padova, Italy Dipartimento di Fisica, University of Padova, via Marzolo 8, 35131 Padova, Italy c Dipartimento di Fisica, University of Torino, Torino, Italy d CERN, Geneva, Switzerland e MIND—Micro Technologies, Bât Archamps, France f LBNL—Lawrence Berkeley National Laboratory, Berkeley, CA, USA b
art ic l e i nf o
a b s t r a c t
Available online 18 June 2013
The LePix project explores monolithic pixel sensors fabricated in a 90 nm CMOS technology built over a lightly doped substrate. This approach keeps the advantages usually offered by Monolithic Active Pixel Sensors (MAPS), like a low input capacitance, having a single piece detector and using a standard CMOS production line, and adds the benefit of charge collection by drift from a depleted region several tens of microns deep into the substrate, therefore providing an excellent signal to noise ratio and a radiation tolerance superior to conventional un-depleted MAPS. Such sensors are expected to offer significant cost savings and reduction of power consumption for the same performance, leading to the use of much less material in the detector (less cooling and less copper), addressing one of the main limitations of present day particle tracking systems. The latest evolution of the project uses detectors thinned down to 50 μm to obtain back illuminated sensors operated in full depletion mode. By back-processing the chip and collecting the charge from the full substrate it is hence possible to efficiently detect soft X-rays up to 10 keV. Test results from first successfully processed detectors will be presented and discussed. & 2013 Elsevier B.V. All rights reserved.
Keywords: CMOS Monolithic Pixels Detector X-ray
1. Introduction The LePix project targets high speed particle imaging and/or tracking applications, like those found in High Energy Physics (HEP), medical imaging or X-rays imaging. The HEP community in particular faced the challenge of particles tracking at the LHC experiments, where high speed (40 MFrames/s), granularity (100 μm pixels) and extreme radiation tolerance (1015 neutrons/cm2) were paramount [1]. Special pixel detectors have been developed during the last decade mostly inside the HEP community to address the challenge of particle tracking at LHC experiments. The specific requirements for speed, spatial resolution and radiation hardness, among others, lead to a common solution adopted in different flavors by all the major experiments, the so-called hybrid pixel detectors [1]. In recent years, a new technology started to be investigated to realize detectors with performances n Corresponding author at: Dipartimento di Fisica, University of Padova, via Marzolo 8, 35131 Padova, Italy. Tel.: +39 0498277215; fax: +39 0498277237. E-mail addresses: [email protected], [email protected] (P. Giubilato).
0168-9002/$ - see front matter & 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.nima.2013.05.189
similar to those of hybrid detectors: the Monolithic Active Pixel Sensors (MAPS). Differently from hybrid detectors, MAPS integrate sensor and readout in one piece of silicon, therefore favorably comparing in terms of assembly, production cost and simplicity [2]. Lacking the parasitic capacitance introduced by the connection between the detector and the collection node, monolithic devices exhibit very low detector capacitance (on the order of some fF), allowing for low power operation. In traditional monolithic detectors charge is collected by diffusion, which means an intrinsic low signal (collection range of ∼10 μm) and low resistance to radiation damage, one of the main reasons they have not yet been widely adopted for HEP. Moreover, a 10 μm collection range makes such detectors impractical to record even low energy (100 eV– 10 keV) X-rays, which have an absorption length in silicon up to some tens of microns. Charge collection by diffusion was a mandatory choice as the substrate (the silicon support the active electronic layer is built upon) is usually made by very low resistivity silicon, which makes it unsuitable for depletion. Further limitations arise from the fact that the electronics shares the space with the collection node inside the pixel. Therefore the number of transistors must be limited, to avoid a rise in the detector
92
P. Giubilato et al. / Nuclear Instruments and Methods in Physics Research A 732 (2013) 91–94
capacitance, and their type can be limited, depending on the technology, to avoid their body from subtracting signal charge to the collection node [3]. Anyway, most recent MAPS processes started to be available with high-resistivity epitaxial layers or high-resistivity substrates, like LePix. Most recent results from high-resistivity epitaxial layer monolithic pixels demonstrate how such technology can improve MAPS radiation tolerance and general performances level of more than one order of magnitude [4], leading to radiation tolerance in excess of 1013 neutrons/cm2. The LePix detector joins this trend, taking the monolithic technology to a performance level comparable, and even superior in many aspects, to the hybrid pixel one, maintaining at the same time the production, assembly and cost advantages characteristics of the monolithic approach.
2. Detector design Two mechanisms exist to collect charge generated in silicon by ionizing radiation: diffusion and drift. In the case of diffusion there is no strong force acting on the charge carriers and the process is slow (some hundreds of ns), increasing the chance for the charge carriers to be captured by defects or traps in the material. Charge collection by diffusion is used in traditional monolithic pixel detectors, where radiation tolerance therefore does not exceed fluences of 1012–1013 neutrons/cm2, often already with significant performance degradation at lower fluences. Charge collection is limited to a 10–15 μm epitaxial layer into the material, therefore limiting signal size, yielding signal-to-noise ratios for minimum ionizing particles of only a few tens despite the very small collection electrode capacitance of a few fF. In the same way, the thin collection layer limits detection efficiency for X-rays in the 100 eV–10 keV range to some per cent. In contrast silicon detectors which collect signal charge primarily by drift show tolerance to fluences of 1015 neutrons/cm2, and collect charge over a depth of several hundred microns in a few nanoseconds. To achieve this, an electric field and hence depletion is needed over this depth requiring a high resistivity substrate. The higher the resistivity, the easier the depletion and the charge collection over a certain depth will be achieved. The LePix detector is a monolithic pixel detector built with 90 nm IBM CMOS process over a mid-resistive substrate. By depleting the substrate with reasonably low voltages (less than 100 V) it is therefore possible to implement the charge collection by drift within a monolithic detector. Charge collection by drift requires a substrate of sufficiently high resistivity, the higher the better. IBM offers substrates above 500 Ω cm on all their CMOS technologies, even including the very advanced ones processed on 300 mm wafers. This is important for a number of reasons: first, a doping level within one order of magnitude of that of traditional detectors allows charge collection by drift with very low bias voltages. Second, advanced technologies (90 nm or better) will be needed for high speed data transmission and to reduce the dead areas at the detector periphery due to the ancillary circuits, thus facilitating the tiling of the detectors to cover large areas uniformly. Third, wafer size will be crucial to manufacture large detectors by stitching. For the LePix detector development the 90 nm CMOS process has been chosen, as it is the first technology offered with low-k dielectrics in the metal stack, so that even with high metal density the parasitics remain limited. The detector matrix is formed by a two-dimensional array of Nwell diffusions into a P-type substrate of moderate resistivity (500 Ω cm). Each of these N-well diffusions creates the detecting diode for one pixel. The N-well diffusion forms the charge collection electrode, and contains the local readout circuit for the pixel. The local readout circuit is connected to the periphery
where the remainder of the readout circuit is located in an N-well. The NMOS transistors are systematically placed in a P-well inside the N-well (use of triple well technology). Charge collection electrodes and readout circuit are biased near ground (a power supply of ∼1 V) with the P-type substrate negatively biased to several Volts. To sustain the reverse substrate voltage, readout circuit and detector matrix are surrounded by a guard ring structure. By applying a sufficient reverse substrate bias a bathtub shaped depletion layer forms underneath the detector matrix, ending near the outer edge of the guard ring. The substrate bias is applied through a top side contact placed outside the guard ring area. The actual detector is a 32 32 pixels matrix of 50 μm pixel pitch. The matrix columns are further divided into four different groups of 8 32 pixels, each sector implementing a different input device. Sector 1 and 2 both use thin oxide PMOS transistors, smaller in the first and bigger in the second. Sector 3 implements a thick oxide PMOS transistor and sector 4 an NMOS one. The thin oxide transistors exhibit more gate leakage, which is not an issue in the thick oxide PMOS. The NMOS input device does not exhibit this problem, at the price of a much larger parasitic capacitance. In the pixels of the other rows the injection capacitor is present but it is connected to a fixed voltage. Analog and digital powers are separated, and nominal power supply is 1.2 V for both. All logic signals are CMOS 1.2 V. The substrate is reverse biased with respect to the circuit, and a special guard ring structure has been introduced to allow a large reverse bias (∼100 V). The pixel matrix is based on an analog serial readout, with double sampling of the analog voltage level simultaneously for each pixel at the beginning and at the end of the (programmable) integration time. The difference between the two stored voltage levels corresponds to the signal plus the integral of the pixel leakage current. This readout is very similar to a traditional serial MAPS readout, but with the difference that the voltage levels are stored outside of the pixel at the same time. This way the duration of the sensitive period can be decoupled from the readout time. The choice of storing the signal out of the pixel means each pixel is connected by a line to the periphery.
3. Characterization and calibration To characterize the base material after the full CMOS process, the depletion thickness as a function of reverse bias has been derived from CV measurements on a diode (∼770 μm2) test structure. Several tens of microns of depletion have been reached with some of tens of volts bias, and measurements indicate a substrate resistivity around 400 Ω cm. The substrate current as a function of reverse bias was measured for both the diode and the pixel matrix (Fig. 1). We do not observe hard breakdown but a gradual current increase with bias until a point is reached where the current is no longer constant in time but increases, indicating some thermal runaway phenomenon. This happens for a different bias for the matrix than for the diode but the phenomenon is the same. The peripheral current does not affect the pixels in the matrix, but remains undesirable. We believe it is possible to eliminate this current and we also intend to simplify the guard ring structure, quite complex due to density design rules, and reduce its width. The different pixel variants included into the matrices were also characterized. The measurements were taken with a reset voltage of 730 mV for sectors 1, 2 and 3, and 1 V for sector 4 with the NMOS input transistors needing a somewhat higher bias. Since the depletion is expected to extend far down into the substrate, the pixel capacitance only weakly depends on the substrate bias. The leakage current increases as expected. The equivalent noise charge was extracted as a function of integration time, and the
P. Giubilato et al. / Nuclear Instruments and Methods in Physics Research A 732 (2013) 91–94
Fig. 1. IV characteristic for the test diode.
Fig. 3. Spectrum obtained from
93
55
Fe source, matrix 1 sector 1.
Fig. 2. Measured Equivalent Noise Charge (ENC) as a function of integration time (Vsub ¼ −30 V). Fig. 4. Photons penetration in silicon depending on energy.
curves were fitted to extract the noise contribution from the leakage current (Fig. 2). This yields actually a good correspondence with the measured leakage current. The pixel matrix was exposed, at room temperature, to a 55Fe source, providing the spectrum in Fig. 3 for sector 1 with a substrate bias voltage of −20 V. The conversion gain is ∼6 e−/ADC count. The two photoelectron peaks (at 5.90 keV and 6.45 keV respectively) can clearly be distinguished, illustrating the potential of the device with respect to low input capacitance (∼5 fF) and signal-to-noise. The sigma of the two peaks is about 140 eV, corresponding to less than 40 electrons. This number can be improved with a faster circuit: it was observed that a reduced integration time reduced the noise indicating leakage current dominated noise. For practical reasons the integration time could not be reduced below 10 μs, for which for an observed pixel leakage current of 3.5 pA yields about 15 electrons noise.
4. Radiation hardness As a quick test, one pixel matrix was kept under bias and irradiated using 10 keV X-rays up to a dose of 10 Mrad. The dose rate was 4.8 krad/min. The readout circuit remained functional throughout the irradiation [5]. In some sectors severe shifts (hundreds of millivolt) in the analog output could be observed immediately after irradiation and in others not, but a room temperature anneal for one week allowed the device to almost fully recover with reasonable residual shifts. The 10 Mrad dose was given in hours, compared to years in an experiment, these results
demonstrate a tolerance to ionizing dose adequate for high energy physics. To investigate displacement damage, samples have been irradiated at the neutron irradiation facility in Ljubljana, with neutron fluences between 1012 n/cm2 and 2 1015 n/cm2 [5]. To avoid edge effects we limited the substrate reverse bias to 40 V. For doses up to 2 1013 n/cm2 the capacitance of the large diode changes by less than 1 pF, but at 1014 n/cm2 leakage current increases significantly and diode capacitance rises as well [5]. At 2 1015 n/cm2 it was not even possible to get a reliable measurement due to saturation of the device.
5. Back thinning and processing Considering the substrate resistivity reported above (about 400 Ω cm) it is evident how, limiting the bias voltage to about 100 V, it is impossible to fully deplete the 300 μm thick substrate. While the detector can actually withstand higher depletion voltages, 100 V is already a potential which requires some care to handle; for practical applications the goal is to deplete the device with even lower biases, to further simplify the whole system, hence we consider 100 V a practical limit for the bias voltage. Full depletion is a key element in detecting low-penetrating radiation, like near-UV photons, which absorption length in silicon can reach less than 100 nm (Fig. 4). By illuminating a device from the active electronic side (conventionally called front) such radiation would get lost before reaching the active area due to the thickness of the
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Fig. 5. 55Fe 5.9 keV X-rays peak measured by a processed and back-illuminated LePix sensor.
electronic and metal layers. Moreover, even for more penetrating radiation, the metal layers cause both reflexions and absorption, hence reducing the detection efficiency for many low-energy particles. To overcome this limitation is possible to illuminate the device from the back-side, avoiding the radiation interaction with the passive layers. To render this approach effective, anyway, the depletion region should ideally extend to the back surface of the device, making it possible to collect even the charge generated in the first nanometers of the substrate by the low penetrating radiation. A device implementing such condition is called fullydepleted; as its entire volume becomes actually sensible to particles interaction generated charge. Therefore, a set of chips has been back-thinned to 50 μm using a commercial grinding technique [6], which has been already successfully employed for back-thinning other MAPS [7]. After thinning, the sensor leakage current usually increases by more than one order of magnitude, due to the defects generated on the back-plane by the grinding process. The thinned sensors have been post-processed to create a thin entrance window on the back-plane and anneal the crystal damage generated by the thinning phase. A thin phosphor layer (p-type implant) has been implanted at 33 keV using a cold process at ∼160 1C. The dose is adjusted to obtain an amorphous layer of Si, which favours the crystal re-growth. After phosphor implant the chips were first annealed at 400 1C for 10 min in nitrogen atmosphere. After discovering that surface contact were burned and that the chips were no more working, the annealing temperature was at first lowered by 50 1C, and then by 100 1C. At 300 1C annealing the survivability of the chips greatly improved, with all chips tested so far working. The thickness of the phosphor layer is measured using spreading resistance analysis (SRA) on a sample chip, and results to be of about 0.4 μm from the back-plane surface, with the highest concentration in the first 0.2 μm. This process provides the sensors with a thin entrance window on the back-plane, ensuring in principle good transparency to X-rays down to ∼5 keV and to electrons down to ∼9 keV. 6. Full depletion test measurement To check the processing effectiveness, back-thinned and processed devices were tested with a 55Fe source, with the source facing the back side of the detector instead of the front one as in standard measurements. From Fig. 4 is apparent how the 6.9 keV main emission peak of the 55Fe has an absorption length of less than 10 μm in silicon. Considering a thickness for the active top
layers of about 5–10 μm and a 50 μm total thickness for the device (after thinning), the source X-rays detection on the back side can be obtained only by extending the depletion layer down toward the device back. Fig. 5 reports the measurement results for the processed LePix in back-illuminated configuration. The iron peak is clearly visible (room temperature, data from the pixel matrix); comparing Fig. 5 spectrum with that of Fig. 3 shows how noise has increased, making impossible to distinguish the secondary peak with this statistics. Due to slightly different biasing conditions is not possible to directly compare the two plots, as the conversion factor (ADC counts vs. collected charge) is not the same. By applying the correct conversion factors, the noise for the plot in Fig. 3 results to be equivalent to 136 eV (FWHM of the peak), while in the spectrum of Fig. 5 such noise has raised to about 340 eV FWHM. This measurement is clearly a first step only. For a precise determination of the actual depletion thickness and uniformity, and the actual behavior of the charge generated very close to the detector surface, tailored measurements are planned, including narrow-wavelength penetration measurements around the 5 eV region.
7. Conclusions Monolithic pixel detectors built in CMOS technology over moderate resistivity substrates can deliver significant performance improvements over both traditional monolithic detectors and hybrid-pixel detectors. The feasibility of such a device has been proven by the LePix prototype here illustrated. While improvements in term of higher signal to noise ratio, smaller cluster size and radiation hardness are apparent, charge collection efficiency is still unsatisfactory. Dedicated measurements anyway indicate the collection efficiency problem can be addressed by improving design details or simply going to smaller (with respect to the prototype 50 μm) pixel pitch. Novel architectures are necessary to fully exploit the potential advantages of such depleted monolithic detectors. With respect to applications in both the HEP and X-rays imaging fields, the capability of operating a monolithic pixel detector in fully depleted mode gives numerous advantages. For minimum ionizing particles it means maximizing the charge collection, leading to higher signal to noise and radiation tolerance when compared to a partially depleted detector of the same thickness. For X-rays detection, it opens the possibility of employing monolithic devices built with standard CMOS processes to detect photons up to the 10 keV range with good efficiency. Precision beam monitoring in linacs and storage rings with X-rays and soft electrons, such as profile monitoring in low emittance electron storage rings (synchrotron light sources and damping rings) [8], [9] also requires fast detectors, sensitive to X-rays of a few keV, to minimize diffraction effects. With the increased request for high resolution, fast, large area pixel detectors for X-rays applications worldwide, fully depleted monolithic sensors can provide an effective solution. References [1] N. Wermes, Nuclear Instruments and Methods A 512 (2003) 277. [2] M. Battaglia, C. Da Via, R&D Paths of Pixel Detectors for Vertex Tracking and Radiation Imaging, arXiv:1208.0251v1 [physics.ins-det], 2012. [3] P. Giubilato, et al., Perspectives for monolithic sensors in deep submicron CMOS, 8th International Meeting on Front-End Electronics, 24–27 May, 2011, Bergamo, IT. [4] M. Deveaux, et al., Radiation tolerance of a column parallel CMOS sensor with high resistivity epitaxial layer, JINST 6 C02004, 2011. [5] A. Potenza, et al., Nuclear Instruments and Methods A, in press. [6] Aptek Industries Inc., San Jose, CA, USA. [7] M. Battaglia, et al., Nuclear Instruments and Methods A 579 (2007) 675. [8] K. Iida, et al., Nuclear Instruments and Methods A 506 (2003) 341. [9] S. Takano, et al., Nuclear Instruments and Methods A 556 (2006) 357.
Contents lists available at ScienceDirect
Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
LePix—A high resistivity, fully depleted monolithic pixel detector P. Giubilato a,b,n, D. Bisello a,b, P. Chalmet e, P. Denes f, K. Kloukinas d, S. Mattiazzo a,b, A. Marchioro d, H. Mugnier e, D. Pantano a,b, A. Potenza a,c, A. Rivetti a, J. Rousset e, W. Snoeys d, C. Tindall f a
INFN Padova, Padova, Italy Dipartimento di Fisica, University of Padova, via Marzolo 8, 35131 Padova, Italy c Dipartimento di Fisica, University of Torino, Torino, Italy d CERN, Geneva, Switzerland e MIND—Micro Technologies, Bât Archamps, France f LBNL—Lawrence Berkeley National Laboratory, Berkeley, CA, USA b
art ic l e i nf o
a b s t r a c t
Available online 18 June 2013
The LePix project explores monolithic pixel sensors fabricated in a 90 nm CMOS technology built over a lightly doped substrate. This approach keeps the advantages usually offered by Monolithic Active Pixel Sensors (MAPS), like a low input capacitance, having a single piece detector and using a standard CMOS production line, and adds the benefit of charge collection by drift from a depleted region several tens of microns deep into the substrate, therefore providing an excellent signal to noise ratio and a radiation tolerance superior to conventional un-depleted MAPS. Such sensors are expected to offer significant cost savings and reduction of power consumption for the same performance, leading to the use of much less material in the detector (less cooling and less copper), addressing one of the main limitations of present day particle tracking systems. The latest evolution of the project uses detectors thinned down to 50 μm to obtain back illuminated sensors operated in full depletion mode. By back-processing the chip and collecting the charge from the full substrate it is hence possible to efficiently detect soft X-rays up to 10 keV. Test results from first successfully processed detectors will be presented and discussed. & 2013 Elsevier B.V. All rights reserved.
Keywords: CMOS Monolithic Pixels Detector X-ray
1. Introduction The LePix project targets high speed particle imaging and/or tracking applications, like those found in High Energy Physics (HEP), medical imaging or X-rays imaging. The HEP community in particular faced the challenge of particles tracking at the LHC experiments, where high speed (40 MFrames/s), granularity (100 μm pixels) and extreme radiation tolerance (1015 neutrons/cm2) were paramount [1]. Special pixel detectors have been developed during the last decade mostly inside the HEP community to address the challenge of particle tracking at LHC experiments. The specific requirements for speed, spatial resolution and radiation hardness, among others, lead to a common solution adopted in different flavors by all the major experiments, the so-called hybrid pixel detectors [1]. In recent years, a new technology started to be investigated to realize detectors with performances n Corresponding author at: Dipartimento di Fisica, University of Padova, via Marzolo 8, 35131 Padova, Italy. Tel.: +39 0498277215; fax: +39 0498277237. E-mail addresses: [email protected], [email protected] (P. Giubilato).
0168-9002/$ - see front matter & 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.nima.2013.05.189
similar to those of hybrid detectors: the Monolithic Active Pixel Sensors (MAPS). Differently from hybrid detectors, MAPS integrate sensor and readout in one piece of silicon, therefore favorably comparing in terms of assembly, production cost and simplicity [2]. Lacking the parasitic capacitance introduced by the connection between the detector and the collection node, monolithic devices exhibit very low detector capacitance (on the order of some fF), allowing for low power operation. In traditional monolithic detectors charge is collected by diffusion, which means an intrinsic low signal (collection range of ∼10 μm) and low resistance to radiation damage, one of the main reasons they have not yet been widely adopted for HEP. Moreover, a 10 μm collection range makes such detectors impractical to record even low energy (100 eV– 10 keV) X-rays, which have an absorption length in silicon up to some tens of microns. Charge collection by diffusion was a mandatory choice as the substrate (the silicon support the active electronic layer is built upon) is usually made by very low resistivity silicon, which makes it unsuitable for depletion. Further limitations arise from the fact that the electronics shares the space with the collection node inside the pixel. Therefore the number of transistors must be limited, to avoid a rise in the detector
92
P. Giubilato et al. / Nuclear Instruments and Methods in Physics Research A 732 (2013) 91–94
capacitance, and their type can be limited, depending on the technology, to avoid their body from subtracting signal charge to the collection node [3]. Anyway, most recent MAPS processes started to be available with high-resistivity epitaxial layers or high-resistivity substrates, like LePix. Most recent results from high-resistivity epitaxial layer monolithic pixels demonstrate how such technology can improve MAPS radiation tolerance and general performances level of more than one order of magnitude [4], leading to radiation tolerance in excess of 1013 neutrons/cm2. The LePix detector joins this trend, taking the monolithic technology to a performance level comparable, and even superior in many aspects, to the hybrid pixel one, maintaining at the same time the production, assembly and cost advantages characteristics of the monolithic approach.
2. Detector design Two mechanisms exist to collect charge generated in silicon by ionizing radiation: diffusion and drift. In the case of diffusion there is no strong force acting on the charge carriers and the process is slow (some hundreds of ns), increasing the chance for the charge carriers to be captured by defects or traps in the material. Charge collection by diffusion is used in traditional monolithic pixel detectors, where radiation tolerance therefore does not exceed fluences of 1012–1013 neutrons/cm2, often already with significant performance degradation at lower fluences. Charge collection is limited to a 10–15 μm epitaxial layer into the material, therefore limiting signal size, yielding signal-to-noise ratios for minimum ionizing particles of only a few tens despite the very small collection electrode capacitance of a few fF. In the same way, the thin collection layer limits detection efficiency for X-rays in the 100 eV–10 keV range to some per cent. In contrast silicon detectors which collect signal charge primarily by drift show tolerance to fluences of 1015 neutrons/cm2, and collect charge over a depth of several hundred microns in a few nanoseconds. To achieve this, an electric field and hence depletion is needed over this depth requiring a high resistivity substrate. The higher the resistivity, the easier the depletion and the charge collection over a certain depth will be achieved. The LePix detector is a monolithic pixel detector built with 90 nm IBM CMOS process over a mid-resistive substrate. By depleting the substrate with reasonably low voltages (less than 100 V) it is therefore possible to implement the charge collection by drift within a monolithic detector. Charge collection by drift requires a substrate of sufficiently high resistivity, the higher the better. IBM offers substrates above 500 Ω cm on all their CMOS technologies, even including the very advanced ones processed on 300 mm wafers. This is important for a number of reasons: first, a doping level within one order of magnitude of that of traditional detectors allows charge collection by drift with very low bias voltages. Second, advanced technologies (90 nm or better) will be needed for high speed data transmission and to reduce the dead areas at the detector periphery due to the ancillary circuits, thus facilitating the tiling of the detectors to cover large areas uniformly. Third, wafer size will be crucial to manufacture large detectors by stitching. For the LePix detector development the 90 nm CMOS process has been chosen, as it is the first technology offered with low-k dielectrics in the metal stack, so that even with high metal density the parasitics remain limited. The detector matrix is formed by a two-dimensional array of Nwell diffusions into a P-type substrate of moderate resistivity (500 Ω cm). Each of these N-well diffusions creates the detecting diode for one pixel. The N-well diffusion forms the charge collection electrode, and contains the local readout circuit for the pixel. The local readout circuit is connected to the periphery
where the remainder of the readout circuit is located in an N-well. The NMOS transistors are systematically placed in a P-well inside the N-well (use of triple well technology). Charge collection electrodes and readout circuit are biased near ground (a power supply of ∼1 V) with the P-type substrate negatively biased to several Volts. To sustain the reverse substrate voltage, readout circuit and detector matrix are surrounded by a guard ring structure. By applying a sufficient reverse substrate bias a bathtub shaped depletion layer forms underneath the detector matrix, ending near the outer edge of the guard ring. The substrate bias is applied through a top side contact placed outside the guard ring area. The actual detector is a 32 32 pixels matrix of 50 μm pixel pitch. The matrix columns are further divided into four different groups of 8 32 pixels, each sector implementing a different input device. Sector 1 and 2 both use thin oxide PMOS transistors, smaller in the first and bigger in the second. Sector 3 implements a thick oxide PMOS transistor and sector 4 an NMOS one. The thin oxide transistors exhibit more gate leakage, which is not an issue in the thick oxide PMOS. The NMOS input device does not exhibit this problem, at the price of a much larger parasitic capacitance. In the pixels of the other rows the injection capacitor is present but it is connected to a fixed voltage. Analog and digital powers are separated, and nominal power supply is 1.2 V for both. All logic signals are CMOS 1.2 V. The substrate is reverse biased with respect to the circuit, and a special guard ring structure has been introduced to allow a large reverse bias (∼100 V). The pixel matrix is based on an analog serial readout, with double sampling of the analog voltage level simultaneously for each pixel at the beginning and at the end of the (programmable) integration time. The difference between the two stored voltage levels corresponds to the signal plus the integral of the pixel leakage current. This readout is very similar to a traditional serial MAPS readout, but with the difference that the voltage levels are stored outside of the pixel at the same time. This way the duration of the sensitive period can be decoupled from the readout time. The choice of storing the signal out of the pixel means each pixel is connected by a line to the periphery.
3. Characterization and calibration To characterize the base material after the full CMOS process, the depletion thickness as a function of reverse bias has been derived from CV measurements on a diode (∼770 μm2) test structure. Several tens of microns of depletion have been reached with some of tens of volts bias, and measurements indicate a substrate resistivity around 400 Ω cm. The substrate current as a function of reverse bias was measured for both the diode and the pixel matrix (Fig. 1). We do not observe hard breakdown but a gradual current increase with bias until a point is reached where the current is no longer constant in time but increases, indicating some thermal runaway phenomenon. This happens for a different bias for the matrix than for the diode but the phenomenon is the same. The peripheral current does not affect the pixels in the matrix, but remains undesirable. We believe it is possible to eliminate this current and we also intend to simplify the guard ring structure, quite complex due to density design rules, and reduce its width. The different pixel variants included into the matrices were also characterized. The measurements were taken with a reset voltage of 730 mV for sectors 1, 2 and 3, and 1 V for sector 4 with the NMOS input transistors needing a somewhat higher bias. Since the depletion is expected to extend far down into the substrate, the pixel capacitance only weakly depends on the substrate bias. The leakage current increases as expected. The equivalent noise charge was extracted as a function of integration time, and the
P. Giubilato et al. / Nuclear Instruments and Methods in Physics Research A 732 (2013) 91–94
Fig. 1. IV characteristic for the test diode.
Fig. 3. Spectrum obtained from
93
55
Fe source, matrix 1 sector 1.
Fig. 2. Measured Equivalent Noise Charge (ENC) as a function of integration time (Vsub ¼ −30 V). Fig. 4. Photons penetration in silicon depending on energy.
curves were fitted to extract the noise contribution from the leakage current (Fig. 2). This yields actually a good correspondence with the measured leakage current. The pixel matrix was exposed, at room temperature, to a 55Fe source, providing the spectrum in Fig. 3 for sector 1 with a substrate bias voltage of −20 V. The conversion gain is ∼6 e−/ADC count. The two photoelectron peaks (at 5.90 keV and 6.45 keV respectively) can clearly be distinguished, illustrating the potential of the device with respect to low input capacitance (∼5 fF) and signal-to-noise. The sigma of the two peaks is about 140 eV, corresponding to less than 40 electrons. This number can be improved with a faster circuit: it was observed that a reduced integration time reduced the noise indicating leakage current dominated noise. For practical reasons the integration time could not be reduced below 10 μs, for which for an observed pixel leakage current of 3.5 pA yields about 15 electrons noise.
4. Radiation hardness As a quick test, one pixel matrix was kept under bias and irradiated using 10 keV X-rays up to a dose of 10 Mrad. The dose rate was 4.8 krad/min. The readout circuit remained functional throughout the irradiation [5]. In some sectors severe shifts (hundreds of millivolt) in the analog output could be observed immediately after irradiation and in others not, but a room temperature anneal for one week allowed the device to almost fully recover with reasonable residual shifts. The 10 Mrad dose was given in hours, compared to years in an experiment, these results
demonstrate a tolerance to ionizing dose adequate for high energy physics. To investigate displacement damage, samples have been irradiated at the neutron irradiation facility in Ljubljana, with neutron fluences between 1012 n/cm2 and 2 1015 n/cm2 [5]. To avoid edge effects we limited the substrate reverse bias to 40 V. For doses up to 2 1013 n/cm2 the capacitance of the large diode changes by less than 1 pF, but at 1014 n/cm2 leakage current increases significantly and diode capacitance rises as well [5]. At 2 1015 n/cm2 it was not even possible to get a reliable measurement due to saturation of the device.
5. Back thinning and processing Considering the substrate resistivity reported above (about 400 Ω cm) it is evident how, limiting the bias voltage to about 100 V, it is impossible to fully deplete the 300 μm thick substrate. While the detector can actually withstand higher depletion voltages, 100 V is already a potential which requires some care to handle; for practical applications the goal is to deplete the device with even lower biases, to further simplify the whole system, hence we consider 100 V a practical limit for the bias voltage. Full depletion is a key element in detecting low-penetrating radiation, like near-UV photons, which absorption length in silicon can reach less than 100 nm (Fig. 4). By illuminating a device from the active electronic side (conventionally called front) such radiation would get lost before reaching the active area due to the thickness of the
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Fig. 5. 55Fe 5.9 keV X-rays peak measured by a processed and back-illuminated LePix sensor.
electronic and metal layers. Moreover, even for more penetrating radiation, the metal layers cause both reflexions and absorption, hence reducing the detection efficiency for many low-energy particles. To overcome this limitation is possible to illuminate the device from the back-side, avoiding the radiation interaction with the passive layers. To render this approach effective, anyway, the depletion region should ideally extend to the back surface of the device, making it possible to collect even the charge generated in the first nanometers of the substrate by the low penetrating radiation. A device implementing such condition is called fullydepleted; as its entire volume becomes actually sensible to particles interaction generated charge. Therefore, a set of chips has been back-thinned to 50 μm using a commercial grinding technique [6], which has been already successfully employed for back-thinning other MAPS [7]. After thinning, the sensor leakage current usually increases by more than one order of magnitude, due to the defects generated on the back-plane by the grinding process. The thinned sensors have been post-processed to create a thin entrance window on the back-plane and anneal the crystal damage generated by the thinning phase. A thin phosphor layer (p-type implant) has been implanted at 33 keV using a cold process at ∼160 1C. The dose is adjusted to obtain an amorphous layer of Si, which favours the crystal re-growth. After phosphor implant the chips were first annealed at 400 1C for 10 min in nitrogen atmosphere. After discovering that surface contact were burned and that the chips were no more working, the annealing temperature was at first lowered by 50 1C, and then by 100 1C. At 300 1C annealing the survivability of the chips greatly improved, with all chips tested so far working. The thickness of the phosphor layer is measured using spreading resistance analysis (SRA) on a sample chip, and results to be of about 0.4 μm from the back-plane surface, with the highest concentration in the first 0.2 μm. This process provides the sensors with a thin entrance window on the back-plane, ensuring in principle good transparency to X-rays down to ∼5 keV and to electrons down to ∼9 keV. 6. Full depletion test measurement To check the processing effectiveness, back-thinned and processed devices were tested with a 55Fe source, with the source facing the back side of the detector instead of the front one as in standard measurements. From Fig. 4 is apparent how the 6.9 keV main emission peak of the 55Fe has an absorption length of less than 10 μm in silicon. Considering a thickness for the active top
layers of about 5–10 μm and a 50 μm total thickness for the device (after thinning), the source X-rays detection on the back side can be obtained only by extending the depletion layer down toward the device back. Fig. 5 reports the measurement results for the processed LePix in back-illuminated configuration. The iron peak is clearly visible (room temperature, data from the pixel matrix); comparing Fig. 5 spectrum with that of Fig. 3 shows how noise has increased, making impossible to distinguish the secondary peak with this statistics. Due to slightly different biasing conditions is not possible to directly compare the two plots, as the conversion factor (ADC counts vs. collected charge) is not the same. By applying the correct conversion factors, the noise for the plot in Fig. 3 results to be equivalent to 136 eV (FWHM of the peak), while in the spectrum of Fig. 5 such noise has raised to about 340 eV FWHM. This measurement is clearly a first step only. For a precise determination of the actual depletion thickness and uniformity, and the actual behavior of the charge generated very close to the detector surface, tailored measurements are planned, including narrow-wavelength penetration measurements around the 5 eV region.
7. Conclusions Monolithic pixel detectors built in CMOS technology over moderate resistivity substrates can deliver significant performance improvements over both traditional monolithic detectors and hybrid-pixel detectors. The feasibility of such a device has been proven by the LePix prototype here illustrated. While improvements in term of higher signal to noise ratio, smaller cluster size and radiation hardness are apparent, charge collection efficiency is still unsatisfactory. Dedicated measurements anyway indicate the collection efficiency problem can be addressed by improving design details or simply going to smaller (with respect to the prototype 50 μm) pixel pitch. Novel architectures are necessary to fully exploit the potential advantages of such depleted monolithic detectors. With respect to applications in both the HEP and X-rays imaging fields, the capability of operating a monolithic pixel detector in fully depleted mode gives numerous advantages. For minimum ionizing particles it means maximizing the charge collection, leading to higher signal to noise and radiation tolerance when compared to a partially depleted detector of the same thickness. For X-rays detection, it opens the possibility of employing monolithic devices built with standard CMOS processes to detect photons up to the 10 keV range with good efficiency. Precision beam monitoring in linacs and storage rings with X-rays and soft electrons, such as profile monitoring in low emittance electron storage rings (synchrotron light sources and damping rings) [8], [9] also requires fast detectors, sensitive to X-rays of a few keV, to minimize diffraction effects. With the increased request for high resolution, fast, large area pixel detectors for X-rays applications worldwide, fully depleted monolithic sensors can provide an effective solution. References [1] N. Wermes, Nuclear Instruments and Methods A 512 (2003) 277. [2] M. Battaglia, C. Da Via, R&D Paths of Pixel Detectors for Vertex Tracking and Radiation Imaging, arXiv:1208.0251v1 [physics.ins-det], 2012. [3] P. Giubilato, et al., Perspectives for monolithic sensors in deep submicron CMOS, 8th International Meeting on Front-End Electronics, 24–27 May, 2011, Bergamo, IT. [4] M. Deveaux, et al., Radiation tolerance of a column parallel CMOS sensor with high resistivity epitaxial layer, JINST 6 C02004, 2011. [5] A. Potenza, et al., Nuclear Instruments and Methods A, in press. [6] Aptek Industries Inc., San Jose, CA, USA. [7] M. Battaglia, et al., Nuclear Instruments and Methods A 579 (2007) 675. [8] K. Iida, et al., Nuclear Instruments and Methods A 506 (2003) 341. [9] S. Takano, et al., Nuclear Instruments and Methods A 556 (2006) 357.