Loading effect and temperature dependence of etch rate of silicon materials in CF4 plasma

Loading effect and temperature dependence of etch rate of silicon materials in CF4 plasma

Fully automated integrated circuit ~ire bonding system M. NARUSE, S. MIYAZAKI, T. YAMADA, K. KAWATA, Y. SAKAGAWA and K. IGARAStll NECRes. Dev. (Jpn), ...

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Fully automated integrated circuit ~ire bonding system M. NARUSE, S. MIYAZAKI, T. YAMADA, K. KAWATA, Y. SAKAGAWA and K. IGARAStll NECRes. Dev. (Jpn), 56, 163 (January 1980). Semiconductor device assembly process involves many operations using microscopes. Automation of this process has been desired for cost reduction, quality stabilisation, etc. The pattern recognition technique ha.~ been introduced into the IC assembly process and the wire bonding operation has been fully automated. The system combines the image processing unit (IPU), wire bonding machines and line-sensor cameras. One IPU determines the exact position of five bonding tools. The algorithm utilised is to detect a special array of electrodes on an IC pellet surface, which requires a comparatively small scanning field. This system was successfully introduced in the LS! production line in 1975. Loading effect and temperature dependence of etch rate of silicon materials in CF4 plasma T. ENOMOTO Solid-St. Technol. 117 (April 1980). Plasma etching of silicon materials in CF4 is evaluated with respect to dependence of etch rate on exposed area and temperature with a modified barrel type plasma reactor. The characteristics of the etch rate and activation energy for silicon dioxide were obtained. The undercut with excess etch time was also examined, and it became evident that suppression of the loading effect and improvement of the pattern undercut could be achieved by lowering the sample temperature. Optical end-point detection for the plasma etching ofaluminlum B. J. CURTIS Solid-St. Technol. 129 (April 1980). The plasma etching of aluminium conductors for integrated circuit applications is assuming ever increasing importance. In order to achieve the precise control required in VLSI processing, it is very desirable to be able to monitor the etching process. When chlorine containing etch gases are employed, a strong optical emission band centred at 261.4nm due to electronic transitions in the AICI molecule is observed. The etching process can be monitored by following the intensity of this emission. This paper describes the use of a spectrometer and also a simple solid state detector combined with an interference filter for the end-point detection ofaluminium plasma etching, utilising both emission and reflection techniques. Plasma etching for SiOz profile control J. A. BONDUR and H. A. CLARK Solid-St. Technol. 122 (April 1980). The plasma etching technology gives the process engineer a controllable technique for forming shaped holes in thick SiO2. Wet chemical etching of thick sputtered SiO2 layers results in the typical isotropic etch profile and poor control of etched image dimensions. Plasma processing, on the other hand, results in improved control of etched image dimensions and an improved ability to modify the etched image shape. The ability to tailor the etched SiO2 profile with plasma processes has been demonstrated in both high-pressure barrel reactors and the low-pressure reactive ion etch process technique, Data are presented to demonstrate the advantages and disadvantages of each of these approaches. Advances in GaAs LSI/VLSI processing technology B. M. WELCH Solid-St. TechnoL 95 (February 1980). Recent advances in GaAs processing techniques in conjunction with new fabrication and circuit approaches have made possible the development of a planar 'silicon-like' GaAs IC fabrication technology with LSI/VLSI potential. New processing methods have overcome the inherent processing difficulties that have prevented GaAs ICs from developing as rapidly as Si ICs. Already, ultrahigh performance (ra~ lOOps) digital GaAs MSI (-60-100 gates) circuits with LSIIVLSI compatible densities (<10-.~mm/gate) and power levels (<200-500 ,aW/gate) have been demonstrated. The GaAs fabrication technology described combines advanced planar device and multilevel interconnect structures with several I # m compatible LSI processes including multiple Iocalised implants, reduction photolithography, plasma etching, reactive ion etching and ion milling.

Polysilicon self-aligned technology - a new approach for bipolar l.Sis K. O K A D A , K. A O M U R A , T, NAKAMURA and tt. StlII3A NECRes. Dev. (Jim), 56, 170 (January 1980). This paper describes a new polysilicon process which has bccn developed to obtain high packing density, high speed and low-power LSIs. The new process, called the polysilicon self-aligned (PSA) technology, is based on a new fabrication concept for dimensional reduction and does not require fine patterning and accurate mask alignment. As a production example of this new process, an emitter-coupled logic (ECL) gate with 0.6ns delay time, (I.5 pJ power-delay product and 64(X} p.m 2 gate area has been achieved. Furthermore, by introducing a polysilicon diode (PSD) and Shottky barrier diode (SBD) to the PSA process, a low-power Schottky-diode-transistor-logic (SDTL) gate with i.6ns delay time, 0.8 pJ power-delay product and 2(X)0"am~ gate area has been successfully developed. Quantitative comparison of electronic component/solder joint stress relief in encapsulated assemblies D. A. CUMMINGS I E E E Trans. Components, tlybrids Mfg Technology. CHMT-2 (4), 454 (December 1979). A qualitative comparison was made of various stress relief bends with and without sleeving in three commonly used eocapsulants. Silicone rubber and heat shrinkable polyolifin sleeving were used on right angle, full loop, and hump style lead bends. Small (from 254 ,am to 762 ,am diameter) and large (762 p.m to 1.27mm diameter) wires were used to simulate small and large component leads. The component leads were encapsulated in mieroballoon-filled epoxy, 128kg/m:~ urethane foam, and 320 kg/m a urethane foam. Ten test samples were fabricated in each configuration; five were used for tensile loading, and five were used for compressive loading. A new air film technique for low contact handling of silicon wafers J. A. PAIVANAS andJ. K. ttASSAN Solid-St. Technol. 148 (April 1980). To reduce contact damage, contamination, and consequent lowering of product yield, wafers in automated semiconductor fabrication facilities are often extensively handled in the industry by equipment employing levitating and motion-producing air films. While considerable advantage is realised, the overall effectiveness of such equipment is nevertheless compromised by inherent wafer motion instabilities on the lubricating air film, coupled with the need for executing difficult motion control requirements. Consequently, some extent of solid contact, and hence the possibility of damage and contamination, is typically involved during such wafer motion. The need for solid contact control is greatly reduced, compared with other techniques, by the new IBM air film system described here. Its operation is based on a unique combination of two fluid mechanics phenomena to provide a supporting air film that simultaneously imparts and controls wafer motion. Wafer transportation and positioning are thus achieved under extremely low contact and contaminating conditions, with the air film operating in conjunction with special control device techniques. Plasma deposited polycrystalline silicon films K. R. S A R M A Solid-St. Technol. 143 (April 1980). A n atmospheric pressure plasma deposition process for depositing polycrystalline silicon films is reviewed and its current status described. Thermodynamic and kinetic aspects of this deposition process employing SiHCI., and SiCh as silicon bearing gases are discussed. Effects of various parameters on the deposition process are presented. Comparisons are made between this plasma process and the conventional chemical vapour deposition process. Characteristics of the deposited polycrystalline silicon films are discussed. Charge injection from a surface depletion region the Al~O:~-silicon system J. KOLK and E. L. HEASELL Solid-St. Electron. 23,223 (1980). Electron injection from a surface depletion region, over the surface barrier at an Al:~O:~-silicon interface is studied. The current passing over the barrier is measured by observing the rate of flat-band voltage shift as charge is trapped in the oxide. The data obtained is compared with the predictions of present models for charge injection. It is found that the so-called "lucky-electron" model gives the most generally satisfactory agreement with the observations. 41