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Logical Operations
Topic 19
Logical Operations There are four basic logical operators, TRUE, NOT (or INVERT), AND and OR. The last three of these were described in Topic 18. The first operator, TRUE is illustrated by its truth table: Input A
Output Z
0 1
0 1
for the last three gates are simply the inverse of the outputs of the first three. The truth tables are shown with two inputs, but gates can have more than two inputs. The truth tables for these can be worked out from the table above. Example In the AND column there is only one way to get a 1 output. This is by having all inputs at 1. This rule applies to any AND gate. For example an 8-input AND gate must have all inputs at 1 to get a 1 output. Any other combination of inputs gives a 0 output.
The output equals the input. This is the symbol for a TRUE gate:
A
Z
FIGURE 19.1
There may seem little point in having a TRUE gate, but a TRUE gate that is also a buffer is useful at times. The input may require only a small current, but the output may be able to source or sink a larger current than a standard logic gate. A buffer can be used to drive an LED, a buzzer, or a similar output device. The actions of logical operators are shown in truth tables, in which A and B are inputs and Z is the output. Logic ‘true’ is represented by 1, and 0 represents ‘false’. In practical circuits logical operations are performed by gates. In positive logic circuits, we represent ‘true’ by a high voltage (fairly close to the positive supply voltage) and ‘false’ by a low voltage (close to zero volts). All the logic circuit descriptions in this book assume positive logic, which is the system most often used. The truth tables for AND, OR and some other commonly used gates are shown on the right side by side for comparison. Reading from left to right, the outputs are A AND B, A OR B, A EX-OR B, A NAND B, A NOR B and A EX-NOR B. The outputs Electronics: Circuits and Systems. r 2011 Owen Bishop. Published by Elsevier Ltd. All rights reserved.
BOOLEAN SYMBOLS The table also serves as a summary of the symbols used in Boolean algebra. Remember that the symbol for AND (G) may be omitted, so that AB means the same thing as A G B. The symbol for NOT or INVERT is a bar over the variable, so A means NOT-A. It makes a difference whether two variables share a bar or have separate bars. For example: A G B means A NAND B but A G B means NOT-A AND NOT-B. Write out the two truth tables to see the difference. Inputs
Output Z
B
A
AGB
A 1 B
A"B
AB
A1B
A"B
0 0 1 1
0 1 0 1
0 0 0 1
0 1 1 1
0 1 1 0
1 1 1 0
1 0 0 0
1 0 0 1
PREDICTING OUTPUT Truth tables are an effective way of predicting the output from a circuit made up of gates. Usually we 157
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need to try all possible combinations of inputs and work out the output for each combination. If there are two inputs there are four combinations, as listed in the preceding table. If there are 3 inputs there are 8 combinations. If there are 4 inputs there are 16 combinations. With even more inputs the number of combinations becomes too large to handle easily and it is simpler to use logic simulator software on a computer. Sometimes there are combinations of inputs that we know in advance can not occur. These can be ignored when working out the outputs.
The next four columns show what each gate does for each combination of inputs. The output of Gate 1 is the inverse of the A column. The output of Gate 2 is obtained by ANDing the output of Gate 1 with the B column. The output of Gate 3 is the OR of B and C. Finally, the output of Gate 4 is the NAND of the outputs of Gates 2 and 3. Self Test In the circuit shown in Figure 19.2, find the outputs of Gate 4 for all possible combinations of inputs if: (a) gates 2 and 3 are both NOR gates. (b) gates 2 and 4 are both OR gates.
Example Predict the outputs of this circuit for each possible combination of inputs: A
A
1
AB
2
4 B
Z AB(B + C)
3
C
Summing up, the last column shows the output of the circuit for all possible combinations of inputs. A second way of solving this problem is to use the logical identities. Most of these are obvious but three in particular are important in circuit design. G
The redundancy theorem:
B+C
FIGURE 19.2 This logic circuit is analysed by several different techniques in this topic.
Circuits
A 1 AB 5 A G
The race hazard theorem: CA 1 CB 5 CA 1 CB 1 AB
G
Inputs
De Morgan’s Theorem, which has two forms:
Outputs
A1B 5AB
C
B
A
Gate 1 A
Gate 2 AB
Gate 3 B 1 C
Gate 4 Z
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 0
0 0 1 0 0 0 1 0
0 0 1 1 1 1 1 1
1 1 0 1 1 1 0 1
First work from left to right, entering the logical expressions at the output of each gate, as has already been done in the diagram. The output of gate 1 (NOT) is the invert of A. The inputs of gate 2 (an AND gate) are A and B, so the output is A B. The output of gate 3 (an OR gate) is B 1 C. The inputs to gate 4 are A B and B 1 C so its output is their NAND. Now follow this through in a truth table (above), for all eight possible combinations of A, B, and C. You can get all the combinations simply by writing out the eight 3-digit binary numbers from 0 to 7 in the first 3 columns.
AB 5 A 1 B
These may be proved by writing out their truth tables. Example Prove the redundancy theorem. Inputs B
A
AB
A 1 AB
0 0 1 1
0 1 0 1
0 0 0 1
0 1 0 1
Fill in columns B and A in the usual way. In the third column write A AND B. Then, in the fourth column, OR the third column with column A. It can then be seen that the second and fourth columns are identical. Therefore: A 1 AB 5 A
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Logical Operations
The result of this simplification shows that the output of the circuit does not depend on the value of C. This means that this 4-gate circuit can be replaced by two gates, as in the diagram below.
Example Prove the first identity of de Morgan’s Theorem. Inputs B
A
A1B
A1B
A
B
AB
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 0 0 0
The truth table lists all four input combinations and the various logical operations. The contents of the fourth and seventh columns are identical, so proving the theorem.
A B
A+B
Z
B
C FIGURE 19.3 The circuit in Figure 19.2 can be replaced by this 2gate version.
Self Test Use the truth table technique to prove the Race Hazard Theorem and the second identity of De Morgan’s Theorem.
4-INPUT CIRCUIT The circuit shown in Figure 19.4 has four inputs, so there are 16 possible combinations of input states. The expression for Z is:
Identities are used to find the outputs of logic circuits. Example Find the output of the circuit shown in Figure 19.2 by labelling the output of each gate with the logical result of its action. Work across the diagram from the inputs to the output. This gives the logical expression for the output shown on the extreme right of the figure. Next, simplify this, using De Morgan’s Theorem and other logical identities: A B ðB 1 C Þ 5 A B 1 B 1 C 5A1B1BC 5A1B1BC 5 A 1 ðB 1 B C Þ 5A1B
Line 1 recognises the expression as two parts that are NANDed together and converts them (using De Morgan) into two 2-term expressions inverted and ORed. Line 2 uses De Morgan again to split the first expression (NANDed) into two inverted ORed variables, and to split the second expression (NORed) into inverted ANDed variables. Line 3 simplifies NOT-NOT-A to A. Line 4 put brackets around an expression in B and C, which can then be simplified to B in line 5.
Self Test Check this simplification, using a truth table.
A1B 1BC 1C D
5 ðA 1 BÞ BC C D 5 ðA 1 BÞ ðB 1 C Þ C D 5 ðA 1 BÞ ðBC DÞ 1 ðC C DÞ 5 ðA 1 BÞ BC D 5 ABC D 1 BBC D 5 ABC D
There is only one combination for which the output is high. This is when A AND D are high, AND B AND C are low. The identities are used as follows. On line 1 we use De Morgan to replace a NOR expression with the inverts of its terms, ANDed together. The middle term, which is a NAND expression, is again replaced by an OR expression in line 2. On line 3 we replace (B1C) G CD with ðBCD 1 CCDÞ. Because C ANDed with its invert is 0, the second of these terms is eliminated on Line 4. Line 5 expands what is left into two terms, and this time we have B and its invert ANDed, so the second term is eliminated. This leaves only one term. This result can be confirmed by writing the truth table of 16 lines. Only one line contains ‘1’ in the output column. In this example it is seen that all four inputs need to be at the correct level to produce the required output. This suggests that there may be no way in which the number of gates may be reduced. However, it is not easy to be sure of this.
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PART | 1
A
Circuits
A+B
B BC
Z A+B+BC+CD
C C CD D
FIGURE 19.4 We use identities to determine what combination or combinations of inputs makes Z go high.
KARNAUGH MAPS
DESIGNING CIRCUITS
A Karnaugh map has the advantage that it tells us if it is possible to simplify the logic circuit and, if so, how to do it.
Karnaugh maps may be used for designing logic circuits to a given specification.
Example
Example
Use a Karnaugh map to simplify the logic circuit in Figure 19.2. Taking the output column of the truth table shown directly below Figure 19.2, we enter these results into a three-variable Karnaugh map. This has two variables (AB) on one edge and variable C on the other edge (see over). This gives 8 cells in the map, each corresponding to one of the rows in the truth table. Note that the columns and rows are headed in such a way that only one bit in the expression changes as we go from one column to the next. The next stage is to encircle groups of 2, 4 or 8 ‘1’s. In this example, it is possible to encircle two overlapping groups of four 1’s as shown in the map below.
A company car park includes two covered bays, one suitable only for a small car. The bays are out of view of the main car park entrance, so it is decided to install an illuminated sign to indicate when there is a vacancy in the covered bays. The system has a sensor in each bay to detect if it is occupied. At the entrace to the park there is a sensor to detect whether a car is large or small. There is also a radio sensor to detect a priority car.
Thus the system has four inputs: G
BA C 0
00
01
11
10
1
1
1
0
G
G G
1
1
B
1
1
0
A
FIGURE 19.5 The Karnaugh map of the logic of the circuit in Figure 17.6 shows us how to perform the same logic with fewer gates. There are two groups of four ‘1’s, representing A51 and B50 (or B51). The output is 1 when A51 OR when B51. In symbols, Z5A1B.
The groups are A and B, so the circuit simplifies to A OR B. The Karnaugh map shows that the circuit has the same action as the 2-gate circuit in Figure 19.3. It does not have a C input, as the state of C makes no difference to the output.
A is the sensor in Bay 1, the bay for both large and small cars. A 5 1 when the bay is occupied. B is the sensor in Bay 2, the bay for small cars. B 5 1 when the bay is occupied. C is the car size sensor: C 5 1 for large cars. D is the priority car sensor. D 5 1 for priority cars.
Sensors A and B are in the bays. Sensors C and D are at the entrance to the park. Also at the entrance is the illuminated sign Z which says ‘Vacancy’. This is the sole output of the system. It is assumed that a car offered a vacancy will take it (if this is not assumed we need duplicate sensors C and D in the bays, which needs six sensors and makes the logic far more complicated!). The rules of the system are that there is a vacancy if both bays are empty. Small cars can park in either bay, but large cars can park only in Bay 1. One of the bays must be kept vacant in case a priority car needs to park there. This means that only one bay may be occupied by a non-priority car. The first step in solving problems of this kind is to set out a truth table (see next page). The sign is
Topic | 19
161
Logical Operations
illuminated when Z51. This indicates that there are seven combinations of inputs in which a vacancy occurs. At this stage the way to build the logic circuit may be obvious, and there is no need for a Karnaugh map. However, the logic is not obvious in this example. so we proceed to the map (see right). This problem needs a 16-cell map, so there are columns for A and B, and rows for C and D. The seven 1’s of the output column of the truth table are carried down to the corresponding cells of the map. We then look for groups of 1’s, preferring large groups to small groups as they make the logic simpler. There are no groups of 8, but two groups of 4. Note that groups may overlap and also that groups may wrap round from one side of the map to the opposite side (example, the group AD) or from top to bottom. Inputs
Output
D
C
B
A
Z
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 0 0 0 1 0 0 0 1 1 1 0 1 0 1 0
BA
00
01
11
10
00
1
0
0
0
01
1
0
0
0
11
1
0
0
1
10
1
1
0
1
DC
AB B CD
AD
FIGURE 19.6 The logic of the car park system. The Karnaugh map with corresponding truth table (see left).
It may be possible to reduce the number of gates, as was done for the circuit in Figure 19.3. Sometimes a Karnaugh map shows how to reduce the gate count, but in this case it does not. Instead we can try to simplify the expression by using identities. This simplification is left to the student as an exercise. The gate count can be reduced to 5, possibly to fewer.
BREADBOARDS AND SIMULATORS A fourth way to solve a circuit is to connect IC gates together on a breadboard, run through all possible input states, as listed in the truth table, and see what output is produced at each stage. You can do the equivalent thing by setting up the circuit on a simulator. Example
There is a third goup consisting of a pair of 1’s. The output Z is high, and the ‘Vacancy’ sign is switched on whenever the combination of inputs corresponds to one of the cells in the groups. Any one OR other of the groups will do, so the logical equation is: Z 5A B1B C D1A D
This result can be confirmed by evaluating the expression using a truth table. The result should be identical with the values shown in column Z of the original table. The equation shows that 7 gates are needed to build the system. It needs 3 NOT gates to invert inputs A, B, and C. It needs 3 AND gates (one of them with 3 inputs), and it needs a 3-input OR gate to produce the value of the whole expression.
The screen display shown in Figure 19.7 is the result of a simulation of the circuit of Figure 19.2, using 74LS series devices. To provide the input we used a 5 MHz clock and fed its signal to a 3-stage binary counter (more about these in Topic 22). The clock and counter are seen on the left of the screen. Times are in nanoseconds, the count incrementing every 200 ns. The vertical dashed lines on the output display represent 200 ns intervals. The inputs (plots A, B and C) begin at the count of 000 and the trace runs while they increase to 111 and return to 000 again. The count then runs through 000 to 100 at the extreme right side of the screen. The output from the NAND gate is plotted as ‘Out’ on the display. This is Z and equals 1 except when A is low and B is high (A 5 0 and B 5 1). The state of C has no effect on output. This result agrees with the truth table for Figure 19.2.
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PART | 1
Circuits
FIGURE 19.7 A run on a simulator confirms that the truth table for Figure 19.2 is correct. The display shows logic circuits (left) that produce the eight different combinations of inputs to the four logic gates (centre). The graphs show the sequence of logical input and output levels.
The trace for output Z shows an unexpected effect. There is a glitch in the output, shown as a brief low pulse occurring as input changes from 011 to 100. The reason for this is discussed in Topic 22. It is not a fault in the logic of the circuit.
WORKING WITH NAND AND NOR Usually we are given a circuit or a truth table and we design a circuit to perform the logic with the minimum of gates. The circuit in Figure 19.3 is an example of a minimised circuit. Although it requires the minimum of components, takes up the least possible board space and uses the minimum of power, it may not be ideal in practice. When a circuit is built from ICs there is the practical point that an IC usually contains several identical gates. A single IC may contain six NOT gates, or four 2-input gates performing the other basic logical operations. It is uneconomical of cost, board space and power to install a 6-gate or 4-gate IC on the circuit board if only one or two of its gates is going to be used. It is better to try to restrict the design to a few different types of gate and so reduce the number of ICs required. This circuit requires only two gates, NOT and AND but unfortunately they are of different kinds. To set up this circuit on its own requires two ICs
containing 10 gates, of which we use only 2. If this circuit is part of a larger logic system, we may find that the system does not need any other AND gates. Or, if it does need a few AND gates, they are situated a long way from the NOT gates. This means having long tracks wandering all over the board. Tracks take up space and, if they are long, may delay the signal sufficiently to cause the logic to fail. The more long tracks there are, the more difficult it becomes to design the board, and the more we need to resort to wire links and vias to make the connections. Via On a printed circuit board a via is a connection (usually a double-headed pin soldered at both ends) that goes through the board, linking a track on one side of the board to another track on the other side.
Circuit board design can be simplified by keeping to two or three types of gate. Better still, use only one type. All logic functions can be obtained with NOT, AND and OR, but these are not the most useful gates in practice. NAND and NOR gates too can be used to perform all the basic logic functions and are also useful in building flip-flops, latches and other more complicated logical circuits. For this reason, we generally prefer to work only with NAND and NOR
Topic | 19
163
Logical Operations
gates. There are some circuits, such as decoders, that need a lot of AND gates, which makes it worth while to use ICs of this type. Some kinds of circuit need a lot of NOT gates. But, on the whole, NAND and NOR gates are preferred.
A
B
B (a)
A
The first step in converting the circuit of Figure 19.3 to NAND and NOR is to note that the second half of the truth table repeats the first half, so it is unnecessary to take C into account. This leaves two inputs, A and B, so there are four possible combinations of input state. Now work backwards from the output. The outputs for the four combinations comprise one 0 and three 1’s. The truth tables on the first page of this topic show that this mix of outputs is a feature of NAND gates. Therefore the output gate of the converted circuit must be NAND. Compare the normal output of NAND with the output of the circuit in Figure 19.3:
B
Outputs
A+B
A.B
B
Example
Inputs
A
A
A
A A+B
A.B B
B
(b)
FIGURE 19.9 Replacing (a) OR with NAND, and (b) AND with NOR, after inverting the inputs.
Topic 20). But often we need such a gate only once or twice in a circuit and it is better then to build it from other basic gates. The Karnaugh map technique is no help as there are no entries from the truth tables that can be grouped together. The expression for exclusive-OR from the truth table itself is:
B
A
NAND
Circuit
A"B 5 AB 1 AB
0 0 1 1
0 1 0 1
1 1 1 0
1 1 0 1
This can be translated directly into gates, using three of the basic types, NOT, AND and OR: A
A.B
B
Inverting A in the bottom two lines makes the NAND output agree with the required output. Inverting A in the top two lines makes no difference as both lines have output 1. So the solution is to invert A before feeding it to the NAND gate. We can use a NOT gate if there is one to spare. Otherwise, build the circuit from two NAND gates, as below:
A
A Z AB
B FIGURE 19.8 It is often useful to be able to work only with NAND gates. This is the NAND gate equivalent of the circuit in Figure 19.2 and its simplified version in Figure 19.3.
We can also use De Morgan’s Theorem to help design a circuit in NAND or NOR gates. Figure 19.9 shows equivalent circuits. Exclusive-OR and exclusive-NOR ICs are available, usually four gates to a package, and sometimes a circuit needs several such ICs (see the parity tree in
A.B +A.B
A
A
AB
FIGURE 19.10 An exclusive-OR gate that is built from NOT, OR and AND gates, requires three different ICs.
In practice we might not find all three types already available as spare gates, and they might be too far apart on the circuit board to make it convenient to connect them. An alternative exclusive-OR circuit circuit can be built entirely from NAND gates: A
A(AB)
AB
Z A(A.B).B(A.B)
B
B(AB)
FIGURE 19.11 This version of the exclusive-OR gate uses only NAND gates to build it. It is assembled from a single IC.
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When trying to solve any particular logical problem, it is useful to adopt more than one of the four possible approaches. The results from one approach act as a check on those produced in another way. So, to confirm the all-NAND version of the exclusive-OR gate we will try to arrive at the same result by using logical equations. As usual, De Morgan’s identities are important in the proof. We begin with the equation quoted earlier: A"B 5 AB 1 AB
The proof continues by including two expressions that are certain to be false, for they state that A AND NOT-A is true, and also that B AND NOT-B is true. Their value is zero so they do not affect the equality. Next, common factors are taken to the outside of brackets. The final two lines rely on De Morgan: 5A B1A B1A A1B B 5 AðA 1 BÞ 1 BðA 1 BÞ 5 AðABÞ 1 BðABÞ 5 AðABÞ:BðABÞ
The array of bars over the final expression is complicated but, if you work carefully from the bottom layer of bars upward, you will see that this expression is made up entirely of NAND operations and is the exact equivalent of the circuit in Figure 19.11.
Circuits
breadboard. The pin may not be making contact but you will not be able to see that there is anything wrong. CMOS ICs need careful handling to avoid damage by static charges. Keep them with their pins embedded in conductive plastic foam until you are ready to use them. It is good practice to remove charges from your body from time to time by touching a finger against an earthed point, such as a cold water tap. Follow any other static charge precautions adopted in your laboratory. Apply 1 or 0 inputs by connecting the appropriate pins to the positive or 0V supply lines. Preferably use push-buttons with pull-down resistors.
ACTIVITY — USING A SIMULATOR Simulation software (see earlier section ‘Breadboards and simulators’) can be used for finding the answers to questions on logical operations. They can also be used to check the answers to questions that you have solved by other methods, such as truth tables, identities and Karnaugh maps. For example, the question might be: Investigate the action of the circuit shown in Figure 19.12. Write its truth table and describe the simplest equivalent circuit. A
ACTIVITY — LOGICAL OPERATIONS Any of the logical circuits in this topic may be set up on a breadboard for testing. You need: G G
A breadboard. A supply of short lengths of single-core wire with insulation stripped from both ends.
B
Z
C FIGURE 19.12 The circuit to be investigated.
A power supply, 5 V regulated DC for 74LS series ICs, or any DC voltage between 3 V and 15 V for CMOS. Any DC voltage between 2 V and 6 V for 74HC series. G G G
Integrated circuits to provide the gates. Manual to show the pin connections of the ICs. Output indicator, either a testmeter or a logic probe. You can also use an LED in series with a resistor to limit the current to a few milliamperes.
Complete the wiring and check it before applying power. With CMOS, all unused inputs must be connected to something before switching on, usually either to the positive or to the 0 V supply line. Unused outputs are left unconnected. Take care to avoid pins becoming bent beneath the IC when inserting the ICs into the sockets in the
FIGURE 19.13 The same circuit set up on a simulator. The user sets each of the three inputs on the left to ‘0’ or ‘1’. The simulator displays the output on the right.
Ater running through all eight possible combinations of the three inputs and recording the output for each combination, the value of Z is found to be ‘1’ for all combinations except for A G B G C, when it is ‘0’.
Topic | 19
165
Logical Operations
This pattern of outputs (all ‘1’ except for one ‘0’) is typical of a NAND gate (see table, p. 157). Therefore the circuit is equivalent to a 3-input NAND gate with input A inverted. Draw some circuits based on 3 or 4 logic gates, each with 2 or 3 inputs (exclusive-OR and exclusiveNOR gates can have only two inputs). Use a simulator to investigate their action. Try to simplify the circuit and use a simulator to confirm your answer. Use a simulator to solve some of the questions following.
QUESTIONS ON LOGICAL OPERATIONS 1 Simplify this expression and write its truth table: AB1AB To what logical operation is it equivalent? 2 Draw a circuit diagram to represent this: Z 5ABC1ABC1ABC1ABC Use a breadboard or simulator to investigate its logic. 3 Write the truth table for the circuit below. To what gate is it equivalent? A B Z
FIGURE 19.14
4 Obtain the logical equations from the Karnaugh maps below. Draw the logic circuit for each equation. B.A
00
01
11
10
0
1
1
0
0
1
0
1
1
0
C
B.A
00
01
11
10
0
1
0
0
1
1
1
0
1
1
C
(a) B.A
(b)
00
01
11
10
00
0
0
1
1
01
0
1
0
11
0
1
10
0
0
D.C
(c) FIGURE 19.15
B.A
5 Convert the circuits of Question 4 into an all-NAND or all-NOR form. 6 Simplify the following expressions and draw their equivalent circuits: (a) (b) (c) (d) (e) (f)
Z 5 ðAB 1 BC 1 ABCÞ C Z 5 ðA 1 BÞ ðA 1 C Þ Z 5A11A11B0 Z 5 A B C 1 AB C Z 5 AB 1 AB 1 AB Z 5 ABCD 1 ABCD 1 A BCD
MULTIPLE CHOICE QUESTIONS 1 In this list, the operator that is not a basic logical operator is: A AND B OR C NAND D NOT. 2 The operator represented by the " symbol is: A NAND B NOT C NOR D Exclusive-OR. 3 The output of a 3-input NAND gate is low when: A all inputs are low B one input is high C more than one input is low D all inputs are high. 4 The number of input combinations which can make the output of a 4-input OR gate go low is: A 8 B 16 C 15 D 1. 5 The output of an Ex-OR gate is ‘0’ when: A A is ‘0’. B A is ‘1’ and B is ‘0’. C A and B are the same. D A and B are different. 6 The combination of inputs that produces a low output from the system below is: A All low B A high, B and C low C A and B high, C low D All high.
00
01
11
10
00
1
0
0
1
1
01
0
0
0
1
1
0
11
0
1
0
0
A
0
0
10
1
0
0
1
B
D.C
(d)
C FIGURE 19.16
Z
Logical Operations There are four basic logical operators, TRUE, NOT (or INVERT), AND and OR. The last three of these were described in Topic 18. The first operator, TRUE is illustrated by its truth table: Input A
Output Z
0 1
0 1
for the last three gates are simply the inverse of the outputs of the first three. The truth tables are shown with two inputs, but gates can have more than two inputs. The truth tables for these can be worked out from the table above. Example In the AND column there is only one way to get a 1 output. This is by having all inputs at 1. This rule applies to any AND gate. For example an 8-input AND gate must have all inputs at 1 to get a 1 output. Any other combination of inputs gives a 0 output.
The output equals the input. This is the symbol for a TRUE gate:
A
Z
FIGURE 19.1
There may seem little point in having a TRUE gate, but a TRUE gate that is also a buffer is useful at times. The input may require only a small current, but the output may be able to source or sink a larger current than a standard logic gate. A buffer can be used to drive an LED, a buzzer, or a similar output device. The actions of logical operators are shown in truth tables, in which A and B are inputs and Z is the output. Logic ‘true’ is represented by 1, and 0 represents ‘false’. In practical circuits logical operations are performed by gates. In positive logic circuits, we represent ‘true’ by a high voltage (fairly close to the positive supply voltage) and ‘false’ by a low voltage (close to zero volts). All the logic circuit descriptions in this book assume positive logic, which is the system most often used. The truth tables for AND, OR and some other commonly used gates are shown on the right side by side for comparison. Reading from left to right, the outputs are A AND B, A OR B, A EX-OR B, A NAND B, A NOR B and A EX-NOR B. The outputs Electronics: Circuits and Systems. r 2011 Owen Bishop. Published by Elsevier Ltd. All rights reserved.
BOOLEAN SYMBOLS The table also serves as a summary of the symbols used in Boolean algebra. Remember that the symbol for AND (G) may be omitted, so that AB means the same thing as A G B. The symbol for NOT or INVERT is a bar over the variable, so A means NOT-A. It makes a difference whether two variables share a bar or have separate bars. For example: A G B means A NAND B but A G B means NOT-A AND NOT-B. Write out the two truth tables to see the difference. Inputs
Output Z
B
A
AGB
A 1 B
A"B
AB
A1B
A"B
0 0 1 1
0 1 0 1
0 0 0 1
0 1 1 1
0 1 1 0
1 1 1 0
1 0 0 0
1 0 0 1
PREDICTING OUTPUT Truth tables are an effective way of predicting the output from a circuit made up of gates. Usually we 157
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PART | 1
need to try all possible combinations of inputs and work out the output for each combination. If there are two inputs there are four combinations, as listed in the preceding table. If there are 3 inputs there are 8 combinations. If there are 4 inputs there are 16 combinations. With even more inputs the number of combinations becomes too large to handle easily and it is simpler to use logic simulator software on a computer. Sometimes there are combinations of inputs that we know in advance can not occur. These can be ignored when working out the outputs.
The next four columns show what each gate does for each combination of inputs. The output of Gate 1 is the inverse of the A column. The output of Gate 2 is obtained by ANDing the output of Gate 1 with the B column. The output of Gate 3 is the OR of B and C. Finally, the output of Gate 4 is the NAND of the outputs of Gates 2 and 3. Self Test In the circuit shown in Figure 19.2, find the outputs of Gate 4 for all possible combinations of inputs if: (a) gates 2 and 3 are both NOR gates. (b) gates 2 and 4 are both OR gates.
Example Predict the outputs of this circuit for each possible combination of inputs: A
A
1
AB
2
4 B
Z AB(B + C)
3
C
Summing up, the last column shows the output of the circuit for all possible combinations of inputs. A second way of solving this problem is to use the logical identities. Most of these are obvious but three in particular are important in circuit design. G
The redundancy theorem:
B+C
FIGURE 19.2 This logic circuit is analysed by several different techniques in this topic.
Circuits
A 1 AB 5 A G
The race hazard theorem: CA 1 CB 5 CA 1 CB 1 AB
G
Inputs
De Morgan’s Theorem, which has two forms:
Outputs
A1B 5AB
C
B
A
Gate 1 A
Gate 2 AB
Gate 3 B 1 C
Gate 4 Z
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 0
0 0 1 0 0 0 1 0
0 0 1 1 1 1 1 1
1 1 0 1 1 1 0 1
First work from left to right, entering the logical expressions at the output of each gate, as has already been done in the diagram. The output of gate 1 (NOT) is the invert of A. The inputs of gate 2 (an AND gate) are A and B, so the output is A B. The output of gate 3 (an OR gate) is B 1 C. The inputs to gate 4 are A B and B 1 C so its output is their NAND. Now follow this through in a truth table (above), for all eight possible combinations of A, B, and C. You can get all the combinations simply by writing out the eight 3-digit binary numbers from 0 to 7 in the first 3 columns.
AB 5 A 1 B
These may be proved by writing out their truth tables. Example Prove the redundancy theorem. Inputs B
A
AB
A 1 AB
0 0 1 1
0 1 0 1
0 0 0 1
0 1 0 1
Fill in columns B and A in the usual way. In the third column write A AND B. Then, in the fourth column, OR the third column with column A. It can then be seen that the second and fourth columns are identical. Therefore: A 1 AB 5 A
Topic | 19
159
Logical Operations
The result of this simplification shows that the output of the circuit does not depend on the value of C. This means that this 4-gate circuit can be replaced by two gates, as in the diagram below.
Example Prove the first identity of de Morgan’s Theorem. Inputs B
A
A1B
A1B
A
B
AB
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 0 0 0
The truth table lists all four input combinations and the various logical operations. The contents of the fourth and seventh columns are identical, so proving the theorem.
A B
A+B
Z
B
C FIGURE 19.3 The circuit in Figure 19.2 can be replaced by this 2gate version.
Self Test Use the truth table technique to prove the Race Hazard Theorem and the second identity of De Morgan’s Theorem.
4-INPUT CIRCUIT The circuit shown in Figure 19.4 has four inputs, so there are 16 possible combinations of input states. The expression for Z is:
Identities are used to find the outputs of logic circuits. Example Find the output of the circuit shown in Figure 19.2 by labelling the output of each gate with the logical result of its action. Work across the diagram from the inputs to the output. This gives the logical expression for the output shown on the extreme right of the figure. Next, simplify this, using De Morgan’s Theorem and other logical identities: A B ðB 1 C Þ 5 A B 1 B 1 C 5A1B1BC 5A1B1BC 5 A 1 ðB 1 B C Þ 5A1B
Line 1 recognises the expression as two parts that are NANDed together and converts them (using De Morgan) into two 2-term expressions inverted and ORed. Line 2 uses De Morgan again to split the first expression (NANDed) into two inverted ORed variables, and to split the second expression (NORed) into inverted ANDed variables. Line 3 simplifies NOT-NOT-A to A. Line 4 put brackets around an expression in B and C, which can then be simplified to B in line 5.
Self Test Check this simplification, using a truth table.
A1B 1BC 1C D
5 ðA 1 BÞ BC C D 5 ðA 1 BÞ ðB 1 C Þ C D 5 ðA 1 BÞ ðBC DÞ 1 ðC C DÞ 5 ðA 1 BÞ BC D 5 ABC D 1 BBC D 5 ABC D
There is only one combination for which the output is high. This is when A AND D are high, AND B AND C are low. The identities are used as follows. On line 1 we use De Morgan to replace a NOR expression with the inverts of its terms, ANDed together. The middle term, which is a NAND expression, is again replaced by an OR expression in line 2. On line 3 we replace (B1C) G CD with ðBCD 1 CCDÞ. Because C ANDed with its invert is 0, the second of these terms is eliminated on Line 4. Line 5 expands what is left into two terms, and this time we have B and its invert ANDed, so the second term is eliminated. This leaves only one term. This result can be confirmed by writing the truth table of 16 lines. Only one line contains ‘1’ in the output column. In this example it is seen that all four inputs need to be at the correct level to produce the required output. This suggests that there may be no way in which the number of gates may be reduced. However, it is not easy to be sure of this.
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PART | 1
A
Circuits
A+B
B BC
Z A+B+BC+CD
C C CD D
FIGURE 19.4 We use identities to determine what combination or combinations of inputs makes Z go high.
KARNAUGH MAPS
DESIGNING CIRCUITS
A Karnaugh map has the advantage that it tells us if it is possible to simplify the logic circuit and, if so, how to do it.
Karnaugh maps may be used for designing logic circuits to a given specification.
Example
Example
Use a Karnaugh map to simplify the logic circuit in Figure 19.2. Taking the output column of the truth table shown directly below Figure 19.2, we enter these results into a three-variable Karnaugh map. This has two variables (AB) on one edge and variable C on the other edge (see over). This gives 8 cells in the map, each corresponding to one of the rows in the truth table. Note that the columns and rows are headed in such a way that only one bit in the expression changes as we go from one column to the next. The next stage is to encircle groups of 2, 4 or 8 ‘1’s. In this example, it is possible to encircle two overlapping groups of four 1’s as shown in the map below.
A company car park includes two covered bays, one suitable only for a small car. The bays are out of view of the main car park entrance, so it is decided to install an illuminated sign to indicate when there is a vacancy in the covered bays. The system has a sensor in each bay to detect if it is occupied. At the entrace to the park there is a sensor to detect whether a car is large or small. There is also a radio sensor to detect a priority car.
Thus the system has four inputs: G
BA C 0
00
01
11
10
1
1
1
0
G
G G
1
1
B
1
1
0
A
FIGURE 19.5 The Karnaugh map of the logic of the circuit in Figure 17.6 shows us how to perform the same logic with fewer gates. There are two groups of four ‘1’s, representing A51 and B50 (or B51). The output is 1 when A51 OR when B51. In symbols, Z5A1B.
The groups are A and B, so the circuit simplifies to A OR B. The Karnaugh map shows that the circuit has the same action as the 2-gate circuit in Figure 19.3. It does not have a C input, as the state of C makes no difference to the output.
A is the sensor in Bay 1, the bay for both large and small cars. A 5 1 when the bay is occupied. B is the sensor in Bay 2, the bay for small cars. B 5 1 when the bay is occupied. C is the car size sensor: C 5 1 for large cars. D is the priority car sensor. D 5 1 for priority cars.
Sensors A and B are in the bays. Sensors C and D are at the entrance to the park. Also at the entrance is the illuminated sign Z which says ‘Vacancy’. This is the sole output of the system. It is assumed that a car offered a vacancy will take it (if this is not assumed we need duplicate sensors C and D in the bays, which needs six sensors and makes the logic far more complicated!). The rules of the system are that there is a vacancy if both bays are empty. Small cars can park in either bay, but large cars can park only in Bay 1. One of the bays must be kept vacant in case a priority car needs to park there. This means that only one bay may be occupied by a non-priority car. The first step in solving problems of this kind is to set out a truth table (see next page). The sign is
Topic | 19
161
Logical Operations
illuminated when Z51. This indicates that there are seven combinations of inputs in which a vacancy occurs. At this stage the way to build the logic circuit may be obvious, and there is no need for a Karnaugh map. However, the logic is not obvious in this example. so we proceed to the map (see right). This problem needs a 16-cell map, so there are columns for A and B, and rows for C and D. The seven 1’s of the output column of the truth table are carried down to the corresponding cells of the map. We then look for groups of 1’s, preferring large groups to small groups as they make the logic simpler. There are no groups of 8, but two groups of 4. Note that groups may overlap and also that groups may wrap round from one side of the map to the opposite side (example, the group AD) or from top to bottom. Inputs
Output
D
C
B
A
Z
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 0 0 0 1 0 0 0 1 1 1 0 1 0 1 0
BA
00
01
11
10
00
1
0
0
0
01
1
0
0
0
11
1
0
0
1
10
1
1
0
1
DC
AB B CD
AD
FIGURE 19.6 The logic of the car park system. The Karnaugh map with corresponding truth table (see left).
It may be possible to reduce the number of gates, as was done for the circuit in Figure 19.3. Sometimes a Karnaugh map shows how to reduce the gate count, but in this case it does not. Instead we can try to simplify the expression by using identities. This simplification is left to the student as an exercise. The gate count can be reduced to 5, possibly to fewer.
BREADBOARDS AND SIMULATORS A fourth way to solve a circuit is to connect IC gates together on a breadboard, run through all possible input states, as listed in the truth table, and see what output is produced at each stage. You can do the equivalent thing by setting up the circuit on a simulator. Example
There is a third goup consisting of a pair of 1’s. The output Z is high, and the ‘Vacancy’ sign is switched on whenever the combination of inputs corresponds to one of the cells in the groups. Any one OR other of the groups will do, so the logical equation is: Z 5A B1B C D1A D
This result can be confirmed by evaluating the expression using a truth table. The result should be identical with the values shown in column Z of the original table. The equation shows that 7 gates are needed to build the system. It needs 3 NOT gates to invert inputs A, B, and C. It needs 3 AND gates (one of them with 3 inputs), and it needs a 3-input OR gate to produce the value of the whole expression.
The screen display shown in Figure 19.7 is the result of a simulation of the circuit of Figure 19.2, using 74LS series devices. To provide the input we used a 5 MHz clock and fed its signal to a 3-stage binary counter (more about these in Topic 22). The clock and counter are seen on the left of the screen. Times are in nanoseconds, the count incrementing every 200 ns. The vertical dashed lines on the output display represent 200 ns intervals. The inputs (plots A, B and C) begin at the count of 000 and the trace runs while they increase to 111 and return to 000 again. The count then runs through 000 to 100 at the extreme right side of the screen. The output from the NAND gate is plotted as ‘Out’ on the display. This is Z and equals 1 except when A is low and B is high (A 5 0 and B 5 1). The state of C has no effect on output. This result agrees with the truth table for Figure 19.2.
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PART | 1
Circuits
FIGURE 19.7 A run on a simulator confirms that the truth table for Figure 19.2 is correct. The display shows logic circuits (left) that produce the eight different combinations of inputs to the four logic gates (centre). The graphs show the sequence of logical input and output levels.
The trace for output Z shows an unexpected effect. There is a glitch in the output, shown as a brief low pulse occurring as input changes from 011 to 100. The reason for this is discussed in Topic 22. It is not a fault in the logic of the circuit.
WORKING WITH NAND AND NOR Usually we are given a circuit or a truth table and we design a circuit to perform the logic with the minimum of gates. The circuit in Figure 19.3 is an example of a minimised circuit. Although it requires the minimum of components, takes up the least possible board space and uses the minimum of power, it may not be ideal in practice. When a circuit is built from ICs there is the practical point that an IC usually contains several identical gates. A single IC may contain six NOT gates, or four 2-input gates performing the other basic logical operations. It is uneconomical of cost, board space and power to install a 6-gate or 4-gate IC on the circuit board if only one or two of its gates is going to be used. It is better to try to restrict the design to a few different types of gate and so reduce the number of ICs required. This circuit requires only two gates, NOT and AND but unfortunately they are of different kinds. To set up this circuit on its own requires two ICs
containing 10 gates, of which we use only 2. If this circuit is part of a larger logic system, we may find that the system does not need any other AND gates. Or, if it does need a few AND gates, they are situated a long way from the NOT gates. This means having long tracks wandering all over the board. Tracks take up space and, if they are long, may delay the signal sufficiently to cause the logic to fail. The more long tracks there are, the more difficult it becomes to design the board, and the more we need to resort to wire links and vias to make the connections. Via On a printed circuit board a via is a connection (usually a double-headed pin soldered at both ends) that goes through the board, linking a track on one side of the board to another track on the other side.
Circuit board design can be simplified by keeping to two or three types of gate. Better still, use only one type. All logic functions can be obtained with NOT, AND and OR, but these are not the most useful gates in practice. NAND and NOR gates too can be used to perform all the basic logic functions and are also useful in building flip-flops, latches and other more complicated logical circuits. For this reason, we generally prefer to work only with NAND and NOR
Topic | 19
163
Logical Operations
gates. There are some circuits, such as decoders, that need a lot of AND gates, which makes it worth while to use ICs of this type. Some kinds of circuit need a lot of NOT gates. But, on the whole, NAND and NOR gates are preferred.
A
B
B (a)
A
The first step in converting the circuit of Figure 19.3 to NAND and NOR is to note that the second half of the truth table repeats the first half, so it is unnecessary to take C into account. This leaves two inputs, A and B, so there are four possible combinations of input state. Now work backwards from the output. The outputs for the four combinations comprise one 0 and three 1’s. The truth tables on the first page of this topic show that this mix of outputs is a feature of NAND gates. Therefore the output gate of the converted circuit must be NAND. Compare the normal output of NAND with the output of the circuit in Figure 19.3:
B
Outputs
A+B
A.B
B
Example
Inputs
A
A
A
A A+B
A.B B
B
(b)
FIGURE 19.9 Replacing (a) OR with NAND, and (b) AND with NOR, after inverting the inputs.
Topic 20). But often we need such a gate only once or twice in a circuit and it is better then to build it from other basic gates. The Karnaugh map technique is no help as there are no entries from the truth tables that can be grouped together. The expression for exclusive-OR from the truth table itself is:
B
A
NAND
Circuit
A"B 5 AB 1 AB
0 0 1 1
0 1 0 1
1 1 1 0
1 1 0 1
This can be translated directly into gates, using three of the basic types, NOT, AND and OR: A
A.B
B
Inverting A in the bottom two lines makes the NAND output agree with the required output. Inverting A in the top two lines makes no difference as both lines have output 1. So the solution is to invert A before feeding it to the NAND gate. We can use a NOT gate if there is one to spare. Otherwise, build the circuit from two NAND gates, as below:
A
A Z AB
B FIGURE 19.8 It is often useful to be able to work only with NAND gates. This is the NAND gate equivalent of the circuit in Figure 19.2 and its simplified version in Figure 19.3.
We can also use De Morgan’s Theorem to help design a circuit in NAND or NOR gates. Figure 19.9 shows equivalent circuits. Exclusive-OR and exclusive-NOR ICs are available, usually four gates to a package, and sometimes a circuit needs several such ICs (see the parity tree in
A.B +A.B
A
A
AB
FIGURE 19.10 An exclusive-OR gate that is built from NOT, OR and AND gates, requires three different ICs.
In practice we might not find all three types already available as spare gates, and they might be too far apart on the circuit board to make it convenient to connect them. An alternative exclusive-OR circuit circuit can be built entirely from NAND gates: A
A(AB)
AB
Z A(A.B).B(A.B)
B
B(AB)
FIGURE 19.11 This version of the exclusive-OR gate uses only NAND gates to build it. It is assembled from a single IC.
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PART | 1
When trying to solve any particular logical problem, it is useful to adopt more than one of the four possible approaches. The results from one approach act as a check on those produced in another way. So, to confirm the all-NAND version of the exclusive-OR gate we will try to arrive at the same result by using logical equations. As usual, De Morgan’s identities are important in the proof. We begin with the equation quoted earlier: A"B 5 AB 1 AB
The proof continues by including two expressions that are certain to be false, for they state that A AND NOT-A is true, and also that B AND NOT-B is true. Their value is zero so they do not affect the equality. Next, common factors are taken to the outside of brackets. The final two lines rely on De Morgan: 5A B1A B1A A1B B 5 AðA 1 BÞ 1 BðA 1 BÞ 5 AðABÞ 1 BðABÞ 5 AðABÞ:BðABÞ
The array of bars over the final expression is complicated but, if you work carefully from the bottom layer of bars upward, you will see that this expression is made up entirely of NAND operations and is the exact equivalent of the circuit in Figure 19.11.
Circuits
breadboard. The pin may not be making contact but you will not be able to see that there is anything wrong. CMOS ICs need careful handling to avoid damage by static charges. Keep them with their pins embedded in conductive plastic foam until you are ready to use them. It is good practice to remove charges from your body from time to time by touching a finger against an earthed point, such as a cold water tap. Follow any other static charge precautions adopted in your laboratory. Apply 1 or 0 inputs by connecting the appropriate pins to the positive or 0V supply lines. Preferably use push-buttons with pull-down resistors.
ACTIVITY — USING A SIMULATOR Simulation software (see earlier section ‘Breadboards and simulators’) can be used for finding the answers to questions on logical operations. They can also be used to check the answers to questions that you have solved by other methods, such as truth tables, identities and Karnaugh maps. For example, the question might be: Investigate the action of the circuit shown in Figure 19.12. Write its truth table and describe the simplest equivalent circuit. A
ACTIVITY — LOGICAL OPERATIONS Any of the logical circuits in this topic may be set up on a breadboard for testing. You need: G G
A breadboard. A supply of short lengths of single-core wire with insulation stripped from both ends.
B
Z
C FIGURE 19.12 The circuit to be investigated.
A power supply, 5 V regulated DC for 74LS series ICs, or any DC voltage between 3 V and 15 V for CMOS. Any DC voltage between 2 V and 6 V for 74HC series. G G G
Integrated circuits to provide the gates. Manual to show the pin connections of the ICs. Output indicator, either a testmeter or a logic probe. You can also use an LED in series with a resistor to limit the current to a few milliamperes.
Complete the wiring and check it before applying power. With CMOS, all unused inputs must be connected to something before switching on, usually either to the positive or to the 0 V supply line. Unused outputs are left unconnected. Take care to avoid pins becoming bent beneath the IC when inserting the ICs into the sockets in the
FIGURE 19.13 The same circuit set up on a simulator. The user sets each of the three inputs on the left to ‘0’ or ‘1’. The simulator displays the output on the right.
Ater running through all eight possible combinations of the three inputs and recording the output for each combination, the value of Z is found to be ‘1’ for all combinations except for A G B G C, when it is ‘0’.
Topic | 19
165
Logical Operations
This pattern of outputs (all ‘1’ except for one ‘0’) is typical of a NAND gate (see table, p. 157). Therefore the circuit is equivalent to a 3-input NAND gate with input A inverted. Draw some circuits based on 3 or 4 logic gates, each with 2 or 3 inputs (exclusive-OR and exclusiveNOR gates can have only two inputs). Use a simulator to investigate their action. Try to simplify the circuit and use a simulator to confirm your answer. Use a simulator to solve some of the questions following.
QUESTIONS ON LOGICAL OPERATIONS 1 Simplify this expression and write its truth table: AB1AB To what logical operation is it equivalent? 2 Draw a circuit diagram to represent this: Z 5ABC1ABC1ABC1ABC Use a breadboard or simulator to investigate its logic. 3 Write the truth table for the circuit below. To what gate is it equivalent? A B Z
FIGURE 19.14
4 Obtain the logical equations from the Karnaugh maps below. Draw the logic circuit for each equation. B.A
00
01
11
10
0
1
1
0
0
1
0
1
1
0
C
B.A
00
01
11
10
0
1
0
0
1
1
1
0
1
1
C
(a) B.A
(b)
00
01
11
10
00
0
0
1
1
01
0
1
0
11
0
1
10
0
0
D.C
(c) FIGURE 19.15
B.A
5 Convert the circuits of Question 4 into an all-NAND or all-NOR form. 6 Simplify the following expressions and draw their equivalent circuits: (a) (b) (c) (d) (e) (f)
Z 5 ðAB 1 BC 1 ABCÞ C Z 5 ðA 1 BÞ ðA 1 C Þ Z 5A11A11B0 Z 5 A B C 1 AB C Z 5 AB 1 AB 1 AB Z 5 ABCD 1 ABCD 1 A BCD
MULTIPLE CHOICE QUESTIONS 1 In this list, the operator that is not a basic logical operator is: A AND B OR C NAND D NOT. 2 The operator represented by the " symbol is: A NAND B NOT C NOR D Exclusive-OR. 3 The output of a 3-input NAND gate is low when: A all inputs are low B one input is high C more than one input is low D all inputs are high. 4 The number of input combinations which can make the output of a 4-input OR gate go low is: A 8 B 16 C 15 D 1. 5 The output of an Ex-OR gate is ‘0’ when: A A is ‘0’. B A is ‘1’ and B is ‘0’. C A and B are the same. D A and B are different. 6 The combination of inputs that produces a low output from the system below is: A All low B A high, B and C low C A and B high, C low D All high.
00
01
11
10
00
1
0
0
1
1
01
0
0
0
1
1
0
11
0
1
0
0
A
0
0
10
1
0
0
1
B
D.C
(d)
C FIGURE 19.16
Z