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Long-term reliability of Ti–Pt–Au metallization system for Schottky contact and first-level metallization on SiC MESFET
Microelectronics Reliability 44 (2004) 1109–1113 www.elsevier.com/locate/microrel
Long-term reliability of Ti–Pt–Au metallization system for Schottky contact and first-level metallization on SiC MESFET A. Sozza b
a,b,*
, C. Dua b, A. Kerlain b, C. Brylinski b, E. Zanoni
a
a Dipartimento di Ingegneria dell’Informazione, Via Gradedigo, 6/B, 35131 Padova, Italy Thales Research and Technology France, Domaine de Corbeville, Orsay Cedex F-91404, France
Received 21 March 2003; received in revised form 19 September 2003 Available online 10 May 2004
Abstract The stability of metal layers on semiconductors is a key issue for the device electrical performances. Therefore, the reliability of SiC/Ti/Pt/Au system was investigated using storage steady-stress testing, AES (Auger Electron Spectrometry), and SIMS (Secondary Ions Mass Spectrometry) analysis. The study was conducted on different patterns for gate and interconnection structure to underline the different reliability problems. Auger and SIMS analysis showed important modifications in the three-metal structure without reactions with the SiC substrate. The resistance degradation was assigned to interdiffusion phenomena. It was analyzed with a diffusion-controlled model. Activation energies and mean time to failure (MTF) were calculated for a failure criterion defined as a 10% increase of the resistance. Finally, the different rules of the metallization degradation in MESFET behaviours for interconnections and gate were discussed. 2004 Elsevier Ltd. All rights reserved.
1. Introduction Silicon carbide is receiving great attention for highpower and high-temperature applications for groundbased telecommunication systems due to its excellent physical and chemical properties. Various high-power devices such as MOSFET and MESFET were studied during the recent years. In particular, the fabrication of reliable power MESFETs requires thermally stable gate and interconnection metallizations. Different metals (Au, Pt, Pd, Ni, Co, ...) were investigated for Schottky gate contacts on n-type SiC. Ti demonstrated good characteristics for Schottky contacts on SiC [1,2], whereas Au is classically used in integrated circuits because of its excellent conductivity, lack of oxidation, and its resistance to electromigration failures [3]. A possible compromise for taking advantage of the characteristics
of these two metals is to utilize a two layer metallization Ti–Au. To prevent interdiffusion between Ti and Au, a third metal has to be introduced. As already experienced in other technologies (Si, GaAs) Ti–Pt–Au was reported as good metallization scheme for high-temperature operation. In the present work, we studied the resistance evolution of Ti–Pt–Au structure for gate and first-level metallization on SiC MESFET. The test patterns were annealed at namely three temperatures 400, 440 and 480 C. Chemical reactions and diffusion processes in the SiC Ti–Pt–Au layers were investigated by AES (Auger Electron Spectroscopy) and SIMS (Secondary Ion Mass Spectroscopy) analysis.
2. Device processing
*
Corresponding author. Tel.: +39-049-827-7786; fax: +39049-827-7699. E-mail address: [email protected] (A. Sozza).
The Schottky contacts were formed on 4H-SiC wafers from CREE Inc. These wafers consisted of P/N/Nþ epitaxial structures grown on SiC substrates: a P-type buffer, an N-active layer, and a Nþ contact layer. The typical
0026-2714/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2004.01.017
A. Sozza et al. / Microelectronics Reliability 44 (2004) 1109–1113
thicknesses and doping levels were: 0.2 lm and ND ¼ 1 1019 cm3 for the Nþ contact layer, 0.3–0.4 lm and ND ¼ 1 1017 cm3 for the active layer. MESFETs with several gate developments and several PCM (process control monitoring) patterns called TEST2 were fabricated on these wafers (see [4] for fabrication process). Concerning characterization, we studied the following test structures: (1) 5 lm length serpentine of Ti–Pt–Au resistor (G5l) which reproduced the interconnected structure (2) 1lm length strip of Ti–Pt–Au resistor (G1l) which reproduced the gate structure. The metallization process was the same for the two structures and consists of multilayer deposited by eTi–Pt–Au contact (500–500–5000 A) beam evaporation. PECVD-deposited SiO2 and Si3 N4 were used for passivation. The metallization was not annealed during the process (450 at 340 C).
∆
1110
√
Fig. 1. Resistance evolution for G5l metallization at 400, 440 and 480 C.
A preliminary step––stress testing was performed for a quick exploration of metallization evolution. The increase of the metallization resistance during the first annealing steps suggested the presence of a diffusionlimited degradation mechanism, so a specific long-term steady life test was planned. The samples were divided into three groups of five samples each and storage tests at 400, 440 and 480 C were carried out. The time intervals between two measurements of the parameters were 1, 3, 12, 48, 80, 112, 144 h at 400 C, 150 , 450 , 3, 21, 39, 57, 75 h at 440 C, 150 , 450 , 3, 5, 7, 9, 11 h at 480 C. These sequences were chosen to have a better fitting of the data plotted with a square root of time scale. After each step the samples were cooled to room temperature, the resistances of elements G5l and G1l were measured. Because of the small dimensions of the test patterns, the chemical analysis were made on metallization structures of bigger area. They exhibited the same resistance evolution as G5l and G1l, confirming that intrinsic properties of the SiC/Ti/Pt/Au system were observed.
4. Results and discussion 4.1. Electrical properties Figs. 1 and 2 show percentage changes in resistance DR=R for steady stress at 400, 440 and 480 C, where R was the initial value of G5l and G1l resistance and DR the deviation from the initial value (the evolution is a function of the square root of the annealing time). The Ti–Pt–Au metallization resistance evolution presents an increase during all the annealing time but with different rate at the different storage temperatures. The resistance increase followed a linear relationship with the square root of the annealing time at least for the first part of the
∆
3. Experiment
√
Fig. 2. Resistance evolution for G1l metallization at 400, 440 and 480 C.
evolution (Fig. 3) and this behaviour pointed out a diffusion-limited process. This increase was assigned to metals scattering into Au, in particular the diffusion of the Pt barrier itself. Assuming this, the slopes of the curves are proportional to the square root of the diffusivity of the process (D1=2 ) when solving Fick’s equation oCðx; tÞ o2 Cðx; tÞ ¼D ot ox2
ð1Þ
for thin metallic film diffusing completely into another metal [5] where Cðx; tÞ is the concentration of solute, D is the diffusivity assumed constant at a given temperature. It was not possible to fit all the data of Fig. 1 but a two regions division appears clearly: a first strongly linear region (Fig. 3) that can be due to enhanced diffusion of impurities through Au grain boundaries, and a second
A. Sozza et al. / Microelectronics Reliability 44 (2004) 1109–1113
1111
G5l and 1.17 eV for G1l were obtained. These values are close to 1 eV as proposed by Sinha [6] for the evolution of the Ti–Pt–Au metallization without chemical interaction with the substrate on which it is deposited. In terms of reliability, considering the use of the Ti– Pt–Au as first-level metallization (G5l pattern) and assuming a 10% resistance increase for failure criterion, the extrapolated MTF is 0.45 · 105 h at 150 C operation temperature. The same calculation when using the Ti–Pt–Au metallization for the gate realization (G1l pattern) gives a 182 h MTF at 250 C operation temperature. The gate region can overrun this temperature in high-power applications for which SiC MESFET were designed. 4.2. Chemical properties Fig. 3. Interpolated linear curves (first region) of increase of R as a function of square root of time at 400, 440 and 480 C.
sub-linear one which could be due to different mechanisms (see Section 4.2). The relationship between diffusivity and temperature for the first region can be expressed as EA ð2Þ D ¼ D0 exp kT where D0 is a proportional constant, EA is the activation energy, T is the temperature, and k is the Boltzmann constant. By plotting the diffusivity D as a function of 1=T in an Arrhenius plot for the three temperatures, activation energy EA was extracted for the first region of the slope of the obtained straight line (Fig. 4). With this calculation the two activation energies of 1.10 eV for
As underlined in Section 3 dedicated structures were used for correct execution of AES and SIMS analysis. In order to study the correlation between the evolution of the resistance and the degradation of the metallization, the samples were annealed at 480 C for 50 min, 25 h, 254 h and then analyzed. As shown in Fig. 5(a) the As-deposited structure presented a sequence of steep interfaces Au/Pt, Pt/Ti and Ti/SiC whereas, annealing caused broadening of the interfaces due to interdiffusion of all elements and changed significantly the multilayer structure and resistivity, as reported in Figs. 5(b)–(d). After 50 min of annealing SIMS analysis (Fig. 5(b)) shows the beginning of the interfaces change and in particular the diffusion of Pt into the Au. The presence of Pt was not confirmed by AES analysis but this could be due to the small concentration of Pt diffused into the gold, probably near or lower than the detection limit of AES detector. This leads to an average Pt concentration of 1–2% which is in agreement with the variation of the resistance. In fact, as reported by Sinha [6], the resistivity (in q Æ cm) of the alloyed Au layer increases linearly with the Pt concentration c (in at.%) in accordance with the relationship
∆
∆√
qAu–Pt ¼ 2:5 þ 0:9c
µ
Fig. 4. Arrhenius plot for the calculation of the activation energy of the increase in R for diffusion in the first evolution region (EA ¼ 1:10 eV) (for G5l).
ð3Þ
For 1% Pt concentration, the law predicts an augmentation of about 35% which is verified by the measurements in the first part of the curve (Fig. 3). Meanwhile, as reported by several authors [6,7], Pt acts as a barrier to the diffusion of Au into the Ti as confirmed by the analysis (Fig. 5(b)). The Pt/Ti interface prevents the Pt diffusion through Ti towards SiC and hinders the Ti penetration into Au layer. However both SIMS and Auger analysis showed the beginning of the Au–Pt and Pt–Ti interfaces degradation. In particular Ti were found in Au–Pt interface in the form of islands (Fig. 7). With regard to Ti/SiC interface AES analysis shows the
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A. Sozza et al. / Microelectronics Reliability 44 (2004) 1109–1113
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Fig. 5. SIMS Analysis. (a) As-deposited (b) After 50 min of annealing at 480 C (c) After 25 h of annealing at 480 C (d) After 254 h of annealing at 480 C.
stabilization of the interface thanks to Ti reaction with C deriving from SiC dissociation forming TiC which acts as a barrier to further Ti diffusion in SiC (Fig. 6) (see also [2]).
Fig. 7. Islands of Ti at the Au/Pt interface.
Fig. 6. AES profile after 50 min.
After 25 h of annealing the resistivity of the metallization reached its maximum. The increase between 50 min and 25 h is sub-linear. Since the SIMS (Fig. 5(c)) and Auger analysis did not reveal any increase in Pt concentration into Au, the change of the rate could be assigned to different mechanisms such as activation of other diffusion mechanisms or important modification in
A. Sozza et al. / Microelectronics Reliability 44 (2004) 1109–1113
1113
gold grains size. Moreover SIMS and AES revealed an increase of Ti concentration in Au layer. After 243 h of annealing the metallization presented an important decrease of its resistivity but no analytical prevision was possible because of the strong interdiffusion among the different metals. In fact, SIMS (Fig. 5(d)) and AES showed the presence of Ti, Pt in high percentage into the Au layer and the presence of Ti–Pt islands at the interface Au/Pt are reported: the former steep Au/Pt and Pt/Ti interfaces of the trimetal structure were then gradual.
oscillation (fmax ) and then degrade the frequency performances of high-power devices.
5. Conclusions
References
This work underlines the important modifications in the tri-metal structure Ti–Pt–Au deposited on SiC during high-temperature long-term annealing. The resistance changes of the structure were studied using steady state life curves and the calculation gives an activation energy of nearly 1.1 eV. A MTF value of 0.45 · 105 h at 150 C was obtained for 10% resistance increase. Therefore the tri-level metallization is suitable candidate for interconnecion directly deposited on SiC for operation at temperatures around 150 C. The rise of resistivity at higher temperature could become more critical. Regarding to the realization of Schottky contact on SiC for MESFET gates, SiC/Ti/Pt/Au has a stable behaviour in terms of electrical characteristics (ideality factor, barrier height) as reported by Kassamakova [2], but presents low MTF predictions for the resistivity evolution at high-channel temperatures. This increase might lead to a decrease of the maximum frequency of
[1] Porter LM, Davis RF. A critical review of ohmic and rectifying contacts for silicon carbide. Mater Sci Eng B 1995;34:83–105. [2] Kassamakova L et al. Thermostable Ti/Au/Pt/Ti Schottky contacts to n-type 4H–SiC. Semicons Sci Techno 1998; 13:1025–30. [3] Poate JM, Turner PA, DeBonte J. Thin-film interdiffusion. I. Au–Pd, Pd–Au, Ti–Pd, Ti–Au, Ti–Pd–Au, and Ti–Au– Pd. J Appl Phys 1975;46(10):4275–90. [4] Noblanc O, Arnodo C, Chartier E, Brylinski C. Characterization of power MESFETs on 4H–SiC conductive and semi-insulating wafers. Mater Sci Forum 1998;264–268:949– 52. [5] Sze SM. VLSI Technology. New York, USA; 1988. p. 280– 326 [Chapter 7]. [6] Sinha AK, Smith TE, Sheng TT. Thin film diffusion of platinum in gold. Thin Solid Films 1974;22:1–10. [7] Kitaura Y et al. Long term reliability of Pt and Mo diffusion barriers in Ti–Pt–Au and Ti–Mo–Au metallization system for GaAs digital integrated circuits. J Vac Sci Technol B 1994;12(5).
Acknowledgements The authors are thankful to the technological team of TRT for their contribution. This work was supported by the French DGA program PEA Marcos SiC.
Long-term reliability of Ti–Pt–Au metallization system for Schottky contact and first-level metallization on SiC MESFET A. Sozza b
a,b,*
, C. Dua b, A. Kerlain b, C. Brylinski b, E. Zanoni
a
a Dipartimento di Ingegneria dell’Informazione, Via Gradedigo, 6/B, 35131 Padova, Italy Thales Research and Technology France, Domaine de Corbeville, Orsay Cedex F-91404, France
Received 21 March 2003; received in revised form 19 September 2003 Available online 10 May 2004
Abstract The stability of metal layers on semiconductors is a key issue for the device electrical performances. Therefore, the reliability of SiC/Ti/Pt/Au system was investigated using storage steady-stress testing, AES (Auger Electron Spectrometry), and SIMS (Secondary Ions Mass Spectrometry) analysis. The study was conducted on different patterns for gate and interconnection structure to underline the different reliability problems. Auger and SIMS analysis showed important modifications in the three-metal structure without reactions with the SiC substrate. The resistance degradation was assigned to interdiffusion phenomena. It was analyzed with a diffusion-controlled model. Activation energies and mean time to failure (MTF) were calculated for a failure criterion defined as a 10% increase of the resistance. Finally, the different rules of the metallization degradation in MESFET behaviours for interconnections and gate were discussed. 2004 Elsevier Ltd. All rights reserved.
1. Introduction Silicon carbide is receiving great attention for highpower and high-temperature applications for groundbased telecommunication systems due to its excellent physical and chemical properties. Various high-power devices such as MOSFET and MESFET were studied during the recent years. In particular, the fabrication of reliable power MESFETs requires thermally stable gate and interconnection metallizations. Different metals (Au, Pt, Pd, Ni, Co, ...) were investigated for Schottky gate contacts on n-type SiC. Ti demonstrated good characteristics for Schottky contacts on SiC [1,2], whereas Au is classically used in integrated circuits because of its excellent conductivity, lack of oxidation, and its resistance to electromigration failures [3]. A possible compromise for taking advantage of the characteristics
of these two metals is to utilize a two layer metallization Ti–Au. To prevent interdiffusion between Ti and Au, a third metal has to be introduced. As already experienced in other technologies (Si, GaAs) Ti–Pt–Au was reported as good metallization scheme for high-temperature operation. In the present work, we studied the resistance evolution of Ti–Pt–Au structure for gate and first-level metallization on SiC MESFET. The test patterns were annealed at namely three temperatures 400, 440 and 480 C. Chemical reactions and diffusion processes in the SiC Ti–Pt–Au layers were investigated by AES (Auger Electron Spectroscopy) and SIMS (Secondary Ion Mass Spectroscopy) analysis.
2. Device processing
*
Corresponding author. Tel.: +39-049-827-7786; fax: +39049-827-7699. E-mail address: [email protected] (A. Sozza).
The Schottky contacts were formed on 4H-SiC wafers from CREE Inc. These wafers consisted of P/N/Nþ epitaxial structures grown on SiC substrates: a P-type buffer, an N-active layer, and a Nþ contact layer. The typical
0026-2714/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2004.01.017
A. Sozza et al. / Microelectronics Reliability 44 (2004) 1109–1113
thicknesses and doping levels were: 0.2 lm and ND ¼ 1 1019 cm3 for the Nþ contact layer, 0.3–0.4 lm and ND ¼ 1 1017 cm3 for the active layer. MESFETs with several gate developments and several PCM (process control monitoring) patterns called TEST2 were fabricated on these wafers (see [4] for fabrication process). Concerning characterization, we studied the following test structures: (1) 5 lm length serpentine of Ti–Pt–Au resistor (G5l) which reproduced the interconnected structure (2) 1lm length strip of Ti–Pt–Au resistor (G1l) which reproduced the gate structure. The metallization process was the same for the two structures and consists of multilayer deposited by eTi–Pt–Au contact (500–500–5000 A) beam evaporation. PECVD-deposited SiO2 and Si3 N4 were used for passivation. The metallization was not annealed during the process (450 at 340 C).
∆
1110
√
Fig. 1. Resistance evolution for G5l metallization at 400, 440 and 480 C.
A preliminary step––stress testing was performed for a quick exploration of metallization evolution. The increase of the metallization resistance during the first annealing steps suggested the presence of a diffusionlimited degradation mechanism, so a specific long-term steady life test was planned. The samples were divided into three groups of five samples each and storage tests at 400, 440 and 480 C were carried out. The time intervals between two measurements of the parameters were 1, 3, 12, 48, 80, 112, 144 h at 400 C, 150 , 450 , 3, 21, 39, 57, 75 h at 440 C, 150 , 450 , 3, 5, 7, 9, 11 h at 480 C. These sequences were chosen to have a better fitting of the data plotted with a square root of time scale. After each step the samples were cooled to room temperature, the resistances of elements G5l and G1l were measured. Because of the small dimensions of the test patterns, the chemical analysis were made on metallization structures of bigger area. They exhibited the same resistance evolution as G5l and G1l, confirming that intrinsic properties of the SiC/Ti/Pt/Au system were observed.
4. Results and discussion 4.1. Electrical properties Figs. 1 and 2 show percentage changes in resistance DR=R for steady stress at 400, 440 and 480 C, where R was the initial value of G5l and G1l resistance and DR the deviation from the initial value (the evolution is a function of the square root of the annealing time). The Ti–Pt–Au metallization resistance evolution presents an increase during all the annealing time but with different rate at the different storage temperatures. The resistance increase followed a linear relationship with the square root of the annealing time at least for the first part of the
∆
3. Experiment
√
Fig. 2. Resistance evolution for G1l metallization at 400, 440 and 480 C.
evolution (Fig. 3) and this behaviour pointed out a diffusion-limited process. This increase was assigned to metals scattering into Au, in particular the diffusion of the Pt barrier itself. Assuming this, the slopes of the curves are proportional to the square root of the diffusivity of the process (D1=2 ) when solving Fick’s equation oCðx; tÞ o2 Cðx; tÞ ¼D ot ox2
ð1Þ
for thin metallic film diffusing completely into another metal [5] where Cðx; tÞ is the concentration of solute, D is the diffusivity assumed constant at a given temperature. It was not possible to fit all the data of Fig. 1 but a two regions division appears clearly: a first strongly linear region (Fig. 3) that can be due to enhanced diffusion of impurities through Au grain boundaries, and a second
A. Sozza et al. / Microelectronics Reliability 44 (2004) 1109–1113
1111
G5l and 1.17 eV for G1l were obtained. These values are close to 1 eV as proposed by Sinha [6] for the evolution of the Ti–Pt–Au metallization without chemical interaction with the substrate on which it is deposited. In terms of reliability, considering the use of the Ti– Pt–Au as first-level metallization (G5l pattern) and assuming a 10% resistance increase for failure criterion, the extrapolated MTF is 0.45 · 105 h at 150 C operation temperature. The same calculation when using the Ti–Pt–Au metallization for the gate realization (G1l pattern) gives a 182 h MTF at 250 C operation temperature. The gate region can overrun this temperature in high-power applications for which SiC MESFET were designed. 4.2. Chemical properties Fig. 3. Interpolated linear curves (first region) of increase of R as a function of square root of time at 400, 440 and 480 C.
sub-linear one which could be due to different mechanisms (see Section 4.2). The relationship between diffusivity and temperature for the first region can be expressed as EA ð2Þ D ¼ D0 exp kT where D0 is a proportional constant, EA is the activation energy, T is the temperature, and k is the Boltzmann constant. By plotting the diffusivity D as a function of 1=T in an Arrhenius plot for the three temperatures, activation energy EA was extracted for the first region of the slope of the obtained straight line (Fig. 4). With this calculation the two activation energies of 1.10 eV for
As underlined in Section 3 dedicated structures were used for correct execution of AES and SIMS analysis. In order to study the correlation between the evolution of the resistance and the degradation of the metallization, the samples were annealed at 480 C for 50 min, 25 h, 254 h and then analyzed. As shown in Fig. 5(a) the As-deposited structure presented a sequence of steep interfaces Au/Pt, Pt/Ti and Ti/SiC whereas, annealing caused broadening of the interfaces due to interdiffusion of all elements and changed significantly the multilayer structure and resistivity, as reported in Figs. 5(b)–(d). After 50 min of annealing SIMS analysis (Fig. 5(b)) shows the beginning of the interfaces change and in particular the diffusion of Pt into the Au. The presence of Pt was not confirmed by AES analysis but this could be due to the small concentration of Pt diffused into the gold, probably near or lower than the detection limit of AES detector. This leads to an average Pt concentration of 1–2% which is in agreement with the variation of the resistance. In fact, as reported by Sinha [6], the resistivity (in q Æ cm) of the alloyed Au layer increases linearly with the Pt concentration c (in at.%) in accordance with the relationship
∆
∆√
qAu–Pt ¼ 2:5 þ 0:9c
µ
Fig. 4. Arrhenius plot for the calculation of the activation energy of the increase in R for diffusion in the first evolution region (EA ¼ 1:10 eV) (for G5l).
ð3Þ
For 1% Pt concentration, the law predicts an augmentation of about 35% which is verified by the measurements in the first part of the curve (Fig. 3). Meanwhile, as reported by several authors [6,7], Pt acts as a barrier to the diffusion of Au into the Ti as confirmed by the analysis (Fig. 5(b)). The Pt/Ti interface prevents the Pt diffusion through Ti towards SiC and hinders the Ti penetration into Au layer. However both SIMS and Auger analysis showed the beginning of the Au–Pt and Pt–Ti interfaces degradation. In particular Ti were found in Au–Pt interface in the form of islands (Fig. 7). With regard to Ti/SiC interface AES analysis shows the
1112
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Fig. 5. SIMS Analysis. (a) As-deposited (b) After 50 min of annealing at 480 C (c) After 25 h of annealing at 480 C (d) After 254 h of annealing at 480 C.
stabilization of the interface thanks to Ti reaction with C deriving from SiC dissociation forming TiC which acts as a barrier to further Ti diffusion in SiC (Fig. 6) (see also [2]).
Fig. 7. Islands of Ti at the Au/Pt interface.
Fig. 6. AES profile after 50 min.
After 25 h of annealing the resistivity of the metallization reached its maximum. The increase between 50 min and 25 h is sub-linear. Since the SIMS (Fig. 5(c)) and Auger analysis did not reveal any increase in Pt concentration into Au, the change of the rate could be assigned to different mechanisms such as activation of other diffusion mechanisms or important modification in
A. Sozza et al. / Microelectronics Reliability 44 (2004) 1109–1113
1113
gold grains size. Moreover SIMS and AES revealed an increase of Ti concentration in Au layer. After 243 h of annealing the metallization presented an important decrease of its resistivity but no analytical prevision was possible because of the strong interdiffusion among the different metals. In fact, SIMS (Fig. 5(d)) and AES showed the presence of Ti, Pt in high percentage into the Au layer and the presence of Ti–Pt islands at the interface Au/Pt are reported: the former steep Au/Pt and Pt/Ti interfaces of the trimetal structure were then gradual.
oscillation (fmax ) and then degrade the frequency performances of high-power devices.
5. Conclusions
References
This work underlines the important modifications in the tri-metal structure Ti–Pt–Au deposited on SiC during high-temperature long-term annealing. The resistance changes of the structure were studied using steady state life curves and the calculation gives an activation energy of nearly 1.1 eV. A MTF value of 0.45 · 105 h at 150 C was obtained for 10% resistance increase. Therefore the tri-level metallization is suitable candidate for interconnecion directly deposited on SiC for operation at temperatures around 150 C. The rise of resistivity at higher temperature could become more critical. Regarding to the realization of Schottky contact on SiC for MESFET gates, SiC/Ti/Pt/Au has a stable behaviour in terms of electrical characteristics (ideality factor, barrier height) as reported by Kassamakova [2], but presents low MTF predictions for the resistivity evolution at high-channel temperatures. This increase might lead to a decrease of the maximum frequency of
[1] Porter LM, Davis RF. A critical review of ohmic and rectifying contacts for silicon carbide. Mater Sci Eng B 1995;34:83–105. [2] Kassamakova L et al. Thermostable Ti/Au/Pt/Ti Schottky contacts to n-type 4H–SiC. Semicons Sci Techno 1998; 13:1025–30. [3] Poate JM, Turner PA, DeBonte J. Thin-film interdiffusion. I. Au–Pd, Pd–Au, Ti–Pd, Ti–Au, Ti–Pd–Au, and Ti–Au– Pd. J Appl Phys 1975;46(10):4275–90. [4] Noblanc O, Arnodo C, Chartier E, Brylinski C. Characterization of power MESFETs on 4H–SiC conductive and semi-insulating wafers. Mater Sci Forum 1998;264–268:949– 52. [5] Sze SM. VLSI Technology. New York, USA; 1988. p. 280– 326 [Chapter 7]. [6] Sinha AK, Smith TE, Sheng TT. Thin film diffusion of platinum in gold. Thin Solid Films 1974;22:1–10. [7] Kitaura Y et al. Long term reliability of Pt and Mo diffusion barriers in Ti–Pt–Au and Ti–Mo–Au metallization system for GaAs digital integrated circuits. J Vac Sci Technol B 1994;12(5).
Acknowledgements The authors are thankful to the technological team of TRT for their contribution. This work was supported by the French DGA program PEA Marcos SiC.