Lot streaming for product assembly in job shop environment

ARTICLE IN PRESS

Robotics and Computer-Integrated Manufacturing 24 (2008) 321–331 www.elsevier.com/locate/rcim

Lot streaming for product assembly in job shop environment F.T.S. Chan, T.C. Wong, L.Y. Chan Department of Industrial and Manufacturing Systems Engineering, The University of Hong Kong, Pokfulam Road, HKSAR, China Received 26 May 2006; received in revised form 21 September 2006; accepted 4 January 2007

Abstract Assembly job shop scheduling problem (AJSP) is an extension of classical job shop scheduling problem (JSP). AJSP starts with JSP and appends an assembly stage to the completed jobs. Lot streaming (LS) technique is a process of splitting jobs into smaller sub-jobs such that successive operations can be overlapped. This paper combines, for the first time, LS and AJSP, extending LS applicability to both machining and assembly. To solve this complex problem, an efficient algorithm is proposed using genetic algorithms and simple dispatching rules. Experimental results suggest that equal size LS outperforms varied size LS with respect to the objective function. r 2007 Published by Elsevier Ltd. Keywords: Assembly job shop; Lot streaming; Genetic algorithms; Dispatching rules

1. Introduction In this paper, a job or a lot is defined as a batch of identical items or components. In order to complete a job, all of its operations should be processed on the machines. If there is assembly stage, only the completed jobs from the same bill-of-material (BOM) can be assembled for the final product. If no assembly is available, the completed jobs should be stored at the inventory. The assembly of the final product and each subassembly in the same BOM can start only when all of its components are completed. Classical job shop scheduling problem (JSP) is one of the most wellknown scheduling issues and it assumes that there is no assembly stage after the job completion. One common objective of most of the available JSP models is the minimization of lateness which is defined as the penalty for completing jobs beyond its due dates. Lot streaming (LS) technique which allows splitting of jobs into sub-jobs can improve shop floor performance. As a result, lead time can be shortened and more jobs or sub-jobs may meet its due dates. In the current study, assembly job shop scheduling problem (AJSP) which appends an assembly stage to JSP has been studied. For the first time, we attempt to extend the Corresponding author. Tel.: +852 2859 7059; fax: +852 2858 6535.

E-mail address: [email protected] (F.T.S. Chan). 0736-5845/$ - see front matter r 2007 Published by Elsevier Ltd. doi:10.1016/j.rcim.2007.01.001

application of LS to AJSP. To justify this study, the research objectives now become the minimization of the delay cost of the final products and the storage cost of the completed jobs and sub-jobs at the inventory. In addition to job shop features, the assembly stage should be solved in AJSP which can be regarded as an advanced version of JSP. Given the demand of a product, the relative job demands that supply the same product must be determined. If necessary, Manufacturing Resource Planning software packages can help to determine the batch sizes of components over a certain planning period. However, it is commonly assumed that the lot size is a constant, i.e. lot splitting is not allowed (e.g. [1]). Hence, we argue that the significance of LS must not be underrated in the shop floor level. For example, if a lot is composed of 4 identical items or components, there are at least 4 ways to split it: (1) {1,1,1,1} means 4 sub-jobs of size 1, (2) {1,1,2}, (3) {2,2} or {1,3}, and (4) no splitting. Hence, we have total 5 sub-job combinations. Since the combination increases significantly with the lot size and the number of jobs, it is necessary to develop an efficient algorithm. The determination of sub-job combinations is not the end of the story. After splitting jobs into sub-jobs, we need to solve AJSP which is also NP-hard. In this paper, an efficient algorithm has been proposed to solve this complex problem using genetic algorithms (GAs) and simple dispatching rules (SDRs).

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2. Literature review P1

LS technique which was first introduced by Reiter [2] is a methodology to split a job into smaller sub-jobs such that successive operations of the same job can be overlapped. Thus, the lead time of the whole job can be possibly shortened. Prior to job splitting, the nature of job size and the sub-job type should be defined. In general, the job size can be discrete or continuous. Discrete job size means a job contains an integer number of identical items. Continuous job size can be a real number. Also, the sub-lot type can be variable or consistent. Variable type means that the sub-job size may vary between successive machines. Consistent type restricts that the sub-job size is fixed. Over the past few years, LS has been prevalently applied to flow shop problem (FSP) [3–5] which only allows one route for all jobs. Thus, the maximum operation overlapping can derive the optimum makespan. It implies that jobs are split into single-unit sub-jobs. In reality, this is often infeasible due to various practical constraints. Nevertheless, this ‘‘one-route-for-all’’ feature has enabled LS to work its very best in FSP. In contrast, LS seems not very promising in JSP and open shop problem (OSP). Even so, some studies about LS to JSP [6,7] and OSP [8] can be found. According to Trietsch and Baker [9], LS can be classified into 4 types: (I) equal size (ES) sub-jobs without intermittent idling means that jobs are split into sub-jobs with even size and are processed on the same machine continuously, (II) ES sub-jobs with intermittent idling that allows idle time between sub-jobs on the same machine, (III) varied size (VS) sub-jobs without intermittent idling means that jobs are split into sub-jobs of uneven size and there is no idle time between sub-jobs on the same machine, and (IV) VS sub-jobs with intermittent idling. For a comprehensive review on LS, please refer to Chang and Chiu [10]. Assembly is usually defined as the process to construct a final product from its components. One basic rule is that components or items can be assembled only if they belong to the same BOM. The complexity of a product mainly depends on the number of its components and the assembly levels. Furthermore, each component must be dedicated to only one product. A typical product structure with 4 assembly levels is presented in Fig. 1. The top level is Product 1 (P1). The second level contains Assembly 1 (A1), Assembly 2 (A2), and Component 2 (C2). A1 is the assembly of A3 and C2. C4 and C5 are assembled for A3 and so on. To study AJSP, there are mainly two streams. The first stream only allows machining to the components but not the assemblies. The second stream allows both machining and assembly to the assemblies. Similar to the current study, Kim and Kim [11] have studied AJSP with no machining for the assemblies, i.e. the first stream. They have compared two evolutionary algorithms for minimizing the earliness penalty of sub-jobs and the tardiness penalty of the final products. For simplicity, lot splitting is neglected. McKoy and Egbelu [12] have presented a 12-step

A1

A3

C4

A2

A4

C2

C5

C6

C1

A5

C3

C7

C8

C9

Fig. 1. A typical product structure.

heuristic to minimize the production flow time for AJSP. Comparisons are made between their proposed heuristic and the mixed integer linear program (MILP) on some test problems. The results have suggested MILP performs better in terms of solution quality. However, MILP requires substantial computational time to obtain the optimality. Thus, their proposed algorithm is more preferable if the problem size is big and computational time is relatively significant. However, LS is clearly not considered. Thiagarajan and Rajendran [13] have proposed 10 dispatching rules to solve AJSP with jobs having different holding and tardiness costs. In their study, a 3-level product structure is used to define the product complexity. They have incorporated those penalties into the proposed dispatching rules. The experiment results reveal that some rules perform better with respect to some weighted objectives (costs). They have successfully dealt with the fact that jobs may carry different penalty costs but failed to consider the impact of lot splitting. In reality, those costs are usually given and fixed. Therefore, more attention must be given to lot splitting. Guide et al. [14] have discussed the priority scheduling policies (or SDRs) in repair shop with no spares. In their paper, the repair shop contains a disassembly area, a repair area and an assembly area. All components of the disassembled products from the disassembly area are processed or repaired through a fixed sequence of operations in the repair area which contains a number of work centres. Then all repaired components are re-assembled in the assembly area. Since each component has its unique and fixed operation sequence, this shop actually can be regarded as AJSP. In addition to different product structures, they have further classified the component matching into three levels, i.e. serial number specific, common, and the mix of them. They have reported that SDRs may outperform complex optimization methods

ARTICLE IN PRESS F.T.S. Chan et al. / Robotics and Computer-Integrated Manufacturing 24 (2008) 321–331

under medium–high uncertainty levels. However, lot splitting again is ignored. Hence, this paper attempts to fill the gap and illustrate the significance and usefulness of LS to AJSP. In the next section, problem background and formulations are given. Section 4 describes the mechanism of the proposed algorithm. Section 5 presents the computational results. The significance of the experiment results is discussed in Section 6. Finally, Section 7 concludes the paper with a summary and recommendations for future research direction.

Work

N

Station

323

Inventory Station

Ready for product assembly?

Assembly Station

Y Fig. 2. Layout of assembly job shop.

3. Problem background 3.1. Notations p m ‘ ‘n Ph DM h DDh CN h Ath Cth Mi CF i Lhj Rhj Qhj F hj MS hjk Pthjk SU hjk Sthjk Cthjk SN hj Lhjs Qhjs Sthjsk Cthjsk lch ichj

total type of products total number of machines total number of lots total number of sub-lots product h demand of product h due date of product h total number of components of product h assembly time of product h delivery time of product h machine i current fixture type on M i lot j of product h ratio of product h to the component in lot j lot size of Lhj fixture type of Lhj machine for kth operation of Lhj processing time of kth operation of Lhj setup time of kth operation of Lhj start time of kth operation of Lhj completion time of kth operation of Lhj sub-lot number of Lhj sth sub-lot of Lhj lot size ofLhjs start time of kth operation of Lhjs completion time of kth operation of Lhjs late cost of Ph per unit per hour inventory cost of Lhj per unit per hour

3.2. Problem formulation In this paper, AJSP contains a Work Station, an Inventory Station and an Assembly Station as shown in Fig. 2. The Work Station contains m distinct machines. For each planning period, there are p product types. Each product Ph contains CN h 2 ½2; 10 distinct components 8h ¼ 1 . . . p, i.e. its BOM. The demand of Ph is given as DM h 2 ½1; 50 unit(s). According to Potts and Van Wassenhove [15], the due date of Ph can be generated from a

discrete uniform distribution DDh 2 ½g  ð1  a  b=2Þ; g  ð1  a þ b=2Þ hour(s) where g as defined by Eq. (2), a 2 ½0:1; 0:5, and b 2 ½0:8; 1:8, respectively. The assembly time of Ph at the Assembly Station is Ath 2 ½10; 50 hour(s). Aforementioned, a lot is composed of identical components only, thus there are total ‘ lots as shown in Eq. (3) and the lot size of Lhj is Qhj by Eq. (4). Rhj 2 ½1; 2 refers to the required unit of components in lot Lhj for one unit of product h. The due date of Lhj is the same as Ph . Same as JSP, Lhj is required to be processed on m machines with processing time Pthjk 2 ½1; 10 hour(s) and setup time SU hjk 2 ½1; 10 hour(s) 8k ¼ 1 . . . m. Lhj can be processed on M i once and SU hjk is counted only if CF i aF hj , otherwise SU hjk ¼ 0. Lhj can only be processed in the Work Station and all finished lots should be stored at the Inventory Station until at least one unit of Ph can be assembled. Then, Lhj will be transferred to the Assembly Station for product assembly and Ph can be delivered to the customer. The delivery time of Ph is Cth as shown in Eq. (5). It means that Ph can be delivered only if all Lhj are completed. This equation is valid if LS is not allowed. However, if LS is permitted, Eq. (5) is not applicable. In this paper, only types II and IV LS models which allow idle time between sub-lots on the same machine are considered with discrete lot size and consistent sub-lot type. With LS, Lhj can be split into SN hj sub-lots. The total number of Lhjs (‘n Þ is obtained from Eq. (6). The due date, fixture type, product ratio, machine sequence, processing time, and setup time of sub-lot Lhjs are the same as that of the original lot Lhj . Eq. (7) restricts that the total lot size of sub-lots should satisfy the original lot size. The late cost of Ph per unit per hour is lch 2 ½0:1; 1:0 and the inventory cost of Lhj per unit per hour is ichj 2 ½0:01; 0:10. Noted that the late cost is calculated per product and the inventory cost is counted per lot or sub-lot. Also, work-in-process (WIP) inventory is not counted. It is reminded that the research objectives are to minimize both costs. If LS is not allowed, the objective function ðZÞ is defined by Eq. (1). The first part of Z is the lateness of all Ph and the second part is the inventory cost of all Lhj . With LS, Z is considered with respect to time as there may be different Cth values if Lhj can be split.

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Objective: Min Z ¼

4. The proposed algorithm

p X

fCth  DDh gþ  DM h  lch

h¼1

þ

p X CN h X ðCth  Cthjm  Ath Þ  Qhj  ichj .

ð1Þ

h¼1 j¼1

Parameter constraints: p X CN h X m X

g¼ ‘¼

!, Pthjk  Qhj

m,

ð2Þ

h¼1 j¼1 k¼1 p X

CN h ,

ð3Þ

h¼1

Qhj ¼ DM h  Rhj

8h ¼ 1 . . . p; j ¼ 1 . . . CN h ,

ð4Þ

Cth ¼ maxðCthjm Þ þ Ath where k ¼ m ‘n ¼

p X CN h X

8h ¼ 1 . . . p; j ¼ 1 . . . CN h ,

SN hj ,

ð5Þ ð6Þ

h¼1 j¼1 SN Xhj

Qhjs  Qhj ¼ 0

8h ¼ 1 . . . p; j ¼ 1 . . . CN h .

ð7Þ

If LS is allowed, the current problem can be divided into 2 sub-problems, Sub-Problem 1 (SP1): Determination of sub-lot combinations and Sub-Problem 2 (SP2): AJSP with all sublots. In Section 1, we have already discussed the complexity of the sub-lot combinations. In this connection, one of the robust evolutionary algorithms, GA, is proposed to solve SP1. In fact, SP1 is already a complex problem, not to mention about SP2 which is NP-hard. If GA is applied to both SP1 and SP2, the final solution must be good but huge computational effort is required. Since timely decision is a major emphasis, tedious computational effort may delay the decision-making process. Also, there are many forms of objective functions and constraints in real world manufacturing environment such that random search technique with SDRs may perform better over exhaustive approaches [16]. Despite the use of some sophisticated systems, the extensive execution of the software is often required to highlight any deviations from the original plan [17]. To solve this problem, SDRs which are time-saving and straightforward also can perform quite well in assembly shop [13,18,19]. Hence, SDR is proposed to solve SP2. Fig. 3 shows the mechanism of the proposed algorithm. The details will be given in the following sub-sections.

s¼1

Same as JSP, lots are processed on m distinct machines. If LS is not considered, Eq. (8) restricts that all lots should be processed with respect to the predefined processing sequence. Also, each machine can process only one lot and preemption is prohibited. The queuing time of lots between kth and (k þ 1)th operation is defined in Eq. (9) and there is unlimited buffer for WIP. Furthermore, all lots are ready for processing at the beginning of each planning period by Eq. (10). Also, resource shortage and machine failure are not considered. Operational constraints: Sthjðkþ1Þ XSthjk þ Pthjk  Qhj þ SU hjk

8h ¼ 1 . . . p,

j ¼ 1 . . . CN h ; k ¼ 1 . . . m, Sthjðkþ1Þ  Cthjk X0 8h ¼ 1 . . . p; j ¼ 1 . . . CN h , k ¼ 1 . . . m, Sthj0 ¼ Cthj0 ¼ 0

ð8Þ ð9Þ

8h ¼ 1 . . . p; j ¼ 1 . . . CN h .

4.1. Genetic algorithm GA which was first introduced by Holland [20] has been widely applied for solving complex combinatorial problems. Its principles follow the natural evolution and the rule of survival of the fittest. It means that good solutions will have greater chances to survive and mate with others. Solutions must be encoded as chromosomes. Firstly, GA starts with a pool (or generation) of initial chromosomes and each chromosome must be evaluated with respect to the objective function. For minimization (or maximization) problem, chromosomes with lower (or higher) objective values will have higher fitness values. Fitter chromosomes then will have more chances to be combined with its mates through crossover operation. This operation usually allows a pair of parental chromosomes to mate with each other in order to produce a pair of child chromosomes or offsprings. Each child chromosome may only preserve a

ð10Þ

Likewise, the same set of operational constraints Eq. (11)–Eq. (13) is also applicable to all sub-lots once LS is allowed.

SP1: Determine GA sub-lot combinations

Sthjsðkþ1Þ XSthjsk þ Pthjk  Qhjs þ SU hjk

8h ¼ 1 . . . p,

j ¼ 1 . . . CN h ; s ¼ 1 . . . SN hj ; k ¼ 1 . . . m, Sthjsðkþ1Þ  Cthjsk X0 8h ¼ 1 . . . p; j ¼ 1 . . . CN h ,

ð11Þ

s ¼ 1 . . . SN hj ; k ¼ 1 . . . m, Sthjs0 ¼ Cthjs0 ¼ 0 8h ¼ 1 . . . p; j ¼ 1 . . . CN h ,

ð12Þ

s ¼ 1 . . . SN hj .

SP2: Solve AJSP with

ð13Þ

sub-lots

SDR

Fig. 3. The proposed algorithm.

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predefined portion of its parental chromosome. This predefined portion is controlled by the crossover rate. After crossover operation, child chromosomes may be selftransformed subject to a probability. This process is controlled by the mutation rate. Then the child chromosomes can enter the next generation. Also, Elitism which refers to the transfer of the best chromosome from the previous pool to the current pool is applied. The procedure goes repeatedly until the terminating criteria are met. Roulette Wheel Selection Scheme is implemented to select chromosomes for crossover operation. This scheme treats a pool of chromosomes as a wheel in which the portion occupied by a chromosome is directly proportional to its fitness value. Therefore, fitter chromosomes may be chosen more than one time on a wheel. Mutation rate is low such that it helps to prevent premature convergence, i.e. trapped in local optima. It is noted that the number of chromosomes in a pool is referred to as population size ðPSÞ and the total number of pools is regarded as generation number ðGENÞ. The transformation of objective value to fitness value is governed by Eq. (14). The objective value ðZÞ is obtained from Eq. (1) FV c ¼ ðMAX  Z c þ MINÞ=AVE

8c ¼ 1 . . . PS,

(14)

where FV c is the fitness value of cth chromosome, MAX the maximum objective value of the same generation, Z c the objective value of cth chromosome, MIN the minimum objective value of the same generation, and AVE the average objective value of the same generation. To successfully implement GA to SP1, solutions must be first encoded as chromosomes. Fig. 4 shows the proposed chromosome structure in a 2-dimension matrix (X,Y). If ð1; YÞ ¼ SN hj ¼ 1, it means that no splitting is applied to the lot. Otherwise, if ð1; YÞ ¼ SN hj 41, it means that the lot is split into SN hj sub-lots. ð2 . . . SN hj þ 1; YÞ indicates the size of each sub-lot of Lhj . If ES LS is applied, Qhjs ¼ Qhj =SN hj and Qhj XSN hj . One possible case is that if ðQhj =SN hj Þ is not an integer, then Qhjs ¼ intðQhj =SN hj Þ and P the size of the last sub-lot QhjSN hj ¼ Qhj  s Qhjs 8s ¼ 1 . . . ðSN hj  1Þ. For VS LS, Qhjs is already defined by Eq. (7). Fig. 5 shows the crossover and mutation operations of the proposed GA for p ¼ 2, CN 1 ¼ 2, CN 2 ¼ 1, DM 1 ¼ 5, DM 2 ¼ 6, Q11 ¼ 5, Q12 ¼ 5, and Q21 ¼ 6. From 6a, the second row has been exchanged between C1 and C2. From 6b, the third row of chromosome C1 has been mutated. The mutation operation is defined as the regeneration of (1,Y). In this case, (1,Y)

325

Fig. 5. Crossover and (b) mutation operation of the proposed GA.

value is the same but the sub-lot combination has been updated. 4.2. Simple dispatching rules The four proposed SDRs to solve SP2 are: shortest processing time (SPT), longest processing time (LPT), minimum slack time (MST), and earliest due date (EDD). In this study, non-delay schedule is constructed such that the job processing priority on each machine is only the preference list. It means that a lot can be processed either if the machine is idle or if the current queue does not contain lots or sub-lots with higher priority. SPT prefers lots or sub-lots with the shortest processing time to be scheduled first and LPT is the opposite case. MST refers to the difference (slack time) between due date and the total processing time of lots or sub-lots. If the difference is small, it means that lots or sub-lots with less slack time must be scheduled first. EDD means that lots or sub-lots with early due date must be processed first. Mathematically, these four SDRs can be defined as: SPT: Lot or sub-lot A ranks higher than lot or sub-lot B if the processing time of kA th operation of lot or sub-lot A is shorter than that of kB th operation of lot or sub-lot B on the same machine. RankA 4RankB

if PthA jA kA oPthB jB kB

and MS hA jA kA ¼ MS hB jB kB . LPT: Opposite to SPT, LPT can be defined as RankA 4RankB if PthA jA kA 4PthB j B kB and MS hA jA kA ¼ MS hB jB kB . MST: Lot or sub-lot A ranks higher than lot or sub-lot B if the slack time of lot or sub-lot A is smaller than that of lot or sub-lot B on all machines. Thus, there is only one ranking of all lots or sub-lots. ! m X RankA 4RankB if DDhA  PthA j A kA  QhA j A kA ¼1

o DDhB 

m X

!

PthB j B kB  QhB jB .

kB ¼1

Fig. 4. The proposed chromosome structure.

EDD: Lot or sub-lot A ranks higher than lot or sub-lot B if the due date of lot or sub-lot A is earlier than that of lot or sub-lot B on all machines. Thus, there is only one

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326

ranking of all lots or sub-lots. RankA 4RankB

if DDhA oDDhB .

Therefore, all lots or sub-lots can be ranked on each machine with respect to each SDR. The ranking is the same as the preference list that indicates the possible processing sequence. Hence, the proposed algorithm actually can solve SP1 and SP2 simultaneously. The final solution must give the best sub-lot combination with the best SDR for optimizing the objective function ðZÞ. 5. Computational results In this section, a number of experiments will be performed to examine the proposed algorithm. The main purpose is to address the performances of different SDRs under various LS approaches. There are two primary factors: m ¼ 3, 5, 7 and p ¼ 3, 5, 7, 10, i.e. total 12 different problems. For each problem, 100 instances will be randomly generated and solved by the proposed algorithm. The algorithm together with the four SDRs will be executed in 3 modes: no LS, ES LS, and VS LS. The algorithm performances are measured by the late cost and the penalty cost (late cost+inventory cost). To summarize, the experimental background is reported in Table 1. Thus, the total number of experiments is ð3  4  4  3  2Þ  100 replications ¼ 28 800. After some preliminary tests, GA parameters are set as PS ¼ 20, GEN ¼ 100, crossover rate ¼ 0:7, and mutation rate ¼ 0:02. Tables 2–4 report the algorithm performances without LS for minimizing the first part of Z in (1), i.e. product lateness. The ‘‘m’’ and ‘‘p’’ columns indicate the total number of machines and product types, respectively. The ‘‘SDR’’ column indicates the current SDR. The ‘‘LS’’ column shows the current mode of LS. The ‘‘Sec’’ column shows the average computational time in seconds over 100 problems. The ‘‘Result’’ column indicates the average lateness cost obtained over 100 problems. It can be observed that EDD outperforms the rest in most of the problems. The second best is MST then followed by SPT and LPT. Tables 5–7 show the algorithm performances under ES and VS LS approaches for minimizing the lateness cost. The meanings of the first six columns are explained before. The ‘‘Best’’ column refers to the number of problems in which the minimum lateness cost is obtained by the current SDR over 100 problems. ‘‘% Diff.’’ calculates the percentage difference between the average lateness cost obtained by the best SDR Table 1 The experiment settings Factors

Levels

m p SDR LS modes Objectives

3; 5; 7 3; 5; 7; 10 SPT, LPT, MST, EDD No LS, equal size LS, varied size LS Lateness cost, penalty cost

Table 2 Lateness cost obtained for m ¼ 3 without LS m

p

SDR

LS

Sec.

Result

3

3

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

48379.6 62691.9 36407.6 34350.1

3

5

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

87171.7 132 886 49 488 44512.3

3

7

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

170 285 258 418 70625.5 64459.6

3

10

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

336 288 496 416 103 212 89997.1

Result

Table 3 Lateness cost obtained for m ¼ 5 without LS m

p

SDR

LS

Sec.

5

3

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

67524.8 88939.7 58207.7 56563.3

5

5

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

136 183 184 532 93264.4 85401.8

5

7

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

216 422 314 772 117 576 108 098

5

10

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

389 030 564 972 143 048 123 146

and the remainder. For example, if m ¼ 3 and p ¼ 3 or 3  3 in Table 5, the average computational time ¼ 6:83 s, the average lateness cost obtained ¼ 17 339, the minimum lateness cost obtained in 31 out of 100 problems and percentage difference is 0 if using MST with VS LS approach or MST-VS. Tables 6 and 7 report the experiment results for m ¼ 5 and 7, respectively. First of all, it is obvious that LS can substantially reduce the average lateness cost obtained over no LS for all test problems. For smaller problems (m ¼ 3), it is observed that MST-ES, MST-VS, and EDD-ES outperform the rest. They combine to obtain the minimum lateness cost in 377 out of 400 problems, i.e. 94.25%. It is noted that only 279 out of 400 problems are achieved by MST-ES and EDD-ES, i.e. 69.75%. However, when m increases, MST-ES and

ARTICLE IN PRESS F.T.S. Chan et al. / Robotics and Computer-Integrated Manufacturing 24 (2008) 321–331 Table 4 Lateness cost obtained for m ¼ 7 without LS m

p

7

3

7

5

7

7

7

10

Table 6 Lateness cost obtained for m ¼ 5 with LS

SDR

LS

Sec.

Result

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

168 435 229 188 129 606 120 142

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

249 003 352 910 173 255 154 693

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

451 020 678 482 228 081 208 112

72705.9 92122.9 69854.3 70 018

m 5

p 3

p

SDR

LS

Sec.

SPT

ES VS ES VS ES VS ES VS

7.75 6.24 8.44 6.22 10.53 6.83 6.85 6.08

ES VS ES VS ES VS ES VS

SDR

LS

SPT

ES VS ES VS ES VS ES VS

10.6 6.3 11.85 6.51 17.02 7.76 8.14 5.79

ES VS ES VS ES VS ES VS

LPT MST EDD 5

5

SPT LPT MST EDD

5

7

SPT LPT

Table 5 Lateness cost obtained for m ¼ 3 with LS m

MST Result

Best

%Diff.

36153.6 37310.4 54064.3 54256.9 17 473 17 339 17496.5 20133.7

6 4 1 0 28 31 33 2

52.04 53.53 67.93 68.04 0.77 0 0.9 13.88

12.91 8.96 14.39 9.14 18.44 10.03 10.87 8.34

77819.3 77 604 119 690 120 076 28412.8 29207.5 28 820 31 993

2 0 0 0 35 28 40 6

63.49 63.39 76.26 76.34 0 2.72 1.41 11.19

ES VS ES VS ES VS ES VS

20.43 11.1 21.07 11.38 28.62 12.91 15.39 10.1

155 641 151 958 234 803 232 484 42919.1 46105.2 44551.1 47724.2

0 2 0 0 50 30 21 5

72.42 71.76 81.72 81.54 0 6.91 3.66 10.07

ES VS ES VS ES VS ES VS

39.35 19.34 43 49.52 56.37 22.48 30.11 16.78

290 993 278 886 445 299 438 216 53508.6 57113.9 55204.1 59191.2

0 0 0 0 46 25 26 4

81.61 80.81 87.98 87.79 0 6.31 3.07 9.6

EDD 3

3

LPT MST EDD 3

5

SPT LPT MST EDD

3

7

SPT LPT MST EDD

3

10

SPT LPT MST EDD

327

EDD-ES clearly become the 2 dominant approaches. For m ¼ 5, they combine to obtain the minimum lateness cost in 339 out of 400 problems, i.e. 84.75%. For m ¼ 7, they

5

10

SPT LPT MST EDD

Sec.

Result

Best

%Diff.

42 844 45 352 60 552 61 952 23 440 26 947 25 146 30 220

8 2 0 0 52 12 28 1

45.29 48.32 61.29 62.16 0 13.01 6.78 22.44

21.97 11.22 26.3 11.57 36.61 13.9 16.18 9.49

101 108 102 757 150 515 153 594 43726.2 49556.2 48689.4 57306.8

1 2 0 0 56 16 25 0

56.75 57.45 70.95 71.53 0 11.76 10.19 23.7

ES VS ES VS ES VS ES VS

36.06 15.41 41.29 16.07 55.92 19.52 24.42 12.64

171 171 169 668 256 014 256 418 45647.5 54392.3 49260.9 57784.3

0 0 0 0 60 11 29 0

73.33 73.1 82.17 82.2 0 16.08 7.34 21

ES VS ES VS ES VS ES VS

63.6 25.49 76.02 26.84 106.38 32.11 43.87 19.8

345 431 336 049 516 389 510 543 71 450 84 317 76 209 85 555

0 0 0 0 68 10 21 1

79.32 78.74 86.16 86.01 0 15.26 6.24 16.49

obtain the minimum lateness cost in 359 out of 400 problems, i.e. 89.75%. The results show that the dominance of MST-ES and EDD-ES increases from 69.75% to 89.75% when m increases from 3 to 7. Independently, MST-ES is the best for 159 (m ¼ 3Þ þ 236 ðm ¼ 5Þ þ 244 ðm ¼ 7Þ ¼ 639 out of 1200 problems (53.25%) and EDD-ES is the best for 120 (m ¼ 3Þ þ 103 ðm ¼ 5Þ þ 116 ðm ¼ 7Þ ¼ 339 out of 1200 problems (28.25%). Furthermore, if only the average lateness cost is compared, MST-ES performs better than EDD-ES by 5.7% on average which ranges from 1.41% to 10.19%. Therefore, MST-ES is the best recommended approach to minimize lateness cost for medium to large size AJSP. Tables 8–10 testify the algorithm performances without LS for minimizing Z, i.e. the penalty cost ¼ the late costs of products + the inventory costs of lots or sub-lots. The ‘‘Result’’ column shows the average penalty cost obtained over 100 problems and the ‘‘Best’’ column refers to the number of problems in which the minimum penalty cost is obtained by the current SDR over 100 problems. ‘‘% Diff.’’ calculates the percentage difference between the average penalty cost attained by the best SDR and the remainder.

ARTICLE IN PRESS F.T.S. Chan et al. / Robotics and Computer-Integrated Manufacturing 24 (2008) 321–331

328

Table 7 Lateness cost obtained for m ¼ 7 with LS m 7

p 3

EDD SPT LPT MST EDD 10

37.31 43.71 56.37 59.34 0 19.88 6.51 27.6

5

34.03 14.4 41.8 15.34 60.1 19.83 24.54 11.95

117 485 122 848 170 997 173 759 51929.9 64015.2 56558.2 71738.5

1 1 0 0 64 8 26 0

55.8 57.73 69.63 70.11 0 18.88 8.18 27.61

ES VS ES VS ES VS ES VS

57.68 21.3 70 23.29 102.54 30.41 39.78 16.93

205 718 208 576 303 453 307 542 81849.1 100 389 85415.8 106 474

0 1 0 0 64 6 29 0

60.21 60.76 73.03 73.39 0 18.47 4.18 23.13

ES VS ES VS ES VS ES VS

96.5 33.69 117.62 36.52 168 47.67 64.8 25.26

347 519 341 907 515 458 516 658 91961.7 111 666 96938.2 117 190

0 0 0 0 66 9 27 0

73.54 73.1 82.16 82.2 0 17.65 5.13 21.53

ES VS ES VS ES VS ES VS

MST

7

9 1 0 1 50 5 34 1

16.07 8.09 18.12 8.23 28.16 10.36 12.15 7.04

SPT

7

48383.8 53878.9 69519.5 74585.1 30329.9 37854.9 32442.9 41892.8

ES VS ES VS ES VS ES VS

LPT

7

m

SPT

EDD 5

%Diff.

LS

MST

7

Best

SDR

LPT

SPT LPT MST EDD

Table 9 Penalty cost obtained for m ¼ 5 without LS

Sec.

Result

p

SDR

LS

Sec.

Result

3

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

92990.7 115 930 74717.7 71 494

5

5

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

216 482 275 586 133 728 121 883

5

7

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

329 874 411 361 164 883 148 615

5

10

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

627 707 801 729 241 813 205 114

Table 10 Penalty cost obtained for m ¼ 7 without LS m

p

p

SDR

LS

Sec.

Result

3

3

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

83321.4 94908.8 53927.2 55372.2

3

5

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

179 593 210 246 89669.5 79293.7

3

7

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

332 461 409 944 117 427 106 832

3

10

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

572 374 700 530 170 636 148 094

Similarly, it is noted that EDD again surpassed other rules in most of the problems. The second best is MST followed by SPT and LPT. It is expected that EDD must perform well

LS

Sec.

Result

7

3

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

106 070 128 647 97709.5 96485.1

7

5

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

212 889 261 563 156 398 145 776

7

7

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

387 987 474 747 223 234 207 957

7

10

SPT LPT MST EDD

No No No No

o1 o1 o1 o1

740 825 965 634 328 595 302 292

Table 8 Penalty cost obtained for m ¼ 3 without LS m

SDR

since its mechanism is to schedule lots with early due date such that overdue can be possibly evaded. SPT and LPT may perform better if the objective is flow time or makespan. Tables 11–13 report the algorithm performances under ES and VS LS approaches for minimizing the penalty cost. It is also obvious that LS can improve the performance over no LS in minimizing the average penalty cost for all test problems. For m ¼ 3, MST-ES, MST-VS, and EDD-ES outperform the rest. They combine to obtain the minimum penalty cost in 382 out of 400 problems, i.e. 95.5%. MST-ES and EDD-ES acquire the minimum penalty cost in only 261 out of 400, i.e. 65.25%. For m ¼ 5, MST-ES and EDD-ES combine to obtain the minimum penalty cost in 331 out of 400 problems, i.e. 82.75%. For m ¼ 7, they further improve the dominance to 90.25%, i.e. 361 out of 400 problems.

ARTICLE IN PRESS F.T.S. Chan et al. / Robotics and Computer-Integrated Manufacturing 24 (2008) 321–331 Table 11 Penalty cost obtained for m ¼ 3 with LS m 3

p 3

EDD SPT LPT MST EDD 3

10

56.38 56.38 64.4 64.07 3.99 0 2.69 10.29

5

11.38 7.71 12.42 7.93 18.12 9.24 9.39 7.2

148 235 146 388 175 334 173 429 45 001 44801.3 45109.4 49805.5

0 0 0 0 29 34 34 3

69.78 69.4 74.45 74.17 0.44 0 0.68 10.05

5

ES VS ES VS ES VS ES VS

20.01 11.34 21.86 11.59 31.24 13.58 15.62 10.28

319 005 311 473 382 744 377 747 70785.3 73817.1 69483.5 76043.6

0 0 0 0 31 26 40 3

78.22 77.69 81.85 81.61 1.84 5.87 0 8.63

5

ES VS ES VS ES VS ES VS

38.48 18.58 41.34 19.34 59.72 23.08 30.43 16.22

553 100 536 633 651 668 638 540 97851.8 105 147 97969.1 105 331

0 0 0 0 35 19 40 6

82.31 81.77 84.98 84.68 0 6.94 0.12 7.1

5

ES VS ES VS ES VS ES VS

SPT

MST

7

0 1 0 1 25 42 27 4

6.91 5.66 7.3 5.7 9.9 6.45 6.03 5.54

LPT

3

70351.4 70342.3 86200.3 85398.7 31961.8 30685.2 31534.6 34203.4

ES VS ES VS ES VS ES VS

EDD 5

m

SPT

MST

3

%Diff.

LS

LPT

SPT LPT MST EDD

Table 12 Penalty cost obtained for m ¼ 5 with LS Best

SDR

Sec.

329

Result

Independently, MST-ES is the best for 120 (m ¼ 3Þþ 192 ðm ¼ 5Þ þ 224 ðm ¼ 7Þ ¼ 536=1200 problems (44.67%) and EDD-ES is the best for 141 (m ¼ 3Þ þ 139 ðm ¼ 5Þþ 137 ðm ¼ 7Þ ¼ 417=1200 problems (34.75%). If we consider the average penalty cost obtained only, MST-ES outperforms EDD-ES by 0.12% to 5.01, average 2.69%. In this connection, MST-ES is the best recommended approach to minimize the penalty cost for medium to large size AJSP. Fig. 6 presents the convergence of the proposed GA to one of the test problems, 7  10, for minimizing the late cost. Note that the dotted line refers to the average value and the solid line represents the best value. In general, the sound convergence is scrutinized over 100 generations. 6. Discussions It is noted that MST and EDD perform relatively better than SPT and LPT. One reason is that both MST and EDD have considered the due date of lots or sub-lots. Without LS, EDD performs slightly better than MST. If LS is allowed, it is interesting to observe that MST mostly

p 3

SDR

LS

SPT

ES VS ES VS ES VS ES VS

10.29 6.75 11.31 6.9 16.29 7.98 8.15 6.07

ES VS ES VS ES VS ES VS

LPT MST EDD 5

SPT LPT MST EDD

7

SPT LPT MST EDD

10

SPT LPT MST EDD

Sec.

Result

Best

%Diff.

61664.7 63687.8 75 994 78115.4 32743.2 35858.8 34362.6 40296.3

5 0 0 0 51 19 26 0

46.9 48.59 56.91 58.08 0 8.69 4.71 18.74

19.14 10.14 22.57 10.69 32.1 13.01 14.36 8.84

149 590 150 279 181 977 183 204 52397.7 58127.5 54447.8 63038.7

1 0 0 0 47 20 30 2

64.97 65.13 71.21 71.4 0 9.86 3.77 16.88

ES VS ES VS ES VS ES VS

37.63 16.42 45.36 17.45 62.17 21.76 27.36 13.72

305 497 300 707 379 157 373 357 84445.1 94325.3 87040.2 100 096

0 0 0 0 56 12 31 1

72.36 71.92 77.73 77.38 0 10.47 2.98 15.64

ES VS ES VS ES VS ES VS

68.3 26.41 77.36 27.83 116.51 34.22 47.65 20.53

589 072 569 916 726 638 715 951 126 829 148 008 124 056 139 996

0 0 0 0 38 9 52 1

78.94 78.23 82.93 82.67 2.19 16.18 0 11.39

performs better than EDD. Another research question is that which LS approach works better, ES or VS? If the objective is the product lateness and only the average late cost obtained is compared, MST-VS outperforms MST-ES by merely 0.77% for 3  3. For 3  5, MST-ES outperforms MST-VS by 2.72%. When p increases, MST-ES clearly surpasses MST-VS by 6.91% and 6.31% for 3  7 and 3  10 apiece. For m ¼ 5 and 7, MST-ES overwhelms MST-VS by no less than 11.76% (up to maximum 19.88%). For EDD, EDD-ES clearly outperforms EDDVS for all test problems. If the objective is the penalty cost and only the average penalty cost obtained is compared, MST-VS outperforms MST-ES by 3.99% and 0.44% for 3  3 and 3  5, respectively. When m and p increases, MST-VS never defeats MST-ES again. For m ¼ 5, MSTES conquers MST-VS by at least 8.69% (up to maximum 14.31%). For m ¼ 7, MST-ES outperforms MST-VS by at least 13.3% (up to maximum 16.96%). Generally speaking, if using MST, the differences between ES and VS modes become explicit with increasing m and p. For EDD, EDDES always outperforms EDD-VS in all cases.

ARTICLE IN PRESS F.T.S. Chan et al. / Robotics and Computer-Integrated Manufacturing 24 (2008) 321–331

330

Table 13 Penalty cost obtained for m ¼ 7 with LS m 7

p 3

SDR

LS

SPT

ES VS ES VS ES VS ES VS

14.8 7.87 17.53 8.2 26.08 10.53 11.86 6.97

ES VS ES VS ES VS ES VS

33.92 15.07 41.57 17.88 61.79 21.11 25.04 12.51

ES VS ES VS ES VS ES VS ES VS ES VS ES VS ES VS

LPT MST EDD 7

5

SPT LPT MST EDD

7

7

SPT LPT MST EDD

7

10

SPT LPT MST EDD

Sec.

Result

Best

%Diff.

69680.6 73506.6 91154.1 94780.3 40281.6 46460.3 42407.7 52648.5

2 1 0 0 58 16 24 0

42.19 45.2 55.81 57.5 0 13.3 5.01 23.49

189 009 192 072 237 209 245 664 78146.5 92728.7 81632.9 100 006

0 0 0 0 56 10 33 1

58.65 59.31 67.06 68.19 0 15.73 4.27 21.86

58.86 21.63 70.7 23.28 105.97 31.06 40.56 17.52

312 252 310 507 385 268 387 555 106 606 125 919 107 208 129 578

0 0 0 0 53 5 40 2

65.86 65.67 72.33 72.49 0 15.34 0.56 17.73

115.52 38.74 134.48 41.57 199.33 55.04 76.72 29.65

620 617 610 842 787 163 776 893 150 366 181 081 150 553 183 568

0 0

75.77 75.38 80.9 80.65 0 16.96 0.12 18.09

0 57 3 40 0

7x10 200000 Best Average

150000 100000 50000 0

1

11

21

31

41

51

61

71

81

91

Fig. 6. Convergence of the proposed GA for 7  10.

In this connection, ES mode is more preferable than VS mode. It is because the delivery of the final product depends on the completion of lots from the same BOM. Unlike JSP, the completion is referred to single lot only. VS mode tends to split various lots into sub-lots of uneven size such that some components may be completed in large quantity, but other components may never be processed. The complexity of AJSP can be depicted as: lots should be processed such

that a sufficient number of components can be finished and assembled to produce at least one unit of the final product as close as its due date. To justify the efficiency of LS, the inventory cost can indicate whether the number and size of sub-lots are effective to deliver the final product. In other words, a good LS technique must allow sub-lots to possibly avoid lodging at the inventory before final product assembly. In this paper, the combination of ES mode and MST performs quite well for most of the test problems. 7. Conclusions In this research, an efficient algorithm is developed to solve the problem in which lots can be split into sub-lots and there is an assembly stage after JSP. To measure the algorithm performances, the late cost and inventory cost are the key indicators. To facilitate timely decision making, GA is proposed to determine the sub-job combinations (SP1) and SDRs are used to solve AJSP with all sub-lots (SP2). Using the proposed GA, a single solution can embrace the information that we need to solve the sub-lot combinations, i.e. (i) which lot should be split, (ii) the number of sub-lots, and (iii) the size of each sub-lot. In fact, this inherent advantage cannot be easily achieved by other AI or evolutionary algorithms. To examine the impact of LS on AJSP, a number of test problems have been studied under two different scenarios, i.e. with and without LS. If LS is implemented, two modes are compared, i.e. equal size (ES) and varied size (VS). According to our knowledge, there is no similar GA-based approach to examine the performances of ES and VS modes. Using SDRs, AJSP has been solved promptly. The experiment results suggest that MST with ES mode or MST-ES surpasses the others in terms of two performance measures, i.e. the minimum cost obtained in most of the test problems, and the average cost obtained over all test problems. Since there are very few LS models dedicated to AJSP, this study attempts to fill the gap and provides some insights about the usefulness of LS to assembly problems. Moreover, the proposed algorithm can be easily applied to flow shop, open shop or the mix of them. However, the current model considers only the lateness and inventory penalties that may not be practical enough to simulate the real manufacturing shop floor. Hence, regarding to the future research work, the authors would like to suggest the following issues: more penalties will be introduced like setup cost, transfer cost, WIP cost, etc. Moreover, more constraints can be incorporated, e.g. finite transfer size, finite WIP buffer, resource shortage, machine failure, etc. Appendix JSP FSP OSP AJSP

job shop scheduling problem flow shop scheduling problem open shop scheduling problem assembly job shop scheduling problem

ARTICLE IN PRESS F.T.S. Chan et al. / Robotics and Computer-Integrated Manufacturing 24 (2008) 321–331

LS ES VS GA SDR SPT LPT MST EDD WIP PS GEN SP1 SP2 BOM

lot streaming equal size varied size genetic algorithm simple dispatching rule shortest processing time longest processing time minimum slack time earliest due date work-in-process population size generation number sub problem 1 sub problem 2 bill-of-material

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