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Low electrical resistivity polycrystalline SiGe films obtained by vertical LPCVD for MOS devices
Materials Science and Engineering B 124–125 (2005) 138–142
Low electrical resistivity polycrystalline SiGe films obtained by vertical LPCVD for MOS devices Ricardo Cotrin Teixeira, Ioshiaki Doi ∗ , Maria Beny Pinto Zakia, Jos´e Alexandre Diniz, Jacobus Willibrordus Swart State University of Campinas (UNICAMP), Center for Semiconductor Components (CCS), School of Electrical and Computer Engineering (FEEC), Rua Jo˜ao Pandi´a Cal´ogeras, 90 Caixa Postal 6061, CEP 13083-870 Campinas-SP, Brazil
Abstract In this study, authors present some morphological and electrical characterization of polycrystalline SiGe thin films (poly-SiGe) deposited by vertical LPCVD using SiH4 , GeH4 and H2 mixture in different deposition parameters aiming for MOS gate electrodes. The obtained thin films are very uniform and smooth, with small grain size, feasible to deep submicrom fabrication. The SiGe samples presented resistivity values as low as 0.42 m cm, one order of magnitude lower than poly-Si reference samples. CV and IV measurements points this poly-SiGe as a suitable material for MOS gate electrodes. © 2005 Elsevier B.V. All rights reserved. Keywords: Poly-SiGe; Poly-Si; LPCVD; MOS; Electrical charecterization; SiON
1. Introduction During the last 30 years, polycrystalline Si1−x Gex (polySiGe) alloys have been studied for microelectronics, mainly for bipolar transistors and optical devices such as superlattices [1]. In the last 10 years, poly-SiGe has also been focused on MOS devices to allow deep submicron fabrication [2]. Many advantages emerge from the usage of poly-SiGe as gate electrode for MOS devices as an alternative to poly-Si and metal gate technologies. Compared to the former, the SiGe presents lower power consumption, higher boron activation, no gate depletion and lower resistivity [1,2]. Different Ge fractions in the alloy lead to the so-called engineering workfunction that eliminates the need of channel implantation to achieve the desirable threshold voltage [1,2]. The workfunction tuning also reduces the vertical electric field in the channel region, which is an important condition to improve the carrier mobility and device speed [3]. Despite the metal gate technology seems to be preferred for future sub-50 nm devices, the high-k materials needed for these devices are facing serious dificulties to integration in the present manufacturing plants. Poly-SiGe is especially attractive for the next technological nodes due its compatibility with the well-
∗
Corresponding author. Tel.: +55 19 3788 7282; fax: +55 19 3788 7888. E-mail address: [email protected] (I. Doi).
0921-5107/$ – see front matter © 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.mseb.2005.08.060
established poly-Si deposition steps and Si-based dielectrics (SiO2 and SiON) and because it can be used in both p- and n-type MOS transistors. Furthermore, poly-SiGe MOS gates less than 20 nm length has already been reported in the literature. However, some dificulties are still to be solved such as those related to etching and chemical compatibilities. Poly-SiGe is soluble in hydrogen peroxide, one of the most used components in the wet cleaning steps while the GeO2 is water soluble, what makes oxidation onto the SiGe layers a concern. Chemistry required for gate channel opening by plasma dry etch are still to be defined, despite experiments using HBr have been shown promising relatively to the anisotropic dry etch needs for the next sub-100 nm devices. The electrical characteristics of the thin films and hence, the devices, are highly affected by morphological characteristics such as grain size and surface roughness. These in turn depend on the parameters and precursor used in the deposition process. In this study, authors present electrical and morphological characterization of poly-SiGe alloy deposited in a pancake type – LPCVD system using GeH4 and SiH4 as precursors gases. Samples were analyzed by means of ellipsometry, AFM, SEM and XRD. Very uniform and low rough samples were obtained even at high deposition rate. Rs values of poly-SiGe are much better than similar poly-Si after 31 P+ or 1 1B+ ion implantation and rapid thermal annealing at various conditions. CV and IV curves indicate the poly-SiGe films as a good material for MOS gate
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electrode, with a leakage current of 6 mA/cm−2 (Vgs = −1 V) through SiON dielectrics (EOT = 3.2 nm). 2. Experimental Poly-SiGe thin films were deposited by LPCVD in a PMC200, pancake type, vertical reactor, onto 10 nm thermally oxidized 1 0 0, n-type, 1–10 cm single crystalline silicon substrates. Precursor gases were silane and germane in a hydrogen carrier gas flow. The CVD apparatus has been described elsewhere [4]. The poly-SiGe films were deposited in the temperature range from 500 to 750 ◦ C with 50 ◦ C steps at pressures of at 666 or 1333 Pa (5 or 10 Torr). Since Ge hardly nucleates on silicon oxide, a 30-s Si nucleation step were conducted prior to the SiGe deposition in order to reduce the incubation period. Deposition rate and uniformity of the non-doped poly-SiGe samples were extracted by ellipsometry. Surface rms roughness and grain size were evaluated by AFM (tapping mode) and SEM measurements. After the physical characterization, a second set of poly-SiGe, 200 nm thick, was deposited at 500 ◦ C/666 Pa and implanted with P or B ions in the dose range from 5E14 to 2E16 cm−2 . The implantation damage was annealed at different temperature from 500 up to 900 ◦ C during 40 s in N2 atmosphere using an RTP system. Electrical characterization was performed by means of four point probe measurements, to obtain samples sheet resistance. MOS capacitors were also fabricated with the same poly-SiGe parameter deposition described above and with poly-Si electrodes for comparison. The gate dielectric used in this samples was SiON grown by ECR electron cyclotron resonance (ECR) plasma at ambient temperature. Other growth parameter are as follows: 1000 W ECR; 5 W RF; 7 sccm N2 + 13 sccm O2 + 20 sccm Ar; different pressures were used to obtain SiON films with different thicknesses. Samples were sintered at 450 ◦ C in forming gas ambient for 30 min and no metal deposition was used. CV and IV measurents allows to extract equivalent oxide thickness (EOT) and leakage current of the high-k dieletrics. 3. Results and discussion Micro Raman spectroscopy (Fig. 1) was used to verify the composition of the obtained thin films. The Ge–Ge (∼288 cm−1 ); Ge–Si (∼406 cm−1 ) and Si–Si (∼501 cm−1 ) resonance peaks clearly indicate that thin films of the Si–Ge alloy were deposited in the temperature/pressure ranges specified above. We observe that the resonance peaks, mainly the Si–Si resonance, becomes more intense and the FWHM is reduced at higher deposition temperatures. This feature is an indicative that the film becomes more crystalline and less defective as temperature rises. No significant difference can be noticed with pressure rising from 666 to 1333 Pa for the same deposition temperature. We also notice that the relative intensity of the Ge–Ge; Ge–Si and Si–Si peaks varies, indicating a difference in the Ge contents (x). For samples deposited above 650 ◦ C, we could also notice the appearance of another peak around 420 cm−1 corre-
139
sponding to Si–Si bonding surrounded by Ge atoms [5]. Using the proposal presented by Tsang et al. [6] and Jawhari [7], we extracted the Ge fraction (x) of the deposited samples. These calculations shows that the Ge concentration rises fastly with temperature up to 30 and 37%, for samples deposited at 666 and 1333 Pa, respectively, and 600 ◦ C. Above this value, x reduces with increasing temperature, that explain the appearance of the resonance at 420 cm−1 due to the higher Si contents, but it still remains higher than 20% even for the highest pressure and temperature set used in this study. This reduction in Ge contents occurs due to the enhancement in Si deposition observed in this temperature range for the vertical LPCVD system used in this study. Temperature also gives rise to a different internal structure of the analyzed samples as pointed by XRD measurements (Fig. 2). Deposition at 750 ◦ C leads to a strong 1 1 1 preferred orientation (PO) for both 666 and 1333 Pa deposition pressure, but a different behavior is noticed for deposition temperatures below this value. While samples prepared with 666 Pa exhibit a weak 1 1 1 PO at 600 ◦ C, 1333 Pa samples exhibit a 2 2 0 PO, which rises greatly up to 700 ◦ C. Such rising for the 2 2 0 intensity is not observed in the 666 Pa samples. We also observed that there were no dual peaks on the XRD spectra that imply the alloy deposition rather than Si or Ge clusters formation [8] and confirms the Raman results. AFM and SEM measurements also show changes in the morphology of the poly-SiGe films. Grain size from 27 up to 46 nm (Fig. 3, right) were observed from AFM phase images and SEM micrographies. Some very fine boundaries were also noticed, probably related to twinning. Surface roughness analysis (Fig. 3, left) presented a simpler behaviour, related as a parabolic curve as a function of deposition temperature. Minimum roughness of 3.7 nm and 5.5 nm were found for 1333 and 666 Pa pressure deposition, respectively. The increase of the 1333 Pa pressure also leads to a less rough surface than samples obtained at 666 Pa. We believe this is due to higher amorphous contents in the film because of the higher deposition rate achieved at higher pressure. The higher deposition rate enhances the nucleation and does not allow the atoms to be properly arranged in the crystal lattice, leading to smaller grains and higher amorphous fraction, and thus to the lower surface roughness. Roughness increase with temperature is related to the thickness increase of poly-SiGe samples. However, some samples with same thickness deposited at 666 Pa presented higher rms roughness as temperature raises from 650 to 700 ◦ C, as the consequence of the others morphological characteristics effects such as grain size and PO. In general, higher grain size and 1 1 1 orientation, leads to more rough surfaces. 1 1 1 grains needs four atoms and two atomic layers for the growth process, leading to pyramidal structures, while 2 2 0 oriented grains needs just two atoms and one atomic layer. The compromise within this character, the grain size and amorphous fraction composes the surface roughness on an intricate matter, such a way we have roughness increasing with grain size for samples deposited at 666 Pa and the opposite for samples deposited at 1333 Pa. Deposition rates as high as 150 nm/min were achieved in the vertical LPCVD reactor. This rate is higher
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Fig. 1. Raman spectra of typical poly-Si (left) and poly-SiGe (right) samples.
Fig. 2. Intensity variation of the XRD peaks of poly-SiGe samples.
than obtained from literature data [9] and is related to the low activation energy observed. Ea values are 1.13 and 1.20 eV for 1333 and 666 Pa, respectively. Despite the high deposition rates, uniformity <1% were achieved. In order to assure poly-SiGe thin films feasible to deep-submicron MOS devices, a 2 2 0 PO is recommended to achieve a good dopant distribution for gate depletion reduction and a low surface roughness and grain size. The 2 2 0 orientation gives rise to films with a columnar morphology that facilitates
the diffusion of dopant species to the whole film thickness and hence diminishes the gate depletion. These characteristics are found in the temperature range from 600 to 650 ◦ C at both 666 and 1333 Pa, that reinforces the usage of low temperature for the poly-SiGe deposition and consequently a low thermal budget, minimizing the stress induced onto devices during the fabrication steps. In order to verify the electrical characteristics of the polySiGe samples, another set of 200 nm thick samples were
Fig. 3. rms surface roughness (left) and grain size (right) as a function of temperature.
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Fig. 4. Sheet resistance as a function of annealing temperature for: (A) phosphorus and (B) boron doped poly-SiGe samples. Results for poly-Si are also shown for comparison.
deposited at 500 ◦ C/666 Pa (5 Torr) onto 10 nm thermally oxidized p-type substrates. These samples were doped with 31 P+ or 1 1B+ ions at dose range from 4E15 up to 2E16 cm−2 . Ion implantation energies were chosen to allow peak dose at 100 nm (half of the film thickness). Thus, the doped samples were annealed during 40 s in nitrogen atmosphere in the temperature range from 500 to 900 ◦ C. Results of sheet resistance (Rs ) are shown in Fig. 4. Poly-Si samples with same thickness and doping conditions were also prepared for comparison. Poly-SiGe samples exhibited a much lower Rs values than poly-Si for all doping/annealing conditions. Actually, 31 P+ -doped SiGe samples presents lower R values regardless s the annealing temperature. Since Ge presents a resistivity half the value of Si, the insertion of Ge atoms in the alloy greatly enhances the Rs as observed mainly for 31 P+ -doping. Rs also presents a more linear behavior with temperature in the poly-SiGe samples. This means that a great percentage of the implantation damage is annealed even at low temperatures. This behavior is observed in the poly-Si samples only above 700 ◦ C. The higher dopant activation obtained for the SiGe samples can be noticed mainly at low implantation dose. While 5E14 cm−2 P+ ion dose poly-Si samples presented a Rs value
>1000 /sq, poly-SiGe samples prepared with the same implantation dose presented Rs of 550 /sq. The same behavior can be noticed in the 1 1B+ -doped samples (685 /sq for poly-Si samples versus 185 /sq for poly-SiGe samples). This characteristic allows the usage of lower temperatures and dose implant to obtain the same Rs values of poly-Si films. Indeed, 100 /sq gate electrode may be obtained for poly-Si implanted with 31 P+ at 2E16 cm−2 /900 ◦ C annealing and 1 1B+ at 1E16 cm−2 /900 ◦ C annealing. The same result was achieved in poly-SiGe in samples with 31 P+ at 1E16 (5E15) cm−2 at/500 (900) ◦ C annealing and 1 1B+ at 1E16 cm−2 /700 ◦ C annealing. The ability to use low thermal budgets/implantation dose is one of great importance to allow formation of shallow junctions in the next device generation. MOS capacitors were also fabricated with the same polySiGe parameter deposition described above onto a high-k SiON dielectrics grown by ECR. Similar poly-Si samples were also prepared for comparison. Samples were sintered at 450 ◦ C in forming gas ambient for 30 min and no metal deposition was used. EOT and I × V results are shown in Fig. 5. From the CV measurements we obtain EOT from 0.46 to 4.7 nm for the SiON dielectrics for the poly-SiGe samples, while the poly-Si gated devices presented no measurable CV charac-
Fig. 5. EOT (left) and I × V (right) characteristics of MOS capacitors with poly-SiGe as gate electrode and SiON as gate dielectric. IV data for poly-Si is also shown for comparison.
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teristics. We believe this is due the high temperature needed to poly-Si deposition (800 ◦ C) in the vertical system we used that degraded the dielectrics layer. On the other hand, the low temperature employed for poly-SiGe deposition has no adverse effect onto the SiON and a very good agreement with data simulated by CVC software [10] was observed in CV curves. IV measurements confirms the dielectrics degradation, as polySi capacitors presented a very high leakage current density of 8.3 A/cm2 at Vgs = −1 V, while poly-SiGe devices presented a very low leakage current of 6 mA/cm−2 in the same Vgs conditions. EOT measurents performed onto the SiGe gated capacitors also shows the referred process is suitable for very low thickness dielectrics. 4. Conclusions Poly-SiGe thin films were obtained in the vertical LPCVD system at very high deposition rates (up to 150 nm/min). Despite the high values of deposition rates, poly-SiGe thin films presented a very uniform thickness, with less than 1% variation. Samples also presented a low rms surface roughness (below 5 nm) and grain size (from 27 to 49 nm). The electrical characteristics of poly-SiGe doped samples are superior to similar poly-Si thin films for both 31 P+ and 1 1B+ doping regardless the annealing temperature employed. These features points the poly-SiGe obtained by vertical LPCVD suitable for MOS devices in the sub-100 nm range. The low thermal budget needed for poly-SiGe MOS capacitors also allows fabrication of devices onto SiON dielectrics with EOT below 1 nm.
Acknowledgments Authors acknowledge CCS staff for their help in sample preparation, the MTA and LME groups from LNLS/Brasil for the AFM and SEM micrographies, respectively, to Prof. Fernando Iikawa and Prof. Dr. Lisandro P. Cardoso, from IFGW/UNICAMP, for the micro-Raman and XRD measurements, respectively. This work has the financial support of CNPq, CAPES, FAPESP and FAEP-UNICAMP. References [1] D.L. Harame, S.J. Koester, G. Freeman, P. Cottrel, K. Rim, G. Dehlinger, D. Ahlgren, J.S. Dunn, D. Greenberg, A. Joseph, F. Anderson, J.S. Rieh, S.A.S.T. Onge, D. Coolbaugh, V. Ramacharandran, J.D. Cressler, S. Subbanna, Appl. Surf. Sci. (2004) 224. [2] Y.V. Ponomarev, P.A. Stolk, C. Salm, J. Schmitz, P.H. Woerlee, IEEE Trans. Electron Devices 47 (2000) 4. [3] W.C. Lee, B. Watson, T.J. King, C. Hu, IEEE Electron Device Lett. 20 (1999) 5. [4] R.C. Teixeira, I. Doi, J.A. Diniz, M.B.P. Zakia, J.W. Swart, Influence of ton the deposition rate of Si-poly obtained by vertical LPCVD, in: XXIV CeBRAVIC, Bauru/SP, Brazil, 2003. [5] M. Krause, H. Stiebig, R. Carius, U. Zastrow, H. Bay, H. Wagner, J. Non-Cryst. Solids 299–302 (2002) 1. [6] J.C. Tsang, P.M. Mooney, F. Dacol, J.O. Chu, J. Appl. Phys. 75 (1994) 12. [7] T. Jawhari, Analusis 28 (2000) 1. [8] L.K. Teh, W.K. Choi, L.K. Bera, W.K. Chin, Solid State Electron. 45 (2001) 1963. [9] A.E. Franke, J.M. Heck, T.J. King, R.T. Howe, J. Microelectromech. Syst. 12 (2003) 2. [10] J.H. Hauser, CVC software, North Caroline State University.
Low electrical resistivity polycrystalline SiGe films obtained by vertical LPCVD for MOS devices Ricardo Cotrin Teixeira, Ioshiaki Doi ∗ , Maria Beny Pinto Zakia, Jos´e Alexandre Diniz, Jacobus Willibrordus Swart State University of Campinas (UNICAMP), Center for Semiconductor Components (CCS), School of Electrical and Computer Engineering (FEEC), Rua Jo˜ao Pandi´a Cal´ogeras, 90 Caixa Postal 6061, CEP 13083-870 Campinas-SP, Brazil
Abstract In this study, authors present some morphological and electrical characterization of polycrystalline SiGe thin films (poly-SiGe) deposited by vertical LPCVD using SiH4 , GeH4 and H2 mixture in different deposition parameters aiming for MOS gate electrodes. The obtained thin films are very uniform and smooth, with small grain size, feasible to deep submicrom fabrication. The SiGe samples presented resistivity values as low as 0.42 m cm, one order of magnitude lower than poly-Si reference samples. CV and IV measurements points this poly-SiGe as a suitable material for MOS gate electrodes. © 2005 Elsevier B.V. All rights reserved. Keywords: Poly-SiGe; Poly-Si; LPCVD; MOS; Electrical charecterization; SiON
1. Introduction During the last 30 years, polycrystalline Si1−x Gex (polySiGe) alloys have been studied for microelectronics, mainly for bipolar transistors and optical devices such as superlattices [1]. In the last 10 years, poly-SiGe has also been focused on MOS devices to allow deep submicron fabrication [2]. Many advantages emerge from the usage of poly-SiGe as gate electrode for MOS devices as an alternative to poly-Si and metal gate technologies. Compared to the former, the SiGe presents lower power consumption, higher boron activation, no gate depletion and lower resistivity [1,2]. Different Ge fractions in the alloy lead to the so-called engineering workfunction that eliminates the need of channel implantation to achieve the desirable threshold voltage [1,2]. The workfunction tuning also reduces the vertical electric field in the channel region, which is an important condition to improve the carrier mobility and device speed [3]. Despite the metal gate technology seems to be preferred for future sub-50 nm devices, the high-k materials needed for these devices are facing serious dificulties to integration in the present manufacturing plants. Poly-SiGe is especially attractive for the next technological nodes due its compatibility with the well-
∗
Corresponding author. Tel.: +55 19 3788 7282; fax: +55 19 3788 7888. E-mail address: [email protected] (I. Doi).
0921-5107/$ – see front matter © 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.mseb.2005.08.060
established poly-Si deposition steps and Si-based dielectrics (SiO2 and SiON) and because it can be used in both p- and n-type MOS transistors. Furthermore, poly-SiGe MOS gates less than 20 nm length has already been reported in the literature. However, some dificulties are still to be solved such as those related to etching and chemical compatibilities. Poly-SiGe is soluble in hydrogen peroxide, one of the most used components in the wet cleaning steps while the GeO2 is water soluble, what makes oxidation onto the SiGe layers a concern. Chemistry required for gate channel opening by plasma dry etch are still to be defined, despite experiments using HBr have been shown promising relatively to the anisotropic dry etch needs for the next sub-100 nm devices. The electrical characteristics of the thin films and hence, the devices, are highly affected by morphological characteristics such as grain size and surface roughness. These in turn depend on the parameters and precursor used in the deposition process. In this study, authors present electrical and morphological characterization of poly-SiGe alloy deposited in a pancake type – LPCVD system using GeH4 and SiH4 as precursors gases. Samples were analyzed by means of ellipsometry, AFM, SEM and XRD. Very uniform and low rough samples were obtained even at high deposition rate. Rs values of poly-SiGe are much better than similar poly-Si after 31 P+ or 1 1B+ ion implantation and rapid thermal annealing at various conditions. CV and IV curves indicate the poly-SiGe films as a good material for MOS gate
R.C. Teixeira et al. / Materials Science and Engineering B 124–125 (2005) 138–142
electrode, with a leakage current of 6 mA/cm−2 (Vgs = −1 V) through SiON dielectrics (EOT = 3.2 nm). 2. Experimental Poly-SiGe thin films were deposited by LPCVD in a PMC200, pancake type, vertical reactor, onto 10 nm thermally oxidized 1 0 0, n-type, 1–10 cm single crystalline silicon substrates. Precursor gases were silane and germane in a hydrogen carrier gas flow. The CVD apparatus has been described elsewhere [4]. The poly-SiGe films were deposited in the temperature range from 500 to 750 ◦ C with 50 ◦ C steps at pressures of at 666 or 1333 Pa (5 or 10 Torr). Since Ge hardly nucleates on silicon oxide, a 30-s Si nucleation step were conducted prior to the SiGe deposition in order to reduce the incubation period. Deposition rate and uniformity of the non-doped poly-SiGe samples were extracted by ellipsometry. Surface rms roughness and grain size were evaluated by AFM (tapping mode) and SEM measurements. After the physical characterization, a second set of poly-SiGe, 200 nm thick, was deposited at 500 ◦ C/666 Pa and implanted with P or B ions in the dose range from 5E14 to 2E16 cm−2 . The implantation damage was annealed at different temperature from 500 up to 900 ◦ C during 40 s in N2 atmosphere using an RTP system. Electrical characterization was performed by means of four point probe measurements, to obtain samples sheet resistance. MOS capacitors were also fabricated with the same poly-SiGe parameter deposition described above and with poly-Si electrodes for comparison. The gate dielectric used in this samples was SiON grown by ECR electron cyclotron resonance (ECR) plasma at ambient temperature. Other growth parameter are as follows: 1000 W ECR; 5 W RF; 7 sccm N2 + 13 sccm O2 + 20 sccm Ar; different pressures were used to obtain SiON films with different thicknesses. Samples were sintered at 450 ◦ C in forming gas ambient for 30 min and no metal deposition was used. CV and IV measurents allows to extract equivalent oxide thickness (EOT) and leakage current of the high-k dieletrics. 3. Results and discussion Micro Raman spectroscopy (Fig. 1) was used to verify the composition of the obtained thin films. The Ge–Ge (∼288 cm−1 ); Ge–Si (∼406 cm−1 ) and Si–Si (∼501 cm−1 ) resonance peaks clearly indicate that thin films of the Si–Ge alloy were deposited in the temperature/pressure ranges specified above. We observe that the resonance peaks, mainly the Si–Si resonance, becomes more intense and the FWHM is reduced at higher deposition temperatures. This feature is an indicative that the film becomes more crystalline and less defective as temperature rises. No significant difference can be noticed with pressure rising from 666 to 1333 Pa for the same deposition temperature. We also notice that the relative intensity of the Ge–Ge; Ge–Si and Si–Si peaks varies, indicating a difference in the Ge contents (x). For samples deposited above 650 ◦ C, we could also notice the appearance of another peak around 420 cm−1 corre-
139
sponding to Si–Si bonding surrounded by Ge atoms [5]. Using the proposal presented by Tsang et al. [6] and Jawhari [7], we extracted the Ge fraction (x) of the deposited samples. These calculations shows that the Ge concentration rises fastly with temperature up to 30 and 37%, for samples deposited at 666 and 1333 Pa, respectively, and 600 ◦ C. Above this value, x reduces with increasing temperature, that explain the appearance of the resonance at 420 cm−1 due to the higher Si contents, but it still remains higher than 20% even for the highest pressure and temperature set used in this study. This reduction in Ge contents occurs due to the enhancement in Si deposition observed in this temperature range for the vertical LPCVD system used in this study. Temperature also gives rise to a different internal structure of the analyzed samples as pointed by XRD measurements (Fig. 2). Deposition at 750 ◦ C leads to a strong 1 1 1 preferred orientation (PO) for both 666 and 1333 Pa deposition pressure, but a different behavior is noticed for deposition temperatures below this value. While samples prepared with 666 Pa exhibit a weak 1 1 1 PO at 600 ◦ C, 1333 Pa samples exhibit a 2 2 0 PO, which rises greatly up to 700 ◦ C. Such rising for the 2 2 0 intensity is not observed in the 666 Pa samples. We also observed that there were no dual peaks on the XRD spectra that imply the alloy deposition rather than Si or Ge clusters formation [8] and confirms the Raman results. AFM and SEM measurements also show changes in the morphology of the poly-SiGe films. Grain size from 27 up to 46 nm (Fig. 3, right) were observed from AFM phase images and SEM micrographies. Some very fine boundaries were also noticed, probably related to twinning. Surface roughness analysis (Fig. 3, left) presented a simpler behaviour, related as a parabolic curve as a function of deposition temperature. Minimum roughness of 3.7 nm and 5.5 nm were found for 1333 and 666 Pa pressure deposition, respectively. The increase of the 1333 Pa pressure also leads to a less rough surface than samples obtained at 666 Pa. We believe this is due to higher amorphous contents in the film because of the higher deposition rate achieved at higher pressure. The higher deposition rate enhances the nucleation and does not allow the atoms to be properly arranged in the crystal lattice, leading to smaller grains and higher amorphous fraction, and thus to the lower surface roughness. Roughness increase with temperature is related to the thickness increase of poly-SiGe samples. However, some samples with same thickness deposited at 666 Pa presented higher rms roughness as temperature raises from 650 to 700 ◦ C, as the consequence of the others morphological characteristics effects such as grain size and PO. In general, higher grain size and 1 1 1 orientation, leads to more rough surfaces. 1 1 1 grains needs four atoms and two atomic layers for the growth process, leading to pyramidal structures, while 2 2 0 oriented grains needs just two atoms and one atomic layer. The compromise within this character, the grain size and amorphous fraction composes the surface roughness on an intricate matter, such a way we have roughness increasing with grain size for samples deposited at 666 Pa and the opposite for samples deposited at 1333 Pa. Deposition rates as high as 150 nm/min were achieved in the vertical LPCVD reactor. This rate is higher
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Fig. 1. Raman spectra of typical poly-Si (left) and poly-SiGe (right) samples.
Fig. 2. Intensity variation of the XRD peaks of poly-SiGe samples.
than obtained from literature data [9] and is related to the low activation energy observed. Ea values are 1.13 and 1.20 eV for 1333 and 666 Pa, respectively. Despite the high deposition rates, uniformity <1% were achieved. In order to assure poly-SiGe thin films feasible to deep-submicron MOS devices, a 2 2 0 PO is recommended to achieve a good dopant distribution for gate depletion reduction and a low surface roughness and grain size. The 2 2 0 orientation gives rise to films with a columnar morphology that facilitates
the diffusion of dopant species to the whole film thickness and hence diminishes the gate depletion. These characteristics are found in the temperature range from 600 to 650 ◦ C at both 666 and 1333 Pa, that reinforces the usage of low temperature for the poly-SiGe deposition and consequently a low thermal budget, minimizing the stress induced onto devices during the fabrication steps. In order to verify the electrical characteristics of the polySiGe samples, another set of 200 nm thick samples were
Fig. 3. rms surface roughness (left) and grain size (right) as a function of temperature.
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Fig. 4. Sheet resistance as a function of annealing temperature for: (A) phosphorus and (B) boron doped poly-SiGe samples. Results for poly-Si are also shown for comparison.
deposited at 500 ◦ C/666 Pa (5 Torr) onto 10 nm thermally oxidized p-type substrates. These samples were doped with 31 P+ or 1 1B+ ions at dose range from 4E15 up to 2E16 cm−2 . Ion implantation energies were chosen to allow peak dose at 100 nm (half of the film thickness). Thus, the doped samples were annealed during 40 s in nitrogen atmosphere in the temperature range from 500 to 900 ◦ C. Results of sheet resistance (Rs ) are shown in Fig. 4. Poly-Si samples with same thickness and doping conditions were also prepared for comparison. Poly-SiGe samples exhibited a much lower Rs values than poly-Si for all doping/annealing conditions. Actually, 31 P+ -doped SiGe samples presents lower R values regardless s the annealing temperature. Since Ge presents a resistivity half the value of Si, the insertion of Ge atoms in the alloy greatly enhances the Rs as observed mainly for 31 P+ -doping. Rs also presents a more linear behavior with temperature in the poly-SiGe samples. This means that a great percentage of the implantation damage is annealed even at low temperatures. This behavior is observed in the poly-Si samples only above 700 ◦ C. The higher dopant activation obtained for the SiGe samples can be noticed mainly at low implantation dose. While 5E14 cm−2 P+ ion dose poly-Si samples presented a Rs value
>1000 /sq, poly-SiGe samples prepared with the same implantation dose presented Rs of 550 /sq. The same behavior can be noticed in the 1 1B+ -doped samples (685 /sq for poly-Si samples versus 185 /sq for poly-SiGe samples). This characteristic allows the usage of lower temperatures and dose implant to obtain the same Rs values of poly-Si films. Indeed, 100 /sq gate electrode may be obtained for poly-Si implanted with 31 P+ at 2E16 cm−2 /900 ◦ C annealing and 1 1B+ at 1E16 cm−2 /900 ◦ C annealing. The same result was achieved in poly-SiGe in samples with 31 P+ at 1E16 (5E15) cm−2 at/500 (900) ◦ C annealing and 1 1B+ at 1E16 cm−2 /700 ◦ C annealing. The ability to use low thermal budgets/implantation dose is one of great importance to allow formation of shallow junctions in the next device generation. MOS capacitors were also fabricated with the same polySiGe parameter deposition described above onto a high-k SiON dielectrics grown by ECR. Similar poly-Si samples were also prepared for comparison. Samples were sintered at 450 ◦ C in forming gas ambient for 30 min and no metal deposition was used. EOT and I × V results are shown in Fig. 5. From the CV measurements we obtain EOT from 0.46 to 4.7 nm for the SiON dielectrics for the poly-SiGe samples, while the poly-Si gated devices presented no measurable CV charac-
Fig. 5. EOT (left) and I × V (right) characteristics of MOS capacitors with poly-SiGe as gate electrode and SiON as gate dielectric. IV data for poly-Si is also shown for comparison.
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teristics. We believe this is due the high temperature needed to poly-Si deposition (800 ◦ C) in the vertical system we used that degraded the dielectrics layer. On the other hand, the low temperature employed for poly-SiGe deposition has no adverse effect onto the SiON and a very good agreement with data simulated by CVC software [10] was observed in CV curves. IV measurements confirms the dielectrics degradation, as polySi capacitors presented a very high leakage current density of 8.3 A/cm2 at Vgs = −1 V, while poly-SiGe devices presented a very low leakage current of 6 mA/cm−2 in the same Vgs conditions. EOT measurents performed onto the SiGe gated capacitors also shows the referred process is suitable for very low thickness dielectrics. 4. Conclusions Poly-SiGe thin films were obtained in the vertical LPCVD system at very high deposition rates (up to 150 nm/min). Despite the high values of deposition rates, poly-SiGe thin films presented a very uniform thickness, with less than 1% variation. Samples also presented a low rms surface roughness (below 5 nm) and grain size (from 27 to 49 nm). The electrical characteristics of poly-SiGe doped samples are superior to similar poly-Si thin films for both 31 P+ and 1 1B+ doping regardless the annealing temperature employed. These features points the poly-SiGe obtained by vertical LPCVD suitable for MOS devices in the sub-100 nm range. The low thermal budget needed for poly-SiGe MOS capacitors also allows fabrication of devices onto SiON dielectrics with EOT below 1 nm.
Acknowledgments Authors acknowledge CCS staff for their help in sample preparation, the MTA and LME groups from LNLS/Brasil for the AFM and SEM micrographies, respectively, to Prof. Fernando Iikawa and Prof. Dr. Lisandro P. Cardoso, from IFGW/UNICAMP, for the micro-Raman and XRD measurements, respectively. This work has the financial support of CNPq, CAPES, FAPESP and FAEP-UNICAMP. References [1] D.L. Harame, S.J. Koester, G. Freeman, P. Cottrel, K. Rim, G. Dehlinger, D. Ahlgren, J.S. Dunn, D. Greenberg, A. Joseph, F. Anderson, J.S. Rieh, S.A.S.T. Onge, D. Coolbaugh, V. Ramacharandran, J.D. Cressler, S. Subbanna, Appl. Surf. Sci. (2004) 224. [2] Y.V. Ponomarev, P.A. Stolk, C. Salm, J. Schmitz, P.H. Woerlee, IEEE Trans. Electron Devices 47 (2000) 4. [3] W.C. Lee, B. Watson, T.J. King, C. Hu, IEEE Electron Device Lett. 20 (1999) 5. [4] R.C. Teixeira, I. Doi, J.A. Diniz, M.B.P. Zakia, J.W. Swart, Influence of ton the deposition rate of Si-poly obtained by vertical LPCVD, in: XXIV CeBRAVIC, Bauru/SP, Brazil, 2003. [5] M. Krause, H. Stiebig, R. Carius, U. Zastrow, H. Bay, H. Wagner, J. Non-Cryst. Solids 299–302 (2002) 1. [6] J.C. Tsang, P.M. Mooney, F. Dacol, J.O. Chu, J. Appl. Phys. 75 (1994) 12. [7] T. Jawhari, Analusis 28 (2000) 1. [8] L.K. Teh, W.K. Choi, L.K. Bera, W.K. Chin, Solid State Electron. 45 (2001) 1963. [9] A.E. Franke, J.M. Heck, T.J. King, R.T. Howe, J. Microelectromech. Syst. 12 (2003) 2. [10] J.H. Hauser, CVC software, North Caroline State University.