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Low-leakage analog switches for low-speed sample-and-hold circuits
Microelectronics Journal 76 (2018) 22–27
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Low-leakage analog switches for low-speed sample-and-hold circuits Jiangtao Xu, Xiaolin Shi, Zhiyuan Gao, Kaiming Nie * Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology, School of Microelectronics, Tianjin University, Tianjin 300072, China
A R T I C L E I N F O
A B S T R A C T
Index Terms: Analog switch Low leakage Low speed Sample-and-hold (S/H) circuit
In this paper, two leakage-combating analog switches for low-speed sample-and-hold (S/H) circuits are proposed. In conventional low-leakage switch, the potential drop along MOSFET is clamped to zero to suppress subthreshold leakage. Based on this switch, the proposed leakage-combating analog switches can suppress p-n junction reverse-biased leakage by clamping the potential drop along parasitic p-n junction to zero. The proposed two switches are designed and fabricated with a 0.13 μm CMOS process in a prototype chip. The experiment results illustrate that the order of magnitude of the leakages from the proposed two switches only change from 1015 A to 1012 A in the temperature range from 20 C to 120 C, which is many times lower than that of the traditional switch. FFT simulations of the S/H circuits using the proposed switches are performed. On the condition of 0.01 kS/s and 100 C, the THDs of the S/H circuits with these proposed switches are 53.98 dB, 61.09 dB respectively. The proposed switches are suitably applied in low-speed S/H circuits.
1. Introduction Sample-and-hold (S/H) circuits are important function blocks for analog signal processing. A typical S/H circuit consists of a metal-oxidesemiconductor field-effect transistor (MOSFET) used as an analog switch and a sampling capacitor. The analog switch is not ideal, since it has several leakage paths that can cause either a drop or a rise of the voltage held on the sampling capacitor. When the sampling rate is very low about 1 Hz~1 KHz, the leakage of switch will affect the S/H circuit's performance significantly. For example, the accuracy of the S/H circuit applied in pacemaker performing at the rate whose magnitude is about heart rate, is dependent on leakage current strongly [1]. In time delay integration (TDI) CMOS image sensor, the signal is stored in accumulator, which is a multiple stage S/H circuit, for a long time [2,3]. As a consequence, leakage current has a significant effect on the imaging quality of TDI CMOS image sensor. Furthermore, a low-speed circuit always has low power consumption, which means it also has the characteristic of low signal swing. Thus, the signal change caused by leakage becomes more obvious. Long clock period in low-speed circuit can induce voltage errors greater than kT/C noise [4], and this phenomenon will be even more serious when the operating temperature is much higher. A traditional analog switch is depicted in Fig. 1. The leakage components in an off-state analog switch consist of sub-threshold leakage, p-n junction reverse-biased leakage and gate leakage [5,6]. The magnitude and
relative contribution of each leakage source depend on the fabrication process strongly [7]. The most typical and convenient solution to solve this leakage issue is using a larger sampling capacitor to decrease voltage change on it caused by leakage current. Because a larger capacitor requires much stronger driver current from the previous stage, this approach is only effective at the expense of power and area. A kind of approach was proposed in Refs. [5,8] to reduce the leakage current by injecting a cancellation current, generated by a replica circuit and a feedback circuit with high-gain operational amplifier (OPA), into the circuit leaky node. However, this kind of approach has some deficiencies in the following aspects. First, the circuit structure is complex. Second, high-gain value of operational amplifier is required to ensure cancellation current precision. Third, the cancellation efficiency is limited by device mismatch. Another effective approach to reduce leakage current is to block the switch away from leaky node such as the method in Ref. [4]. It was proposed that the body terminal has been protected by body-guarded in BiCMOS or triple-well CMOS process. Nevertheless, this approach relies on fabrication process strongly, which is hard to compatible with common commercial CMOS fabrication process. In Ref. [9], a kind of leakage-combating analog switch is presented, across which the potential drop is clamped to zero by a unity-gain amplifier. However, this method cannot eliminate the p-n junction reverse-biased leakage. When the temperature ascends, the p-n junction reverse-biased leakage increases. Therefore, the
* Corresponding author. School of Microelectronics, Tianjin University, Tianjin 300072, China. E-mail address: [email protected] (K. Nie). https://doi.org/10.1016/j.mejo.2018.04.008 Received 30 August 2017; Received in revised form 31 January 2018; Accepted 8 April 2018 0026-2692/© 2018 Elsevier Ltd. All rights reserved.
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Microelectronics Journal 76 (2018) 22–27
(clkþ ¼ 1, clk- ¼ 0), it works like two TGs in series. When this switch is off (clkþ ¼ 0, clk- ¼ 1), VX is biased at the potential of Vout through a unitygain amplifier, whose gain doesn't need to be very large. The potential drop along the TG2 is clamped to about zero, and therefore the subthreshold leakage of TG2 is reduced to a negligible level. As shown in the dotted frame in Fig. 2, there are two reverse-biased p-n junctions connected to VDD and VSS respectively in the output node of TG2, so one of the p-n junction reverse-biased leakages charges the output node and the other one discharges the output node [9]. These two p-n junction reverse-biased leakages can cancel out each other in some degree, but this cancellation is sensitive to the operation temperature. When the temperature ascends, the two p-n junction reverse-biased leakages increase together. However, the increasing rate is different, the difference between the two currents becomes more distinct. Therefore, the magnitude of the total leakage current of the conventional low-leakage switch is correlated with operation temperature.
Fig. 1. Schematic of typical analog switch in S/H circuit and its leakage current components.
magnitude of the total leakage current of this switch is correlated with operation temperature. Considering the applications in low-speed S/H circuits, this paper focuses on leakage reduction in a 0.13 μm CMOS process. With gate oxide thicknesses in a typical 0.13 μm CMOS process, we can neglect gate leakage in this work compared with other leakage components [10,11]. On the basis of eliminating sub-threshold leakage, two types of switches eliminating p-n junction reverse-biased leakage are proposed in this paper. These proposed two switches can achieve much lower total leakage currents over a wide temperature range. The paper is organized as follows. Section 2 presents circuit structures of the proposed two low-leakage switches. In Section 3, the performances of the proposed two low-leakage switches are tested and simulated. Finally, the conclusion is presented in Section 4.
2.2. The proposed leakage-combating switches 2.2.1. The method based on deep-N-well to combat p-n junction reversebiased leakage On the basis of the conventional low-leakage switches, a kind of switch eliminating p-n junction reverse-biased leakage are proposed. The concept of reducing p-n junction reverse-biased leakage is to clamp the potential drop along parasitic p-n junction to zero. The proposed structure of the leakage-combating switch is illustrated in Fig. 3. For conciseness, this kind of switch is referred as TYPE-I switch henceforth. When the TYPE-I switch is on (clkþ ¼ 1, clk- ¼ 0), the TG4 is on whereas the TG5 is off. The body terminal of N2 is biased at VSS. Likewise, the body terminal of P2 is biased at VDD. The TYPE-I switch works like two conventional TGs in series. When the proposed switch is off (clkþ ¼ 0, clk- ¼ 1), Vx is biased at the potential of Vout through a unitygain amplifier. The potential drop along the TG2 composed of MOSFETs N2 and P2 is clamped to zero, which is similar to the approach presented in segment 2.1. TG4 and TG6 are off, while TG5 and TG7 are on. The body terminals of N2 and P2 are connected to output node of the unitygain amplifier. As a result, the potentials of leakage (Vout) node, body terminals of N2 and P2, the Vx node are the same. Therefore, p-n junction reverse-biased leakage can be eliminated effectively. P-type MOSFETs are fabricated in N-well (NW), therefore the body terminal could be biased at any potential higher than ground level. Whereas n-type MOSFETs are fabricated in substrate directly, and therefore the utilization of this approach confronts an obstruction which is how to bias the body terminal of N2 at other potential instead of VSS. The implementation to solve this obstruction is indicated in Fig. 4. The utilization of deep-N-well (DNW) and NW is an effective approach to insulate the body of N2. The NW need to be biased at VDD. As a result, the
2. Structures and principles of leakage-combating switches The leakage components in an off-state analog switch consist of p-n junction reverse-biased current, sub-threshold leakage and gate leakage. In this CMOS process, the gate leakage is negligible because its magnitude is too small compared to the other types of leakage. In this section, the approaches to reducing sub-threshold leakage and p-n junction reverse-biased leakage are presented. 2.1. The brief sketch of the conventional low-leakage switch The conventional low-leakage switch is illustrated in Fig. 2. It consists of three transmission gates (TGs) and an OPA. The concept of this switch is to clamp the potential drop along the MOSFETs. When this switch is on
Fig. 2. Schematic of the conventional low-leakage switch.
Fig. 3. Schematic of the TYPE-I switch. 23
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Microelectronics Journal 76 (2018) 22–27
is on. Thus, its gate voltage has to be bootstrapped. Therefore, a kind of bootstrapped switch described in Ref. [12] with the ability to handle voltage levels much below VSS is used in the proposed TYPE-II switch. The key component of the proposed switch consists of a bootstrapped structure and a p-type MOSFET indicated in dotted frame in Fig. 5, and the bootstrapped structure is shown in Fig. 6. The bootstrapped switch is controlled by clkþ. When clkþ ¼ 0, the main switch is turned off, and its gate node n3 is shorted to VDD and the gate of M4 is connected to node n3 via M7. Thus, both plates of the capacitor C2 are shorted to VDD. During this off-phase, the gate voltages of M2 and M3 are all VSS, so the voltage crossing the capacitor C1 will be a little bit lower than VDD due to M3's threshold. The off-phase ends when clkþ goes up. First, M7 is turned off and M8 on, and thus the voltage at node n5 begins to go down. Since clk2 is delayed to clkþ, node n3 is still shorted to VDD. When the voltage at node n5 goes down lower than the threshold of M8, M8 will be turned off automatically, leaving node n5 floating. As a result, a voltage appears across the capacitor C2. After a short delay, clk2 also goes up, releasing node n3. Since the voltage at node n5 is very low, M4 is turned on. Therefore, the voltage at node n3 will be pulled down by node n2. Because the capacitor C2 is floating, C2 makes n5 follow n3 with an offset large enough to keep M4 properly conducting. To lower the threshold voltage of M4, its bulk is switched to VSS during the on-phase. Finally, the gate voltage n3 of the bootstrapped switch MS equals to the voltage at node n2. Since the capacitor C1 is also floating, the VGS of MS is clamped to -VDD.
Fig. 4. Sectional drawing of n-type MOSFET N2 in the TYPE-I switch.
potential of substrate is VSS, whereas the body terminal of N2 can be biased at any potential lower than VDD level. 2.2.2. The method based on bootstrapped structure to combat p-n junction reverse-biased leakage The TYPE-I switch, which utilizes DNW, depends on process slightly. Another structure of leakage-combating switch is proposed in this segment and illustrated in Fig. 5. For conciseness, this kind of switch is referred as TYPE-II switch henceforth. The TYPE-II switch consists of TGs, an OPA and a bootstrapped switch illustrated in dotted frame. When the proposed switch is on (clkþ ¼ 1, clk- ¼ 0), it works like typical analog switch. When the proposed switch is off (clkþ ¼ 0, clk- ¼ 1), node VX is biased at the potential of Vout through a unity-gain amplifier. The potential drop along the MS is clamped to about zero, and therefore the sub-threshold leakage of MS is reduced to a negligible level. The reduction on p-n junction reverse-biased leakage uses the same concept, which clamps the potential drop along parasitic pn junction to zero. To realize this concept, one single p-type MOSFET is utilized in this structure. P-type MOSFET is processed in NW whose body is isolated, so the body and the source can be shorted to reduce p-n junction reverse-biased leakage. However, the traditional analog switch consists of a p-type MOSFET and a n-type MOSFET in parallel, which ensures complete transmission of voltage signal. But using a single p-type MOSFET will lose a threshold voltage when it transmits low voltage level signal. In order to transmit voltage signal ranging from rail to rail (i.e. VSS to VDD) through one single p-type MOSFET transistor and keep its onresistance constant and low, the gate-source voltage VGS of the p-type MOSFET transistor should be clamped to a fixed negative voltage when it
3. Experiments 3.1. Test results of the proposed two leakage-combating switches The proposed two leakage-combating switches were designed and fabricated with a 0.13 μm CMOS process. In order to compare the leakages, the conventional low-leakage switch and the traditional switch without any leakage combating technique were also fabricated and tested. The traditional switch is a TG consisted of one n-type MOSFET (L ¼ 130 nm W ¼ 500 nm) and one p-type MOSFET (L ¼ 130 nm W ¼ 1.5 μm). The sizes of key transistors in the other three low-leakage switches are illustrated in Table 1. The layout of the chip and test system PCB are illustrated in Fig. 7. The layouts of the switches are shown in the blue frames. The total areas of the conventional low-leakage switch, the TYPE-I switch, the TYPE-II switch, and the traditional switch are about 500 μm2, 780 μm2, 1140 μm2 and 15 μm2, respectively. The other parts of the layouts, which are high-gain buffers and load capacitors and connected to the switches' output nodes, are utilized to test the switches. To calculate the magnitude of leakages in these switches, the experiments were conducted as follows. The diagram of the experiment chip is shown in Fig. 8. In order to change the voltage level of the inputs of the switches, an analog 2-to-1 mux is connected to the input of each switch. When the condition of switches changes from on-state to off-state, a
Fig. 5. Schematic of the TYPE-II switch.
Fig. 6. Schematic of the bootstrapped structure. 24
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Microelectronics Journal 76 (2018) 22–27
Table 1 The sizes of key transistors in the conventional low-leakage switch, the TYPE-I switch and the TYPE-II switch. Conventional lowleakage switch N1 P1 N2 P2 N3 P3 –
L ¼ 130 nm W ¼ 500 nm L ¼ 130 nm W ¼ 1.5 μm L ¼ 130 nm W ¼ 500 nm L ¼ 130 nm W ¼ 1.5 μm L ¼ 130 nm W ¼ 200 nm L ¼ 130 nm W ¼ 200 nm –
TYPE-I switch N1 P1 N2 P2 N3 P3 N4-N7, P4-P7
TYPE-II switch L ¼ 130 nm W ¼ 500 nm L ¼ 130 nm W ¼ 1.5 μm L ¼ 130 nm W ¼ 500 nm L ¼ 130 nm W ¼ 1.5 μm L ¼ 130 nm W ¼ 200 nm L ¼ 130 nm W ¼ 200 nm L ¼ 130 nm W ¼ 200 nm
N1 P1 N2 P2 M1-M9, M11, MS M10, M12 –
L ¼ 130 nm W ¼ 500 nm L ¼ 130 nm W ¼ 1.5 μm L ¼ 130 nm W ¼ 200 nm L ¼ 130 nm W ¼ 200 nm L ¼ 130 nm W ¼ 866 nm L ¼ 130 nm W ¼ 743 nm –
potential change can be formed. When clkþ ¼ 1, all the switches are on and the voltages of Vin nodes are Von. The sampling capacitors CS store the voltages of Vin nodes as Von. When clkþ ¼ 0, all the switches are off, the voltages of Vin nodes are Voff. The charge stored in CS leaks to power source or Vin nodes due to p-n junction leakage and sub-threshold leakage. The voltage of Vout node of each switch was sampled by one off-chip 12-bit ADC at a sampling rate of 250 KHz The input range of this ADC is 3.3 V in this experimental system. Then, the relationship between the voltage of Vout and the sampling time is derived for each switch, which is shown in Fig. 9. Based on these curves, slopes (ΔVout/Δt) can be calculated by linear fitting. The leakage current Ilkg can be calculated through slope (ΔVout/Δt) and sampling capacitor Cs by Ilkg ¼
Fig. 8. The schematic of the experiment chip.
The leakages can be calculated by the above experiments. To obtain the temperature characteristics of the switches, the above experiments were conducted in different temperature. Fig. 10 illustrates the leakage currents under the temperature range from 20 C to 120 C. The leakage of the TYPE-I switch changes from 10.24 fA to 2.06 pA. The leakage of the TYPE-II switch changes from 0.4 fA to 1.4 pA. The leakage of the conventional low-leakage switch changes from 302 fA to 188 pA. The leakage of the traditional switch changes from 417 fA to 122 pA. The order of magnitude of the leakages from the proposed two switches are many times lower than that of the traditional switch in the temperature range from 20 C to 120 C. On the contrary, the order of magnitude of
ΔQ Cs ⋅ΔVout ¼ Δt Δt
where Cs is 1.5 pF.
Fig. 7. The pictures of (a) the layout of the chip (b) test system PCB. 25
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Fig. 11. The schematic of S/H circuit in the FFT simulation and the position of low-leakage switch. Fig. 9. The experimental result of the change of Vout with sampling time.
Table 2 Comparison of (a) the conventional low-leakage switch (b) the TYPE-I switch and (c) the TYPE-II switch 1024-point FFT plots at 27 C.
the leakage from the conventional low-leakage switch is about 1014 A from 20 C to 50 C. While the operation temperature is above 50 C, the leakage-combating mechanism of the conventional low-leakage switch became invalid. The order of magnitude of the leakage increases with temperature sharply and is similar with that of the traditional switch.
Sampling Rate(KS/s) (a) 0.01 0.1 1 10 (b) 0.01 0.1 1 10 (c) 0.01 0.1 1 10
3.2. Simulation results Post-layout netlists of the conventional low-leakage switch and the proposed two switches with a 0.13 μm CMOS process were simulated in Cadence Spectre. The performances of the S/H circuits with the conventional low-leakage switch and the proposed two switches are simulated at 27 C and 100 C, respectively. The schematic and the position of low-leakage switch are illustrated in Fig. 11. The leakage sensitive node is shown in the dotted frame. Table 2 and Table 3 show the simulated 1024-point FFT results for a VPP ¼ 1.5 V sinusoidal input signal, sampled by the S/H circuit at 0.01 kS/s, 0.1 kS/s, 1 kS/s and 10 kS/s sampling rate at 27 C and 100 C. When the temperature is 27 C, the performance parameters remain stable in the sampling rate range from 10 Hz to 10 KHz. The total harmonic distortions (THDs) of the S/H circuits with the conventional lowleakage switch and the proposed two switches are both low and the THDs of the S/H circuits with the proposed switches are even lower. When the temperature is 100 C, the THD of the S/H circuit with the conventional low-leakage switch is 67.76 dB at 10 KHz sampling rate. As sampling rate descends, its THD increases. When the sampling rate is drop to 10 Hz, its THD increases to 24.29 dB. The change of the THD is about 43 dB. The THDs of the S/H circuits with the proposed two switches maintain about 54 dB and 61 dB in the sampling rate range from 10 Hz to 10 KHz, respectively. The changes of the THDs are all within 1 dB. Therefore, the proposed two switches have much lower
THD (dB)
SNDR (dB)
SFDR (dB)
67.09 67.03 67.42 67.29
62.06 62 62.12 62.08
74.08 74.32 75.38 74.97
78.08 76.8 78.1 77.67
67.98 67.89 68.34 68.35
85.57 87.73 85.63 88.6
68.34 68.37 68.67 68.43
79.14 78.12 79.86 79.32 83.1 86.12 88.64 87.96
leakage in wider temperature range and could be more suitable for lowspeed S/H circuit. 3.3. Comparisons between the switches Table 4 shows comparisons between the traditional switch, the conventional low-leakage switch, the TYPE-I switch and the TYPE-II switch. The performances of each switch can be compared from three respects, such as area, process and leakage. As shown in Table 4, the areas of the conventional low-leakage switch, the proposed two switches are about 33 times, 50 times and 75 times as large as the area of the traditional switch, respectively. DNW process is necessary to fabricate the TYPE-I switch, however DNW process is supplied in most process. Therefore, it is not an issue in Table 3 Comparison of (a) the conventional low-leakage switch (b) the TYPE-I switch and (c) the TYPE-II switch 1024-point FFT plots at 100 C. Sampling Rate(KS/s) (a) 0.01 0.1 1 10 (b) 0.01 0.1 1 10 (c) 0.01 0.1 1 10
Fig. 10. The leakage currents from different switches at 20 C–120 C. 26
THD (dB)
SNDR (dB)
SFDR (dB)
24.29 46.77 63.44 67.76
24.27 45.94 59.53 62.35
27.88 55.29 71.78 75.71
54.6 53.98 54.55 53.93
54.41 53.36 54.35 53.34
57.46 56.26 57.45 56.19
61.07 61.09 61.02 61.08
60.4 60.43 60.35 60.4
64.64 64.81 64.56 64.66
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with the conventional low-leakage switch. The proposed switches are suitably applied in low-speed S/H circuit and can improve the accuracy of low-speed S/H circuit in a wide temperature range.
Table 4 Comparison between the switches.
Area (μm2) Special Process Leakage @20 C (pA) Leakage @120 C (pA)
Traditional Switch
Conventional LowLeakage Switch
Type-I Switch
Type-II Switch
15 None
500 None
780 DNW
1140 None
1.3261
0.3446
0.0676
0.032
122.5192
118.3832
2.0619
1.6347
Acknowledgement This work is supported by National Natural Science Foundation of China (NFSC) under grant (No. 61504091) and Natural Science Foundation of Tianjin under grant (No. 17JCQNJC01200). Appendix A. Supplementary data Supplementary data related to this article can be found at https://doi. org/10.1016/j.mejo.2018.04.008.
fabrication. The TYPE-II switch is independent on process, whereas the area is larger than that of the TYPE-I switch. When the temperature is 20 C, compared to the leakage of the traditional switch, the leakages of the conventional low-leakage switch and the proposed two switches decrease by 74.01%, 94.90%, and 97.59% respectively. When the temperature is 120 C, compared to the leakage of the traditional switch, the leakage of the conventional switch only decreases by 3.38%, while the leakage of the proposed two switches decrease by 98.32%, 98.67%. Above all, the proposed two switches have lower leakages than the two formers and can still achieve low leakages even at high temperature.
References [1] L.S.Y. Wong, S. Hossain, A. Ta, J. Edvinsson, D.H. Rivas, H. N€a€as, A very low-power CMOS mixed-signal IC for implantable pacemaker applications, IEEE J. Solid-State Circuits 39 (12) (Dec. 2004) 2446–2456. [2] K. Nie, S. Yao, J. Xu, J. Gao, Thirty two-stage CMOS TDI image sensor with on-chip analog accumulator, IEEE Trans. VLSI Systems 22 (4) (Apr. 2014) 951–956. [3] K. Nie, S. Yao, J. Xu, J. Gao, X. Yu, A 128-stage analog accumulator for CMOS TDI image sensor, IEEE Trans. Circuits Syst. I, Reg. Papers 61 (7) (Jul. 2014). [4] J.J. Su, K.S. Demirci, O. Brand, A low-leakage body-guarded analog switch in 0.35μm BiCMOS and its applications in low-speed switched-capacitor circuits, IEEE Trans. Circuit Syst. II, Exp. Briefs 62 (10) (Oct. 2015) 947–951. [5] M.A. Abhari, A. Abrishamifar, A novel ultra low-leakage switch for switched capacitor circuits, in: GCC Conference & Exhibition, 2009, pp. 1–4. [6] D.S. Lee, Y.H. Jun, B.S. Kong, Simultaneous reverse body and negative word-line biasing control scheme for leakage reduction of dram, IEEE J. Solid-State Circuits 46 (10) (Oct. 2011) 2396–2405. [7] Y.S. Lin, C.C. Wu, C.S. Chang, R.P. Yang, W.M. Chen, J.J. Liaw, C.H. Diaz, Leakage scaling in deep submicron CMOS for SoC, IEEE Trans. Electron. Dev. 49 (6) (Jun. 2002) 1034–1041. [8] L.S.Y. Wong, S. Hossain, A. Walker, Leakage current cancellation technique for low power switched-capacitor circuits, in: Proceedings of International Symposium on Low Power Electronics and Design, 2001, pp. 310–315. [9] L. Zou, J. Pathrose, K.T.C. Chai, M. Je, Sample-and-hold circuit with dynamic switch leakage compensation, Electron. Lett. 49 (21) (Oct. 2013) 1323–1325. [10] S.H. Lo, D.A. Buchanan, Y. Taur, Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides, IBM J. Res. Dev. 43 (3) (May. 1999) 327–337. [11] T. Yuan, E.J. Nowak, CMOS devices below 0.1 μm: how high will performance go?, in: Proc. IEDM Tech. Dig, 1997, pp. 215–218. [12] M.E. Waltari, et al., in: Circuit Techniques for Low-voltage and High-speed A/D Converters, Springer US, 2002.
4. Conclusion Two leakage-combating analog switches have been proposed in this paper, which reduce sub-threshold leakage and p-n junction reversebiased leakage effectively by clamping the potential drop along MOSFET and parasitic p-n junction to zero, respectively. Both of the TYPE-I switch and the TYPE-II switch are the embodiments of the proposed switches, which are fabricated with a 0.13 μm CMOS process. The test results show that the order of magnitude of the proposed two switches' leakage currents can all be reduced to 1014 A at 20 C, which is 10 times lower than that of the conventional low-leakage switch. When the operation temperature rises up to 120 C, the leakages of the proposed two switches are 100 times lower than that of the conventional lowleakage switch. 1024-point FFT analysis of the S/H circuits adopting the conventional low-leakage switch and the proposed two switches are conducted respectively. The results show that the S/H circuits with the proposed two switches all have a better THD compared to the S/H circuit
27
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Low-leakage analog switches for low-speed sample-and-hold circuits Jiangtao Xu, Xiaolin Shi, Zhiyuan Gao, Kaiming Nie * Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology, School of Microelectronics, Tianjin University, Tianjin 300072, China
A R T I C L E I N F O
A B S T R A C T
Index Terms: Analog switch Low leakage Low speed Sample-and-hold (S/H) circuit
In this paper, two leakage-combating analog switches for low-speed sample-and-hold (S/H) circuits are proposed. In conventional low-leakage switch, the potential drop along MOSFET is clamped to zero to suppress subthreshold leakage. Based on this switch, the proposed leakage-combating analog switches can suppress p-n junction reverse-biased leakage by clamping the potential drop along parasitic p-n junction to zero. The proposed two switches are designed and fabricated with a 0.13 μm CMOS process in a prototype chip. The experiment results illustrate that the order of magnitude of the leakages from the proposed two switches only change from 1015 A to 1012 A in the temperature range from 20 C to 120 C, which is many times lower than that of the traditional switch. FFT simulations of the S/H circuits using the proposed switches are performed. On the condition of 0.01 kS/s and 100 C, the THDs of the S/H circuits with these proposed switches are 53.98 dB, 61.09 dB respectively. The proposed switches are suitably applied in low-speed S/H circuits.
1. Introduction Sample-and-hold (S/H) circuits are important function blocks for analog signal processing. A typical S/H circuit consists of a metal-oxidesemiconductor field-effect transistor (MOSFET) used as an analog switch and a sampling capacitor. The analog switch is not ideal, since it has several leakage paths that can cause either a drop or a rise of the voltage held on the sampling capacitor. When the sampling rate is very low about 1 Hz~1 KHz, the leakage of switch will affect the S/H circuit's performance significantly. For example, the accuracy of the S/H circuit applied in pacemaker performing at the rate whose magnitude is about heart rate, is dependent on leakage current strongly [1]. In time delay integration (TDI) CMOS image sensor, the signal is stored in accumulator, which is a multiple stage S/H circuit, for a long time [2,3]. As a consequence, leakage current has a significant effect on the imaging quality of TDI CMOS image sensor. Furthermore, a low-speed circuit always has low power consumption, which means it also has the characteristic of low signal swing. Thus, the signal change caused by leakage becomes more obvious. Long clock period in low-speed circuit can induce voltage errors greater than kT/C noise [4], and this phenomenon will be even more serious when the operating temperature is much higher. A traditional analog switch is depicted in Fig. 1. The leakage components in an off-state analog switch consist of sub-threshold leakage, p-n junction reverse-biased leakage and gate leakage [5,6]. The magnitude and
relative contribution of each leakage source depend on the fabrication process strongly [7]. The most typical and convenient solution to solve this leakage issue is using a larger sampling capacitor to decrease voltage change on it caused by leakage current. Because a larger capacitor requires much stronger driver current from the previous stage, this approach is only effective at the expense of power and area. A kind of approach was proposed in Refs. [5,8] to reduce the leakage current by injecting a cancellation current, generated by a replica circuit and a feedback circuit with high-gain operational amplifier (OPA), into the circuit leaky node. However, this kind of approach has some deficiencies in the following aspects. First, the circuit structure is complex. Second, high-gain value of operational amplifier is required to ensure cancellation current precision. Third, the cancellation efficiency is limited by device mismatch. Another effective approach to reduce leakage current is to block the switch away from leaky node such as the method in Ref. [4]. It was proposed that the body terminal has been protected by body-guarded in BiCMOS or triple-well CMOS process. Nevertheless, this approach relies on fabrication process strongly, which is hard to compatible with common commercial CMOS fabrication process. In Ref. [9], a kind of leakage-combating analog switch is presented, across which the potential drop is clamped to zero by a unity-gain amplifier. However, this method cannot eliminate the p-n junction reverse-biased leakage. When the temperature ascends, the p-n junction reverse-biased leakage increases. Therefore, the
* Corresponding author. School of Microelectronics, Tianjin University, Tianjin 300072, China. E-mail address: [email protected] (K. Nie). https://doi.org/10.1016/j.mejo.2018.04.008 Received 30 August 2017; Received in revised form 31 January 2018; Accepted 8 April 2018 0026-2692/© 2018 Elsevier Ltd. All rights reserved.
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(clkþ ¼ 1, clk- ¼ 0), it works like two TGs in series. When this switch is off (clkþ ¼ 0, clk- ¼ 1), VX is biased at the potential of Vout through a unitygain amplifier, whose gain doesn't need to be very large. The potential drop along the TG2 is clamped to about zero, and therefore the subthreshold leakage of TG2 is reduced to a negligible level. As shown in the dotted frame in Fig. 2, there are two reverse-biased p-n junctions connected to VDD and VSS respectively in the output node of TG2, so one of the p-n junction reverse-biased leakages charges the output node and the other one discharges the output node [9]. These two p-n junction reverse-biased leakages can cancel out each other in some degree, but this cancellation is sensitive to the operation temperature. When the temperature ascends, the two p-n junction reverse-biased leakages increase together. However, the increasing rate is different, the difference between the two currents becomes more distinct. Therefore, the magnitude of the total leakage current of the conventional low-leakage switch is correlated with operation temperature.
Fig. 1. Schematic of typical analog switch in S/H circuit and its leakage current components.
magnitude of the total leakage current of this switch is correlated with operation temperature. Considering the applications in low-speed S/H circuits, this paper focuses on leakage reduction in a 0.13 μm CMOS process. With gate oxide thicknesses in a typical 0.13 μm CMOS process, we can neglect gate leakage in this work compared with other leakage components [10,11]. On the basis of eliminating sub-threshold leakage, two types of switches eliminating p-n junction reverse-biased leakage are proposed in this paper. These proposed two switches can achieve much lower total leakage currents over a wide temperature range. The paper is organized as follows. Section 2 presents circuit structures of the proposed two low-leakage switches. In Section 3, the performances of the proposed two low-leakage switches are tested and simulated. Finally, the conclusion is presented in Section 4.
2.2. The proposed leakage-combating switches 2.2.1. The method based on deep-N-well to combat p-n junction reversebiased leakage On the basis of the conventional low-leakage switches, a kind of switch eliminating p-n junction reverse-biased leakage are proposed. The concept of reducing p-n junction reverse-biased leakage is to clamp the potential drop along parasitic p-n junction to zero. The proposed structure of the leakage-combating switch is illustrated in Fig. 3. For conciseness, this kind of switch is referred as TYPE-I switch henceforth. When the TYPE-I switch is on (clkþ ¼ 1, clk- ¼ 0), the TG4 is on whereas the TG5 is off. The body terminal of N2 is biased at VSS. Likewise, the body terminal of P2 is biased at VDD. The TYPE-I switch works like two conventional TGs in series. When the proposed switch is off (clkþ ¼ 0, clk- ¼ 1), Vx is biased at the potential of Vout through a unitygain amplifier. The potential drop along the TG2 composed of MOSFETs N2 and P2 is clamped to zero, which is similar to the approach presented in segment 2.1. TG4 and TG6 are off, while TG5 and TG7 are on. The body terminals of N2 and P2 are connected to output node of the unitygain amplifier. As a result, the potentials of leakage (Vout) node, body terminals of N2 and P2, the Vx node are the same. Therefore, p-n junction reverse-biased leakage can be eliminated effectively. P-type MOSFETs are fabricated in N-well (NW), therefore the body terminal could be biased at any potential higher than ground level. Whereas n-type MOSFETs are fabricated in substrate directly, and therefore the utilization of this approach confronts an obstruction which is how to bias the body terminal of N2 at other potential instead of VSS. The implementation to solve this obstruction is indicated in Fig. 4. The utilization of deep-N-well (DNW) and NW is an effective approach to insulate the body of N2. The NW need to be biased at VDD. As a result, the
2. Structures and principles of leakage-combating switches The leakage components in an off-state analog switch consist of p-n junction reverse-biased current, sub-threshold leakage and gate leakage. In this CMOS process, the gate leakage is negligible because its magnitude is too small compared to the other types of leakage. In this section, the approaches to reducing sub-threshold leakage and p-n junction reverse-biased leakage are presented. 2.1. The brief sketch of the conventional low-leakage switch The conventional low-leakage switch is illustrated in Fig. 2. It consists of three transmission gates (TGs) and an OPA. The concept of this switch is to clamp the potential drop along the MOSFETs. When this switch is on
Fig. 2. Schematic of the conventional low-leakage switch.
Fig. 3. Schematic of the TYPE-I switch. 23
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is on. Thus, its gate voltage has to be bootstrapped. Therefore, a kind of bootstrapped switch described in Ref. [12] with the ability to handle voltage levels much below VSS is used in the proposed TYPE-II switch. The key component of the proposed switch consists of a bootstrapped structure and a p-type MOSFET indicated in dotted frame in Fig. 5, and the bootstrapped structure is shown in Fig. 6. The bootstrapped switch is controlled by clkþ. When clkþ ¼ 0, the main switch is turned off, and its gate node n3 is shorted to VDD and the gate of M4 is connected to node n3 via M7. Thus, both plates of the capacitor C2 are shorted to VDD. During this off-phase, the gate voltages of M2 and M3 are all VSS, so the voltage crossing the capacitor C1 will be a little bit lower than VDD due to M3's threshold. The off-phase ends when clkþ goes up. First, M7 is turned off and M8 on, and thus the voltage at node n5 begins to go down. Since clk2 is delayed to clkþ, node n3 is still shorted to VDD. When the voltage at node n5 goes down lower than the threshold of M8, M8 will be turned off automatically, leaving node n5 floating. As a result, a voltage appears across the capacitor C2. After a short delay, clk2 also goes up, releasing node n3. Since the voltage at node n5 is very low, M4 is turned on. Therefore, the voltage at node n3 will be pulled down by node n2. Because the capacitor C2 is floating, C2 makes n5 follow n3 with an offset large enough to keep M4 properly conducting. To lower the threshold voltage of M4, its bulk is switched to VSS during the on-phase. Finally, the gate voltage n3 of the bootstrapped switch MS equals to the voltage at node n2. Since the capacitor C1 is also floating, the VGS of MS is clamped to -VDD.
Fig. 4. Sectional drawing of n-type MOSFET N2 in the TYPE-I switch.
potential of substrate is VSS, whereas the body terminal of N2 can be biased at any potential lower than VDD level. 2.2.2. The method based on bootstrapped structure to combat p-n junction reverse-biased leakage The TYPE-I switch, which utilizes DNW, depends on process slightly. Another structure of leakage-combating switch is proposed in this segment and illustrated in Fig. 5. For conciseness, this kind of switch is referred as TYPE-II switch henceforth. The TYPE-II switch consists of TGs, an OPA and a bootstrapped switch illustrated in dotted frame. When the proposed switch is on (clkþ ¼ 1, clk- ¼ 0), it works like typical analog switch. When the proposed switch is off (clkþ ¼ 0, clk- ¼ 1), node VX is biased at the potential of Vout through a unity-gain amplifier. The potential drop along the MS is clamped to about zero, and therefore the sub-threshold leakage of MS is reduced to a negligible level. The reduction on p-n junction reverse-biased leakage uses the same concept, which clamps the potential drop along parasitic pn junction to zero. To realize this concept, one single p-type MOSFET is utilized in this structure. P-type MOSFET is processed in NW whose body is isolated, so the body and the source can be shorted to reduce p-n junction reverse-biased leakage. However, the traditional analog switch consists of a p-type MOSFET and a n-type MOSFET in parallel, which ensures complete transmission of voltage signal. But using a single p-type MOSFET will lose a threshold voltage when it transmits low voltage level signal. In order to transmit voltage signal ranging from rail to rail (i.e. VSS to VDD) through one single p-type MOSFET transistor and keep its onresistance constant and low, the gate-source voltage VGS of the p-type MOSFET transistor should be clamped to a fixed negative voltage when it
3. Experiments 3.1. Test results of the proposed two leakage-combating switches The proposed two leakage-combating switches were designed and fabricated with a 0.13 μm CMOS process. In order to compare the leakages, the conventional low-leakage switch and the traditional switch without any leakage combating technique were also fabricated and tested. The traditional switch is a TG consisted of one n-type MOSFET (L ¼ 130 nm W ¼ 500 nm) and one p-type MOSFET (L ¼ 130 nm W ¼ 1.5 μm). The sizes of key transistors in the other three low-leakage switches are illustrated in Table 1. The layout of the chip and test system PCB are illustrated in Fig. 7. The layouts of the switches are shown in the blue frames. The total areas of the conventional low-leakage switch, the TYPE-I switch, the TYPE-II switch, and the traditional switch are about 500 μm2, 780 μm2, 1140 μm2 and 15 μm2, respectively. The other parts of the layouts, which are high-gain buffers and load capacitors and connected to the switches' output nodes, are utilized to test the switches. To calculate the magnitude of leakages in these switches, the experiments were conducted as follows. The diagram of the experiment chip is shown in Fig. 8. In order to change the voltage level of the inputs of the switches, an analog 2-to-1 mux is connected to the input of each switch. When the condition of switches changes from on-state to off-state, a
Fig. 5. Schematic of the TYPE-II switch.
Fig. 6. Schematic of the bootstrapped structure. 24
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Table 1 The sizes of key transistors in the conventional low-leakage switch, the TYPE-I switch and the TYPE-II switch. Conventional lowleakage switch N1 P1 N2 P2 N3 P3 –
L ¼ 130 nm W ¼ 500 nm L ¼ 130 nm W ¼ 1.5 μm L ¼ 130 nm W ¼ 500 nm L ¼ 130 nm W ¼ 1.5 μm L ¼ 130 nm W ¼ 200 nm L ¼ 130 nm W ¼ 200 nm –
TYPE-I switch N1 P1 N2 P2 N3 P3 N4-N7, P4-P7
TYPE-II switch L ¼ 130 nm W ¼ 500 nm L ¼ 130 nm W ¼ 1.5 μm L ¼ 130 nm W ¼ 500 nm L ¼ 130 nm W ¼ 1.5 μm L ¼ 130 nm W ¼ 200 nm L ¼ 130 nm W ¼ 200 nm L ¼ 130 nm W ¼ 200 nm
N1 P1 N2 P2 M1-M9, M11, MS M10, M12 –
L ¼ 130 nm W ¼ 500 nm L ¼ 130 nm W ¼ 1.5 μm L ¼ 130 nm W ¼ 200 nm L ¼ 130 nm W ¼ 200 nm L ¼ 130 nm W ¼ 866 nm L ¼ 130 nm W ¼ 743 nm –
potential change can be formed. When clkþ ¼ 1, all the switches are on and the voltages of Vin nodes are Von. The sampling capacitors CS store the voltages of Vin nodes as Von. When clkþ ¼ 0, all the switches are off, the voltages of Vin nodes are Voff. The charge stored in CS leaks to power source or Vin nodes due to p-n junction leakage and sub-threshold leakage. The voltage of Vout node of each switch was sampled by one off-chip 12-bit ADC at a sampling rate of 250 KHz The input range of this ADC is 3.3 V in this experimental system. Then, the relationship between the voltage of Vout and the sampling time is derived for each switch, which is shown in Fig. 9. Based on these curves, slopes (ΔVout/Δt) can be calculated by linear fitting. The leakage current Ilkg can be calculated through slope (ΔVout/Δt) and sampling capacitor Cs by Ilkg ¼
Fig. 8. The schematic of the experiment chip.
The leakages can be calculated by the above experiments. To obtain the temperature characteristics of the switches, the above experiments were conducted in different temperature. Fig. 10 illustrates the leakage currents under the temperature range from 20 C to 120 C. The leakage of the TYPE-I switch changes from 10.24 fA to 2.06 pA. The leakage of the TYPE-II switch changes from 0.4 fA to 1.4 pA. The leakage of the conventional low-leakage switch changes from 302 fA to 188 pA. The leakage of the traditional switch changes from 417 fA to 122 pA. The order of magnitude of the leakages from the proposed two switches are many times lower than that of the traditional switch in the temperature range from 20 C to 120 C. On the contrary, the order of magnitude of
ΔQ Cs ⋅ΔVout ¼ Δt Δt
where Cs is 1.5 pF.
Fig. 7. The pictures of (a) the layout of the chip (b) test system PCB. 25
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Fig. 11. The schematic of S/H circuit in the FFT simulation and the position of low-leakage switch. Fig. 9. The experimental result of the change of Vout with sampling time.
Table 2 Comparison of (a) the conventional low-leakage switch (b) the TYPE-I switch and (c) the TYPE-II switch 1024-point FFT plots at 27 C.
the leakage from the conventional low-leakage switch is about 1014 A from 20 C to 50 C. While the operation temperature is above 50 C, the leakage-combating mechanism of the conventional low-leakage switch became invalid. The order of magnitude of the leakage increases with temperature sharply and is similar with that of the traditional switch.
Sampling Rate(KS/s) (a) 0.01 0.1 1 10 (b) 0.01 0.1 1 10 (c) 0.01 0.1 1 10
3.2. Simulation results Post-layout netlists of the conventional low-leakage switch and the proposed two switches with a 0.13 μm CMOS process were simulated in Cadence Spectre. The performances of the S/H circuits with the conventional low-leakage switch and the proposed two switches are simulated at 27 C and 100 C, respectively. The schematic and the position of low-leakage switch are illustrated in Fig. 11. The leakage sensitive node is shown in the dotted frame. Table 2 and Table 3 show the simulated 1024-point FFT results for a VPP ¼ 1.5 V sinusoidal input signal, sampled by the S/H circuit at 0.01 kS/s, 0.1 kS/s, 1 kS/s and 10 kS/s sampling rate at 27 C and 100 C. When the temperature is 27 C, the performance parameters remain stable in the sampling rate range from 10 Hz to 10 KHz. The total harmonic distortions (THDs) of the S/H circuits with the conventional lowleakage switch and the proposed two switches are both low and the THDs of the S/H circuits with the proposed switches are even lower. When the temperature is 100 C, the THD of the S/H circuit with the conventional low-leakage switch is 67.76 dB at 10 KHz sampling rate. As sampling rate descends, its THD increases. When the sampling rate is drop to 10 Hz, its THD increases to 24.29 dB. The change of the THD is about 43 dB. The THDs of the S/H circuits with the proposed two switches maintain about 54 dB and 61 dB in the sampling rate range from 10 Hz to 10 KHz, respectively. The changes of the THDs are all within 1 dB. Therefore, the proposed two switches have much lower
THD (dB)
SNDR (dB)
SFDR (dB)
67.09 67.03 67.42 67.29
62.06 62 62.12 62.08
74.08 74.32 75.38 74.97
78.08 76.8 78.1 77.67
67.98 67.89 68.34 68.35
85.57 87.73 85.63 88.6
68.34 68.37 68.67 68.43
79.14 78.12 79.86 79.32 83.1 86.12 88.64 87.96
leakage in wider temperature range and could be more suitable for lowspeed S/H circuit. 3.3. Comparisons between the switches Table 4 shows comparisons between the traditional switch, the conventional low-leakage switch, the TYPE-I switch and the TYPE-II switch. The performances of each switch can be compared from three respects, such as area, process and leakage. As shown in Table 4, the areas of the conventional low-leakage switch, the proposed two switches are about 33 times, 50 times and 75 times as large as the area of the traditional switch, respectively. DNW process is necessary to fabricate the TYPE-I switch, however DNW process is supplied in most process. Therefore, it is not an issue in Table 3 Comparison of (a) the conventional low-leakage switch (b) the TYPE-I switch and (c) the TYPE-II switch 1024-point FFT plots at 100 C. Sampling Rate(KS/s) (a) 0.01 0.1 1 10 (b) 0.01 0.1 1 10 (c) 0.01 0.1 1 10
Fig. 10. The leakage currents from different switches at 20 C–120 C. 26
THD (dB)
SNDR (dB)
SFDR (dB)
24.29 46.77 63.44 67.76
24.27 45.94 59.53 62.35
27.88 55.29 71.78 75.71
54.6 53.98 54.55 53.93
54.41 53.36 54.35 53.34
57.46 56.26 57.45 56.19
61.07 61.09 61.02 61.08
60.4 60.43 60.35 60.4
64.64 64.81 64.56 64.66
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with the conventional low-leakage switch. The proposed switches are suitably applied in low-speed S/H circuit and can improve the accuracy of low-speed S/H circuit in a wide temperature range.
Table 4 Comparison between the switches.
Area (μm2) Special Process Leakage @20 C (pA) Leakage @120 C (pA)
Traditional Switch
Conventional LowLeakage Switch
Type-I Switch
Type-II Switch
15 None
500 None
780 DNW
1140 None
1.3261
0.3446
0.0676
0.032
122.5192
118.3832
2.0619
1.6347
Acknowledgement This work is supported by National Natural Science Foundation of China (NFSC) under grant (No. 61504091) and Natural Science Foundation of Tianjin under grant (No. 17JCQNJC01200). Appendix A. Supplementary data Supplementary data related to this article can be found at https://doi. org/10.1016/j.mejo.2018.04.008.
fabrication. The TYPE-II switch is independent on process, whereas the area is larger than that of the TYPE-I switch. When the temperature is 20 C, compared to the leakage of the traditional switch, the leakages of the conventional low-leakage switch and the proposed two switches decrease by 74.01%, 94.90%, and 97.59% respectively. When the temperature is 120 C, compared to the leakage of the traditional switch, the leakage of the conventional switch only decreases by 3.38%, while the leakage of the proposed two switches decrease by 98.32%, 98.67%. Above all, the proposed two switches have lower leakages than the two formers and can still achieve low leakages even at high temperature.
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4. Conclusion Two leakage-combating analog switches have been proposed in this paper, which reduce sub-threshold leakage and p-n junction reversebiased leakage effectively by clamping the potential drop along MOSFET and parasitic p-n junction to zero, respectively. Both of the TYPE-I switch and the TYPE-II switch are the embodiments of the proposed switches, which are fabricated with a 0.13 μm CMOS process. The test results show that the order of magnitude of the proposed two switches' leakage currents can all be reduced to 1014 A at 20 C, which is 10 times lower than that of the conventional low-leakage switch. When the operation temperature rises up to 120 C, the leakages of the proposed two switches are 100 times lower than that of the conventional lowleakage switch. 1024-point FFT analysis of the S/H circuits adopting the conventional low-leakage switch and the proposed two switches are conducted respectively. The results show that the S/H circuits with the proposed two switches all have a better THD compared to the S/H circuit
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