- Email: [email protected]
Low noise electronics for the CLEO III silicon detector
Nuclear Instruments
and Methods
in Physics
Research
A 383 (1996)
189-192
NUCLUR
INSTRUMENTS &METNoDS IN PWSICS ELSEVIER
Low noise electronics
for the CLEO III silicon detector
H. Kagan”‘“, J. Alexanderb, A. Beanc, C. Bebekb, G. Brandenburgd, C. Darling”, J. Duboscq”, J. Faste, A. Folandb, K.K. Gana, P. Hopmanb, R. Kass”, P. Kimb, N. Menon’, D. Miller”, B. Nematif, J. Oliverd, C. Rush”, I. Shipsey’, P. Skubicf, M.B. Spencera, C. Uhl”, C. Wardb, R. Wilsond, M. Yurko”, M.M. Zoeller” “ThrOhio State
University,
Columbus,
OH 4X10,
USA
“Cornell University, Ithaca, NY 148_%3.USA ‘University of Kansas. Lawrence, KA 66045, USA ‘Harvard University, Cambridge, MA O-3138. USA ‘Purdue University. Lafayette. IN 47907, USA ‘University of Oklahoma, Norman, OK 73019. USA
Abstract We report here the status of the CLEO III silicon vertex detector electronics. The CLEO III silicon detector is a 4-layer barrel-style device which spans 93% of the solid angle observing the interaction region. All layers will be constructed with double-sided silicon. The innermost layer must be able to handle large singles rates associated with a detector situated near the interaction region. In order to cover the required solid angle, the outermost layer is 55 cm long and presents a large capacitive load to the front-end electronics. The electronics chain chosen to meet this challenge consists of a low noise cascade preamplifier followed by an ADC on each channel. The system issues will be described herein together with the chosen solutions, noise performance of each subsystem prototype, and expected results of the full system.
1. Introduction
The Cornell Electron Storage Ring (CESR) is presently beginning an upgrade which will yield a luminosity of 1O”7cmm2 s-’ in 1998. This will give CLEO III access to a new world of rare B decays, r decays and charm decays. Detectors which operate in this environment will have to be quite robust while still providing excellent signal to noise performance. The CLEO III silicon detector (Si3) is a 4-layer barrelstyle device which is designed to span 93% of the available solid angle. A side view of Si3 is shown in Fig. I. The Si3 detector spans the radial distance from 2.5 to 11 cm. In order to simplify the construction of this large device, all layers will be constructed with the same doublesided silicon design. The innermost layer must be able to handle large singles rates associated with a detector situated near the interaction region. The outermost layer, 55 cm long to cover the required solid angle, presents a large capacitive load to the front-end electronics. Moreover, the CLEO III overall electronics design requires that
* Corresponding author. Tel. + 1 614 292 2314, fax + 1 614 292 8261, e-mail [email protected].
there be no active clocks during data taking and a trigger latency of 1.5 p,s. These constraints together with the demand for large signal to noise (>20: 1 in all layers) push the electronics design to one without a pipeline and long shaping time. Finally to minimize the experimental deadtime the data readout should take less than 20 p.s. This essentially means that each silicon strip must be provided with its own ADC and that sparsification must be an available option. In this paper. we describe the various components of the CLEO III silicon electronics design. We also describe the measured performance of each subsystem prototype.
2. Overall design In Fig. 2 we show the block diagram of Si3. The detectors have an active area of 51.2 mm X 25.6 mm. The r+ side consists of single metal on 50 Km pitch; the z side consists of double metal on 100 pm pitch. Each side has 51 I readout strips. The details of the design may be found elsewhere in these proceedings [I]. In order to allow the detectors to cover the full solid angle, the hybrids will be mounted on the support cone. The connection from the detectors to the hybrids is
0168-9002/96/$15.00 Copyright 0 1996 Elsevier Science B.V. All rights reserved PII SO168-9002(96)00693-6
VI. ELECTRONICS/DAQ
190
H. Kugan et al. / Nucl. Instr. and Meth. in Phys. Res. A 383 (1996) 189- I92
I
Drift Chamber
Layer 4 Si, 102,26r@ Layer 3 Si, 72, l&q Layer 2 Si, 42, lOr$
Interaction Point
Fig. 1. A schematic
view of the central region of the CLEO III detector
accomplished via a Flex Circuit. This design has the added advantage of allowing the electrical and mechanical/thermal problems to be isolated from one another. The Flex Circuits are designed for the 50 pm pitch readout traces as a two-Kapton sandwich with 100 pm pitch lines per layer. Since this circuit “sees” the full detector capacitance care must be taken to minimize the noise associated with its parameters. For Si3, the series resistance is designed to be < 10 fi and the capacitance is designed to < 5 pF. The biasing and AC coupling of the detectors to the electronics is accomplished with an R/C chip. The R/C chip consists of 128 channels on 50 pm pitch. Each channel consists of a bias resistor to a high voltage bus on the input side of the device and a series capacitor to decouple the detector from the electronics. In addition, the metal traces introduce a series resistance. Since a small value of the bias resistor will add noise its value was chosen to be > 100 MR. Similarly, since the series resistance of the R/C chip “sees” the full detector capacitance (ENC -&C) the series resistance must be kept <.50fl. Finally in order to collect most of the charge, the decoupling capacitor must be large compared to the detector capacitance. This constraint pushes the R/C chip to large physical dimensions (2.5 cm long) in order to reach 125 pF capacitance in the CMOS technology used.
illustrating
the rq5 and z segmentation
of the Si3 detector.
The front-end of the electronics chain is shown in Fig. 3. It consists of a preamplifier, shaper, buffer and gain stage. The front-end is a 128 channel custom IC designed in a single poly, double metal, p-well process [2]. The design noise specification for the front-end is 125e- + 8e-/pF in order to attain the desired signal to noise on each of the 4 silicon layers. The preamp section of the front-end consists of a folded cascade with large gain (0.125 pF feedback capacitor). The preamp is isolated from the shaper with a follower and A/C coupled to the shaper with a 5 pF capacitor. Two designs of the shaper are under investigation both of which implement CR-RC shaping: a Viking-style shaper [3,4], and a Coupled-R design where CR = RC. The advantage of the Coupled-R design is a larger shaping range and more nearly semi-Gaussian shaping. The disadvantage of the Coupled-R design is excess noise from the first resistor. The front-end electronics also has a variable gain stage. By choosing the appropriate capacitor (4 to 7 pF) at the input to the gain stage, the gain may be adjusted in four steps by nearly a factor of two. This allows compensation for the difference in signal size observed at the input of the front-end electronics due to the relative size of the coupling capacitor in the R/C circuit to the detector capacitance for each layer. The final section of the front-end electronics is
191
H. Kagan et al. I Nucl. lnstr. and Meth. in Ph.w. Res. A 383 (1996) 189-192
Buffer
Shaper
Preamp
Gain Stage
A
Fig. 3. A block diagram
of the silicon front-end
the baseline subtraction circuit. This circuit samples the baseline for typically 200 l.rs before a trigger. The sampled baseline is subtracted from the signal to compensate for large baseline shifts at the ADC. The back-end of the electronics chain consists of one ADC per channel, comparator, and FIFO. This circuit was derived from the SVX2b 151. This circuit requires the input of a baseline and a signal. It takes the difference between them and integrates it and digitizes it using an &bit Wilkinson ADC. The comparators allow three modes of operation: all channels read out, only channels above a threshold read out, channels above a threshold plus their nearest neighbors read out.
3. Prototype results In Flex look met.
Table 1 we show the present status of the prototype Circuits and R/C chips. Overall the first prototypes quite good and most specifications have already been These prototypes will be used in a full detector/
Table I Prototype
results from the CLEO III Flex Circuits and R/C chips
Quality
Specification
Measured value
Flex capacitance lpF]
<5I25
2 I5 1 2 I.50 2 200 23 47
Flex series resistance [iI] Flex shorts [%I Flex breaks [ %I R/C capacitance [pF] R/C capacitance variation [pF] R/C bias resistance [Ma] R/C series resistance [fk] R/C voltage breakdown [V]
>I00 <50 loo
electronics.
electronics test. There are however a few areas of concern which are being addressed in a second prototyping round. These include the ruggedness of the Flex Circuits and the breakdown voltage of the R/C chips. In Fig. 4 we show the measured noise from the 128 channel prototype for the Coupled-R shaper as a function of shaping time and capacitive load. This circuit performs well in the shaping time range of interest. In Table 2 we show the present status of the prototype front-end and back-end electronics. All specifications have been met and these ICs are being prepared for a radiation hard run. We have used the prototype data to model the signal collection and noise in the complete system. This model includes all known noise sources as well as collection efficiencies. The results of the modeling, shown in Table 3, take into account the number of detectors per layer (I in layer I and 5 in layer 4), capacitance per detector, trace resistance, leakage current (strip and surface), flex cable capacitance and resistance, R/C coupling capacitor, bias resistor and series resistance, preamp feedback resistor, dynamic capacitance. input capacitance and I lfnoise’. The results are shown for a 2.0 l,~s shaping time under the assumption that the detectors draw I.8 nA of leakage current. Present prototype detectors draw less than 0.5 nA of leakage current per average strip before being irradiated.
’ The model defines 1lf noise by the following
equation:
where C,,, is the gate capacitance/unit area, and Wand L are the gate width and length, respectively. The values of Fk and a used for the results shown in Table 3 were FL = 0.5 X 1Om’4 V2F and cy = 1.0.
VI. ELECTRONICS/DAQ
192
H. Kagan et al. I Nucl. Instr. and Meth. in Phys. Res. A 38.1 (1996) 189-192
Table 2 Prototype
results from the CLEO III front-end
Quantity Front-end Front-end Front-end Back-end Back-end
noise at 2 ps linearity (Z-5 MIPS) range [V] range [V] linearity [%J
Table 3 Noise simulation
[%I
and back-end
electronics
Specification
Measured
125e- + 8e-/pF
I lOe_ + 8e-/pF 2 1.5 I .5
3 1.0
I .o 1
value
(in em) of the full Si3 system with a 2.0 p.s
shaping time
I noise
Layer 4 noise
Noise source
Layer
Amplifier white noise Detector trace resistance Leakage current ( I .8 nA/stripf Amplifier 1/fnoise Flex series resistance R/C series resistance R/C bias resistor
240 45 230 100 45 55 70
410 315 405 185 125 13.5 90
Total noise
375
745
‘0
ENC= 124e + 9.8 e/pF -+-ENC=113e+8.2e/pF --o--ENC= 95e+6.2eJpF 1,1,,,,,11,,1,,,,11,1*,,,,,,,,,,,,,5 10 1.5 20 25 30 35 40 C load (pF)
Moreover, we have measured the damage constant 5 nA/cm’/krad with the prototype detectors.
4. Summary
to be
and future
CLEO III has chosen a simple, low noise solution for the silicon detector which handles a long barrel design. The expected noise levels range from 375 em for layer 1 to 745 em in layer 4. The system is based on simple detectors, long shaping times, massive parallelism, and separation of the electrical and mechanical/thermal problems. The concentration in 1995 was on design and prototyping. In 1996 the full design will be completed, orders placed, and construction will begin. The construction phase will continue into 1997. At present essentially all milestones have been met.
Fig. 4. Measurements from the Coupled-R of shaping time and capacitive load.
front-end
as a function
References et al.. these Proceedings (2nd Int. Symp. on Development and Application of Semiconductor Tracking Detectors, Hiroshima, Japan, 1995) Nucl. Instr. and Meth. A 383 (1996) 98. PI The radiation soft prototypes were produced by Orbit Semiconductor Inc.. 1215 Bordeaux Drive, Sunnyvale. CA 94089, USA. [31 P Aspell et al., Nucl. Instr. and Meth. A 315 (1992) 425. [41 E. Nygard et al., Nucl. Instr. and Meth. A 301 (I991 ) 506. PI 0. Milgromme et al., presented at this Symposium (2nd Int. Symp. on Development and Application of Semiconductor Tracking Detectors. Hiroshima, Japan, I995 ).
[II P. Hopman
and Methods
in Physics
Research
A 383 (1996)
189-192
NUCLUR
INSTRUMENTS &METNoDS IN PWSICS ELSEVIER
Low noise electronics
for the CLEO III silicon detector
H. Kagan”‘“, J. Alexanderb, A. Beanc, C. Bebekb, G. Brandenburgd, C. Darling”, J. Duboscq”, J. Faste, A. Folandb, K.K. Gana, P. Hopmanb, R. Kass”, P. Kimb, N. Menon’, D. Miller”, B. Nematif, J. Oliverd, C. Rush”, I. Shipsey’, P. Skubicf, M.B. Spencera, C. Uhl”, C. Wardb, R. Wilsond, M. Yurko”, M.M. Zoeller” “ThrOhio State
University,
Columbus,
OH 4X10,
USA
“Cornell University, Ithaca, NY 148_%3.USA ‘University of Kansas. Lawrence, KA 66045, USA ‘Harvard University, Cambridge, MA O-3138. USA ‘Purdue University. Lafayette. IN 47907, USA ‘University of Oklahoma, Norman, OK 73019. USA
Abstract We report here the status of the CLEO III silicon vertex detector electronics. The CLEO III silicon detector is a 4-layer barrel-style device which spans 93% of the solid angle observing the interaction region. All layers will be constructed with double-sided silicon. The innermost layer must be able to handle large singles rates associated with a detector situated near the interaction region. In order to cover the required solid angle, the outermost layer is 55 cm long and presents a large capacitive load to the front-end electronics. The electronics chain chosen to meet this challenge consists of a low noise cascade preamplifier followed by an ADC on each channel. The system issues will be described herein together with the chosen solutions, noise performance of each subsystem prototype, and expected results of the full system.
1. Introduction
The Cornell Electron Storage Ring (CESR) is presently beginning an upgrade which will yield a luminosity of 1O”7cmm2 s-’ in 1998. This will give CLEO III access to a new world of rare B decays, r decays and charm decays. Detectors which operate in this environment will have to be quite robust while still providing excellent signal to noise performance. The CLEO III silicon detector (Si3) is a 4-layer barrelstyle device which is designed to span 93% of the available solid angle. A side view of Si3 is shown in Fig. I. The Si3 detector spans the radial distance from 2.5 to 11 cm. In order to simplify the construction of this large device, all layers will be constructed with the same doublesided silicon design. The innermost layer must be able to handle large singles rates associated with a detector situated near the interaction region. The outermost layer, 55 cm long to cover the required solid angle, presents a large capacitive load to the front-end electronics. Moreover, the CLEO III overall electronics design requires that
* Corresponding author. Tel. + 1 614 292 2314, fax + 1 614 292 8261, e-mail [email protected].
there be no active clocks during data taking and a trigger latency of 1.5 p,s. These constraints together with the demand for large signal to noise (>20: 1 in all layers) push the electronics design to one without a pipeline and long shaping time. Finally to minimize the experimental deadtime the data readout should take less than 20 p.s. This essentially means that each silicon strip must be provided with its own ADC and that sparsification must be an available option. In this paper. we describe the various components of the CLEO III silicon electronics design. We also describe the measured performance of each subsystem prototype.
2. Overall design In Fig. 2 we show the block diagram of Si3. The detectors have an active area of 51.2 mm X 25.6 mm. The r+ side consists of single metal on 50 Km pitch; the z side consists of double metal on 100 pm pitch. Each side has 51 I readout strips. The details of the design may be found elsewhere in these proceedings [I]. In order to allow the detectors to cover the full solid angle, the hybrids will be mounted on the support cone. The connection from the detectors to the hybrids is
0168-9002/96/$15.00 Copyright 0 1996 Elsevier Science B.V. All rights reserved PII SO168-9002(96)00693-6
VI. ELECTRONICS/DAQ
190
H. Kugan et al. / Nucl. Instr. and Meth. in Phys. Res. A 383 (1996) 189- I92
I
Drift Chamber
Layer 4 Si, 102,26r@ Layer 3 Si, 72, l&q Layer 2 Si, 42, lOr$
Interaction Point
Fig. 1. A schematic
view of the central region of the CLEO III detector
accomplished via a Flex Circuit. This design has the added advantage of allowing the electrical and mechanical/thermal problems to be isolated from one another. The Flex Circuits are designed for the 50 pm pitch readout traces as a two-Kapton sandwich with 100 pm pitch lines per layer. Since this circuit “sees” the full detector capacitance care must be taken to minimize the noise associated with its parameters. For Si3, the series resistance is designed to be < 10 fi and the capacitance is designed to < 5 pF. The biasing and AC coupling of the detectors to the electronics is accomplished with an R/C chip. The R/C chip consists of 128 channels on 50 pm pitch. Each channel consists of a bias resistor to a high voltage bus on the input side of the device and a series capacitor to decouple the detector from the electronics. In addition, the metal traces introduce a series resistance. Since a small value of the bias resistor will add noise its value was chosen to be > 100 MR. Similarly, since the series resistance of the R/C chip “sees” the full detector capacitance (ENC -&C) the series resistance must be kept <.50fl. Finally in order to collect most of the charge, the decoupling capacitor must be large compared to the detector capacitance. This constraint pushes the R/C chip to large physical dimensions (2.5 cm long) in order to reach 125 pF capacitance in the CMOS technology used.
illustrating
the rq5 and z segmentation
of the Si3 detector.
The front-end of the electronics chain is shown in Fig. 3. It consists of a preamplifier, shaper, buffer and gain stage. The front-end is a 128 channel custom IC designed in a single poly, double metal, p-well process [2]. The design noise specification for the front-end is 125e- + 8e-/pF in order to attain the desired signal to noise on each of the 4 silicon layers. The preamp section of the front-end consists of a folded cascade with large gain (0.125 pF feedback capacitor). The preamp is isolated from the shaper with a follower and A/C coupled to the shaper with a 5 pF capacitor. Two designs of the shaper are under investigation both of which implement CR-RC shaping: a Viking-style shaper [3,4], and a Coupled-R design where CR = RC. The advantage of the Coupled-R design is a larger shaping range and more nearly semi-Gaussian shaping. The disadvantage of the Coupled-R design is excess noise from the first resistor. The front-end electronics also has a variable gain stage. By choosing the appropriate capacitor (4 to 7 pF) at the input to the gain stage, the gain may be adjusted in four steps by nearly a factor of two. This allows compensation for the difference in signal size observed at the input of the front-end electronics due to the relative size of the coupling capacitor in the R/C circuit to the detector capacitance for each layer. The final section of the front-end electronics is
191
H. Kagan et al. I Nucl. lnstr. and Meth. in Ph.w. Res. A 383 (1996) 189-192
Buffer
Shaper
Preamp
Gain Stage
A
Fig. 3. A block diagram
of the silicon front-end
the baseline subtraction circuit. This circuit samples the baseline for typically 200 l.rs before a trigger. The sampled baseline is subtracted from the signal to compensate for large baseline shifts at the ADC. The back-end of the electronics chain consists of one ADC per channel, comparator, and FIFO. This circuit was derived from the SVX2b 151. This circuit requires the input of a baseline and a signal. It takes the difference between them and integrates it and digitizes it using an &bit Wilkinson ADC. The comparators allow three modes of operation: all channels read out, only channels above a threshold read out, channels above a threshold plus their nearest neighbors read out.
3. Prototype results In Flex look met.
Table 1 we show the present status of the prototype Circuits and R/C chips. Overall the first prototypes quite good and most specifications have already been These prototypes will be used in a full detector/
Table I Prototype
results from the CLEO III Flex Circuits and R/C chips
Quality
Specification
Measured value
Flex capacitance lpF]
<5
2 I5 1 2 I.50 2 200 23 47
Flex series resistance [iI] Flex shorts [%I Flex breaks [ %I R/C capacitance [pF] R/C capacitance variation [pF] R/C bias resistance [Ma] R/C series resistance [fk] R/C voltage breakdown [V]
>I00 <50 loo
electronics.
electronics test. There are however a few areas of concern which are being addressed in a second prototyping round. These include the ruggedness of the Flex Circuits and the breakdown voltage of the R/C chips. In Fig. 4 we show the measured noise from the 128 channel prototype for the Coupled-R shaper as a function of shaping time and capacitive load. This circuit performs well in the shaping time range of interest. In Table 2 we show the present status of the prototype front-end and back-end electronics. All specifications have been met and these ICs are being prepared for a radiation hard run. We have used the prototype data to model the signal collection and noise in the complete system. This model includes all known noise sources as well as collection efficiencies. The results of the modeling, shown in Table 3, take into account the number of detectors per layer (I in layer I and 5 in layer 4), capacitance per detector, trace resistance, leakage current (strip and surface), flex cable capacitance and resistance, R/C coupling capacitor, bias resistor and series resistance, preamp feedback resistor, dynamic capacitance. input capacitance and I lfnoise’. The results are shown for a 2.0 l,~s shaping time under the assumption that the detectors draw I.8 nA of leakage current. Present prototype detectors draw less than 0.5 nA of leakage current per average strip before being irradiated.
’ The model defines 1lf noise by the following
equation:
where C,,, is the gate capacitance/unit area, and Wand L are the gate width and length, respectively. The values of Fk and a used for the results shown in Table 3 were FL = 0.5 X 1Om’4 V2F and cy = 1.0.
VI. ELECTRONICS/DAQ
192
H. Kagan et al. I Nucl. Instr. and Meth. in Phys. Res. A 38.1 (1996) 189-192
Table 2 Prototype
results from the CLEO III front-end
Quantity Front-end Front-end Front-end Back-end Back-end
noise at 2 ps linearity (Z-5 MIPS) range [V] range [V] linearity [%J
Table 3 Noise simulation
[%I
and back-end
electronics
Specification
Measured
125e- + 8e-/pF
I lOe_ + 8e-/pF 2 1.5 I .5
3 1.0
I .o 1
value
(in em) of the full Si3 system with a 2.0 p.s
shaping time
I noise
Layer 4 noise
Noise source
Layer
Amplifier white noise Detector trace resistance Leakage current ( I .8 nA/stripf Amplifier 1/fnoise Flex series resistance R/C series resistance R/C bias resistor
240 45 230 100 45 55 70
410 315 405 185 125 13.5 90
Total noise
375
745
‘0
ENC= 124e + 9.8 e/pF -+-ENC=113e+8.2e/pF --o--ENC= 95e+6.2eJpF 1,1,,,,,11,,1,,,,11,1*,,,,,,,,,,,,,5 10 1.5 20 25 30 35 40 C load (pF)
Moreover, we have measured the damage constant 5 nA/cm’/krad with the prototype detectors.
4. Summary
to be
and future
CLEO III has chosen a simple, low noise solution for the silicon detector which handles a long barrel design. The expected noise levels range from 375 em for layer 1 to 745 em in layer 4. The system is based on simple detectors, long shaping times, massive parallelism, and separation of the electrical and mechanical/thermal problems. The concentration in 1995 was on design and prototyping. In 1996 the full design will be completed, orders placed, and construction will begin. The construction phase will continue into 1997. At present essentially all milestones have been met.
Fig. 4. Measurements from the Coupled-R of shaping time and capacitive load.
front-end
as a function
References et al.. these Proceedings (2nd Int. Symp. on Development and Application of Semiconductor Tracking Detectors, Hiroshima, Japan, 1995) Nucl. Instr. and Meth. A 383 (1996) 98. PI The radiation soft prototypes were produced by Orbit Semiconductor Inc.. 1215 Bordeaux Drive, Sunnyvale. CA 94089, USA. [31 P Aspell et al., Nucl. Instr. and Meth. A 315 (1992) 425. [41 E. Nygard et al., Nucl. Instr. and Meth. A 301 (I991 ) 506. PI 0. Milgromme et al., presented at this Symposium (2nd Int. Symp. on Development and Application of Semiconductor Tracking Detectors. Hiroshima, Japan, I995 ).
[II P. Hopman