Low-power subthreshold to above threshold level shifters in 90 nm and 65 nm process

Microprocessors and Microsystems 35 (2011) 1–9

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Microprocessors and Microsystems journal homepage: www.elsevier.com/locate/micpro

Low-power subthreshold to above threshold level shifters in 90 nm and 65 nm process Amir Hasanbegovic ⇑, Snorre Aunet Department of Informatics, University of Oslo, Norway

a r t i c l e

i n f o

Article history: Available online 21 November 2010 Keywords: Level shifter Low power Subthreshold operation MTCMOS Dynamic voltage scaling

a b s t r a c t In this paper we present low power level shifters in the 90 nm (general purpose) and 65 nm (low power) technology nodes capable of converting subthreshold voltage signals to above threshold voltage signals. The level shifters make use of the MTCMOS design technique which gives more design flexibility, especially in low power systems. Post layout simulations indicate static power consumption down to 1 nW and 83 pW in the 90 nm and 65 nm process respectively. Energy consumption per transition is recorded to be below 30 fJ in both processes, orders of magnitude lower then other published level shifter implementations. Propagation delay is found to be as low as 32 ns for subthreshold logic high input signals of 180 mV. The functionality of the level shifters is verified across process-, mismatch- and temperature variations between 40 °C and 150 °C. Minimum input voltage attainable while maintaining robust operation is found to be around 180 mV at operational frequencies above 1 MHz in the 90 nm process, and 350 mV at operational frequencies above 500 kHz in the 65 nm process. The level shifters employ an enable/disable feature, allowing for power saving when the level shifter is not in use. Ó 2010 Elsevier B.V. All rights reserved.

1. Introduction Recently there has been a lot of focus on low power electronics capable of maintaining acceptable performance requirements in terms of speed and power consumption. The most effective means of reducing the power consumption of an integrated circuit (IC) is by reducing the supply voltage. The reduction in supply voltage contributes to dramatic decrease in dynamic and static power consumption, however the utilization of low supply voltage has a negative impact on the speed of the circuit [1]. In order to reduce power consumption while limiting the sacrifice of speed, multiple voltage domains may be implemented on the same IC. By doing so, less critical sections of the circuit may be supplied by a low supply voltage, VDDL, while critical sections are supplied by higher supply voltages, VDDH. In order to connect the different voltage domains in an effective way, the use of level shifters for interfacing is vital for minimizing delay and power consumption. The different voltage domains may also be represented by digital logic (VDDL) interfaced with I/O buffers (VDDH) via level shifters, which is important for effective off-chip communication. Fig. 1a illustrates a typical application area for level shifters, and Fig. 1b shows the transient response of a previously fabricated level shifter1 which is based ⇑ Corresponding author. Tel.: +47 98858167. E-mail addresses: amirh@ifi.uio.no (A. Hasanbegovic), sa@ifi.uio.no (S. Aunet). Measurements anno May 12. 2010, of a level shifter fabricated in a 90 nm process from STMicroelectronics. 1

0141-9331/$ - see front matter Ó 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.micpro.2010.11.003

on a different circuit topology. For the sections of the IC where speed is of less importance, the supply voltage may be reduced down to the subthreshold region with the goal of saving as much power as possible. Subthreshold operation has the prospective to contribute with considerable power savings which may highly benefit modern portable devices. Level shifters converting subthreshold signals to above threshold signals are most likely to have transistors operating in the subthreshold region. Transistors operating in above threshold region have a supply voltage above their inherent threshold voltage jVthj. However, when the supply voltage is reduced below the threshold voltage Vdd < Vth, the transistor is considered to be operating in subthreshold region. Transistors operating in subthreshold region have exponential reduction in Ids when Vgs < Vth. IDsub is given by [2] V gs V th nV T

IDsub ¼ I0 e

  V ds 1  e VT

ð1Þ

where I0 is the drain current when Vgs < Vth

I0 ¼ l0 C ox

W ðn  1ÞV 2T L

ð2Þ

An important parameter in the subthreshold region is the subthreshold swing, which is given by

k S ¼ n lnð10Þ T q

ð3Þ

2

A. Hasanbegovic, S. Aunet / Microprocessors and Microsystems 35 (2011) 1–9

10

10 10

Log(Id)

10 10 10 10 10 10

(a) Typical application for the level shifters

Temperature dependency of subthreshold current

−4

−5

−6

−7

−8

−9

ΔVth(T) 150 degrees Celsius 104 degrees Celsius 56 degrees Celsius 8 degrees Celsius −40 degrees Celsius

−10

ΔId(T) −11

−12

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Vgs 1.4

Level shifter input Level shifter output (buffered)

Input/output voltage (V)

1.2

Fig. 2. Subthreshold swing temperature dependence in the temperature range between 40 °C and 150 °C.

1

It is also clear from Fig. 2 that the temperature dependence of Id is different for two operation regions. When Vgs < 0.6 V, the current increases with temperature, as opposed to a current decrease when Vgs > 0.6 V.

0.8 0.6 0.4

2. Conventional level shifter

0.2 0 1.5

2

2.5

3

3.5

4

4.5

5

Time (s)

5.5 -6 x 10

(b) Measured transisent response of a level shifter interfacing two voltage domains, VDDL = 160 mV and VDDH = 1.2 V Fig. 1. Typical level shifter application area, and transient response.

where n, k and q are the inverse slope in weak inversion, Boltzmann constant and electron charge respectively. A small subthreshold swing is desired since it improves the ratio between the on- and off-currents, ION and IOFF. It is apparent from Eq. (3) that the subthreshold swing is highly temperature dependent and therefore contributes to design challenges and reliability issues in circuits which employ transistors operating in the subthreshold region. This is due to carrier transport in subthreshold region being dominated by diffusion, as opposed to carrier transport being dominated by drift in above threshold region [3]. Carrier transport by diffusion is a thermal energy driven mechanism and it has been shown that the current conductivity displays exponential temperature dependence in the subthreshold region [4]. As the temperature decreases, the subthreshold swing also decreases, resulting in higher ION/IOFF ratio. However, although a small subthreshold swing is desired, a sufficiently high ION is also desired in order to achieve adequate transistor drive strength. Therefore, a decrease in temperature results in a decrease in subthreshold swing which reduces ION for a given Vgs which in turn weakens the drive strength of transistors operating at a specified supply voltage (VDDL in the case of the level shifter). This presents a problem particularly in the cases where transistors operating in subthreshold region are stacked in the same signal path as transistors operating above threshold region. In the opposite case, when the temperature increases, the drive strength of the transistors increase due to increased diffusion current. The result of increased diffusion current is an increase in subthreshold swing, reduction in threshold voltage and thereby increased ION for a given Vgs, resulting in increased leakage currents as well [5]. Fig. 2 illustrates the temperature dependence of the subthreshold swing and the threshold voltage shift of a NMOS transistor in the 65 nm process.

The conventional level shifter, shown in Fig. 3, can be implemented as an interface between two voltage domains as long as the input voltage is above the threshold voltage, Vtn, of Mn1 (and Mn2). The level shifter has the following operational behavior: When the input goes from a logic low to a logic high, Mn1 is turned on and Mn2 is turned off. Then, the voltage at node nA is pulled towards ground due to the conducting path established by Mn1. If the voltage at node nA reaches (Vdd  Vth(Mp2)), the positive feedback is triggered as Mp2 turns on and pulls node nB high. The input has then been shifted from a lower voltage level, to a higher voltage level, through the output inverter. The circuit behavior is inverted for opposite input case. The voltage shift can be completed only if the pull-up/pull-down ratio is roughly the same. In other words, the pull-up strength has to be close or equal to the pull-down strength. If the pull-up/pull-down ratio is not close to unity, contention will take place between the pull-up transistors (Mp1 and Mp2) and pull-down transistors (Mn1 and Mn2), which will increase delay and increase power consumption [6]. This contention worsens when the input signal approaches subthreshold. For subthreshold voltages on the input, the drive strength of Mn1 may not be able to overcome the drive strength of Mp1. Hence, node nA cannot be pulled down, and the positive feedback cannot be triggered, labeling the conventional level shifter impractical for subthreshold conversion. By increasing the width of Mn1 and Mn2 and increasing the length of Mp1 and Mp2, close to threshold

VDDH

VDDH

VDDH

Mp2

Mp1

nB

nA

Mp4

VDDL

input Mn1

Mn2 Mp3

Mn3

Fig. 3. Dual cascode voltage switch.

Mn4

output

A. Hasanbegovic, S. Aunet / Microprocessors and Microsystems 35 (2011) 1–9

voltages may be converted. However, the width increase of Mn1 and Mn2 would come at an expense of high leakage currents and increased area. The pull-up/pull-down ratio sizing for the conventional level shifter is described in [7], where it is also concluded that the sizing ratio is impractical for subthreshold conversion. In order to enable subthreshold conversion, the pull-up/pull-down ratio has to be equalized. 3. Proposed level shifters in 90 nm and 65 nm process The proposed level shifter topology (MDCVS), shown in Fig. 4, is designed in a 90 nm general purpose process from ST Microelectronics and utilizes multithreshold voltage CMOS (MTCMOS) design technique. Low-threshold transistors (‘‘lvt’’) are placed where speed is of importance at the expense of leakage current and high-threshold transistors (‘‘hvt’’) are placed where leakage current can be reduced at the expense of speed. In addition to the low-VT and the high-VT transistors, a standard threshold transistor (‘‘svt’’) is provided in the library which presents a tradeoff between leakage and speed in itself. The use of multi-VT transistors enables us to find a good tradeoff between static power consumption, dynamic power consumption and propagation delay. The proposed level shifter has been designed in two versions to satisfy the needs of both high speed (MDCVSHS) and low power (MDCVSLP) operation, subthreshold operation taken into consideration. The level shifter topology has also been implemented in 65 nm (MDCVS65) low power process from STMicroelectronics and is based on the same topology as the level shifter in the 90 nm process. The level shifter works in the same matter as the level shifter in Fig. 4. The main changes done in the 65 nm version are choice of transistor types and sizes as well as supply voltag (VDDH). The 90 nm process used here has a typical supply voltage of 1 V as the 65 nm process has a typical supply voltage of 1.2 V. 3.1. Modified dual cascode voltage switch (MDCVS) The new level shifter topology is inspired by the DCVS circuit topology, and makes use of topological modifications in order to enable subthreshold to above threshold level conversion. The circuit exploits several techniques in order to limit the contention between pull-up and pull-down at nodes nA and nC. Primarily, the pull-down transistors (Mn1 and Mn2) are set to low threshold transistors, meaning they conduct more current at a given gate voltage. This increase in current makes it easier for the pull-down

VDDH

VDDH

Mp8

Mp7

VDDH

VDDH Mp1

Mp2

nC

nD

Mp5

Mp6

en Mp4

nB

nA

Mn4

VDDL

input

en Mn1 Mp3

en Mn5

Mn2

Mn8

en Mn6

Mp9

output

3

strength to follow the pull-up strength. However, the low threshold transistors are not enough to establish an even pull-up/pulldown ratio for subthreshold inputs. As proposed in [8], diode connected PMOS (Mp5 and Mp6) can be used to limit the pull-up strength of the two branches in the level shifter. When the level shifter is in steady state, jVgsj of the diodes is small and is equal to the diode voltage drop VMPD. When the input signal switches, the diode voltage drop is kept stable, limiting the pull-up strength. However, in our design this configuration is taken one step further in an attempt to reduce energy consumption. Since the voltage at node nA only goes up to Vdd  VMPD, and the voltage at node nC only goes down to gnd + VMPD, Mp4 and Mn4 are never completely turned on. This results in reduction of short circuit current, and may thereby contribute to a reduction of dynamic power consumption in the output inverter, given that the capacitive load is relatively low. Another useful feature with the PMOS diodes is that they enable VDDL scaling, which is critical in adaptive voltage scaling systems [1]. When VDDL increases, the pull-down strength of the level shifter increases as a result of increase in conducting sink current. The increase in sink current contributes to a faster increase in voltage drop across the PMOS diodes during the transistor switching time, thereby maintaining the pull-up/pull-down ratio. An increase in both pull-up and pull-down strength results in a reduction of the propagation delay, which allows higher operational frequencies as VDDL scales up. In order to achieve robust operation at lower temperatures Mp7 and Mp8 are added, which may further limit or increase the drive strength of the pull-up transistors (Mp1 and Mp2) by sizing the transistors up or down respectively, enabling fine adjustments of the pull-up/pull-down ratio. Transistors Mp7 and Mp8 are biased in off-state, providing a leakage current in their respective branch. This configuration allows the pull-up strength of Mp1 and Mp2 to be controlled by sizing of Mp7 and Mp8. By increasing(decreasing) the size of Mp7 and Mp8, the pull-up transistors will conduct more(less) current, thereby increase(decrease) the pull-up strength. This enables control over the rise- and fall delay on the output by balancing the pull-up/pull-down ratio. Furthermore, as the temperature increases, the leakage current from Mp7 and Mp8 becomes larger which in turn increases the pull-up strength of Mp1 and Mp2. Proper functionality is preserved because of the constant voltage drop over the PMOS diodes, limiting the pull up strength at high temperatures as well. By adding four additional sleep transistors, Mn5, Mn6, Mn7 and Mn8, the level shifter can be turned on or off (sleep-mode) by setting their gate to ‘1’ or ‘0’ respectively. The sleep configuration is implemented using high threshold NMOS transistors since the on-resistance of an NMOS is smaller then the on-resistance of a PMOS, given the same size [9]. Furthermore, the NMOS configuration is chosen due to practical ease of layout reasons, which are described in Section 4.2. When the level shifter is turned off, an isolation cell is needed to separate neighboring cells supplied by different supply voltages. When EN is ‘0’ (i.e. the level shifter is in sleep-mode), the output node is pulled up to VDDH via Mp9, thereby avoiding an intermediate state on the output. Intermediate or floating outputs may cause a large static current path between power and ground, therefore a pull-up transistor is needed if the output is driving a transistor gate. The combination of the sleepand isolation configuration make the level shifter power gating compliant while utilizing a single cell.

Mn3 en Mn7

Fig. 4. Proposed circuit topology of the level shifters.

4. Implementation considerations Factors such as area-, speed- and power consumption are very important when it comes to effectively implementing level shifters

4

A. Hasanbegovic, S. Aunet / Microprocessors and Microsystems 35 (2011) 1–9

in larger designs. Therefore, some implementation considerations need to be taken into account. 4.1. Implementation of sleep transistors The length and width of the sleep transistors will have a significant impact on the NMOS sink current if a footer configuration is used. Increase in the sleep transistor length will increase the source voltage of the input NMOS transistor due to the ON resistance in the sleep transistor and thereby decrease the Vgs of the input NMOS transistors, Mn1 and Mn2 in Fig. 4 [10]. This decrease in Vgs leads to a decrease in the sink current of the NMOS transistor, which contributes to lower power consumption, as well as degrading of the speed of the circuit. The speed is affected by the reduction in rise- and fall times. Therefore, the lengths of the sleep transistors should be set to meet a reasonable trade-off between speed and power. In order to achieve an effective sleep-mode in a low power system, one should carefully choose the approach to realizing the sleep-mode configuration. As presented in [11], ‘‘sneak leakage’’ can have a substantial impact on the power consumption when in sleep-mode. In the proposed level shifter topology, sleep transistors have been implemented in a NMOS footer configuration due to the low ON-resistance of NMOS transistors. Keeping this in mind, the circuitry the level shifter is interfacing should utilize the same sleep-mode configuration as the level shifter, i.e. a NMOS footer configuration, given that the circuitry is based on MTCMOS. An ex-

Fig. 5. Layout of MDCVS65.

tended set of rules for avoiding sneak leakage may be found in [11]. A sleep-mode configuration comprising both footer and header transistors may be an unattractive approach due to a larger area overhead with little to gain in terms of leakage control [5]. Therefore, for this particular level shifter topology, it is adequate with a sleep-mode configuration that utilizes either a header or a footer configuration.

4.2. Level shifter layout When designing a larger system that makes use of level shifters, the layout of the level shifter becomes an important factor. The proposed level shifters have been implemented using the same layout strategy as in [12]. The routing of the level shifters is realized using metal layers 1 and 2, thereby leaving the other metal layers available for interconnect on a higher abstraction level. The layout of the MDCVS65 is illustrated in Fig. 5, and utilizes dual-height cell approach, meaning the cell height of the level shifter is twice the cell height of a standard cell. The layout dimensions of the level shifters (using footer sleep configuration) are 9.8 lm  9.2 lm, 9.8 lm  6.1 lm and 6.4 lm  6.4 lm for MDCVSLP, MDCVSHS and MDCVS65 respectively. In Fig. 5, two power supply lines are shown; VDDL (bottom), VDDH (top) and GND (middle). The advantage of a dual-height cell implantation of the proposed level shifter topology is the ability to utilize well-sharing. Well-sharing leads to a compact physical implementation by relieving the dimensional limitations related to physical layout constraints. Although dual-height cells may imply some impracticalities when deployed in a single-height cell design, a streamlined interface between VDDL and VDDH domains can easily be accomplished by flipping layout cells. Fig. 6 illustrates a physical layout strategy for interfacing VDDL and VDDH domains while exploiting the advantages of well-sharing. ‘‘Level shifter 1’’ and ‘‘Level shifter 2’’ can be put next to each other horizontally in order to comply with the cell height of two digital cells (denoted as ‘‘VDDL cell’’ and ‘‘VDDH cell’’ in Fig. 6). By flipping ‘‘VDDL cell 2’’ across the x-axis, in respect to ‘‘VDDL cell 1’’, proper placement configuration is achieved for exploiting the advantages of well-sharing. For this particular case, ‘‘VDDL cell 1’’ and ‘‘VDDL cell 2’’ would be sharing the ground connection. Correspondingly, by flipping ‘‘VDDL cell 3’’ across the x-axis in respect to ‘‘VDDL cell 2’’ (i.e. ‘‘VDDL cell’’ 3 has the same orientation as ‘‘VDDL cell 1’’), enables ‘‘VDDL cell 3’’ to share its n-well with ‘‘VDDL cell 2’’. In the same way as for the digital cells, flipping the level shifters will also lead to well-sharing. ‘‘Level shifter 3’’ and ‘‘Level shifter 4’’

Fig. 6. Physical layout strategy for interfacing VDDL and VDDH domains.

5

A. Hasanbegovic, S. Aunet / Microprocessors and Microsystems 35 (2011) 1–9

W/L (lm)

Transistor

Type

W/L (lm)

MN1 MN2 MN3 MN4 MN5 MN6 MN7 MN8 MP1

svtlp svtlp svtlp svtlp hvtlp hvtlp hvtlp hvtlp hvtlp

0.2/0.4 0.2/0.4 0.8/0.08 0.12/0.12 0.12/0.2 0.12/0.2 0.12/0.2 0.12/0.2 0.12/0.15

MP2 MP3 MP4 MP5 MP6 MP7 MP8 MP9

hvtlp lvtlp hvtlp lvtlp lvtlp svt svt hvtlp

0.12/0.06 0.36/0.1 0.36/0.06 0.3/0.2 0.3/0.2 6/0.06 6/0.06 0.5/0.5

10n

30f Static power consumption MDCVSHS Energy consumption per transition MDCVSHS

8n

25f

6n

20f

4n

15f

2n 0.1

0.2

0.3

0.4

0.5

0.6

0.7

10f 0.8

Energy consumption per tran sit ion (J )

Type

VDDL (V)

(a) Static power- and energy consumption 40n

60n Average power consumption MDCVSHS Propagation delay MDCVSHS

30n

50n

20n

40n

10n

30n

0n 0.1

0.2

0.3

0.4

0.5

0.6

0.7

Average p ower con sumpt ion (W )

In this section we present the simulation results focusing around the following design parameters: Static power consumption, energy consumption, propagation delay and average power consumption. These design parameters are put in context with scaling of the lower supply voltage (VDDL). The simulation results are based on post layout simulations at 27 °C with a 10 fF capacitive load and input signal rise- and fall times of 10 ns. The riseand fall times of the input signal are chosen based on worst case Monte Carlo simulations of a minimum sized inverter under the same temperature conditions. The capacitive load is chosen arbitrarily, emulating a (large) buffer input or equivalent circuit. In most cases however, the level shifter would drive smaller capacitive loads, such as close to minimum sized transistor gates. Simulations were run for 20 input periods to capture any behavioral irregularities in the circuit simulations that may corrupt the results. All simulation results are extracted from the CadenceÒ Virtu-

Transistor

Stat ic power consumption (W)

5. Circuit simulations

Table 3 Transistor types and sizes for the MDCVS65.

Propagation delay (s)

are flipped across the x-axis, enabling them to share an n-well with ‘‘Level shifter1’’ and ‘‘Level shifter 2’’. By applying the necessary connections between the VDDL cells (in the VDDL domain) and the level shifters, the VDDH domain can easily be interfaced, given that the VDDH cells have the same orientation as the VDDL cells. This approach will however impose special placement and orientation rules on a placement tool. Care should also be taken when deciding if a header or footer sleep configuration should be implemented. In this level shifter topology the best suited approach is to use the footer sleep configuration in order to preserve the cell height and to make the layout as compact as possible. Since the p-channel devices take up a relatively large area compared to the n-channel devices (due to transistors MP7 and MP8), there is more room left in the n-channel area for sleep transistors. A header configuration for the sleep transistors may therefore contribute to a less compact layout due to the need of exploiting more of the cell width instead. However a reduction in sleep mode power consumption may be achieved due to the lower mobility of p-channel devices.

20n 0.8

VDDL (V)

(b) Propagation delay and total power consumption

Table 1 Transistor types and sizes for the MDCVSLP. Transistor

Type

W/L (lm)

Transistor

Type

W/L (lm)

MN1 MN2 MN3 MN4 MN5 MN6 MN7 MN8 MP1

lvt lvt svt hvt hvt hvt hvt hvt hvt

0.3/1 0.3/1 2/0.2 0.24/0.2 0.12/0.2 0.12/0.2 0.12/0.2 0.12/0.2 0.12/0.15

MP2 MP3 MP4 MP5 MP6 MP7 MP8 MP9

hvt svt hvt lvt lvt lvt lvt hvt

0.12/0.15 2/0.2 0.6/0.2 0.12/0.15 0.12/0.15 6/0.1 6/0.1 0.6/0.1

Table 2 Transistor types and sizes for the MDCVSHS. Transistor

Type

W/L (lm)

Transistor

Type

W/L (lm)

MN1 MN2 MN3 MN4 MN5 MN6 MN7 MN8 MP1

lvt lvt lvt hvt hvt hvt hvt hvt hvt

0.12/0.2 0.12/0.2 0.12/0.1 0.12/0.1 0.12/0.2 0.12/0.2 0.12/0.2 0.12/0.2 0.12/0.15

MP2 MP3 MP4 MP5 MP6 MP7 MP8 MP9

hvt lvt hvt lvt lvt lvt lvt hvt

0.12/0.1 0.36/0.1 0.6/0.2 0.2/0.1 0.2/0.1 8/0.1 8/0.1 0.6/0.1

Fig. 7. Level shifter (MDCVSHS) performance with varying VDDL when VDDH = 1 V and the input signal frequency is 1 MHz.

osoÒ SpectreÒ Circuit Simulator. Transistor types and sizes used for the simulations are shown in Table 1 for the MDCVSLP, Table 2 for the MDCVSHS and Table 3 for the MDCVS65.

5.1. Simulation results of 90 nm level shifter Figs. 7a and 8a show the static power consumption and the total energy consumption per transition as a function of VDDL for MDCVSHS and MDCVSLP respectively. Simulation results show that an increase in VDDL contributes to increase in both static power- and energy consumption when VDDL > Vtn. This trend is primarily due to transistors Mn1 and Mn2 being in the above threshold region and depends on their capability to sink current. When VDDL is scaled further up in the above threshold region, the static current in Mn1 and Mn2 is increased, which also increases the leakage energy. As indicated, the energy consumption is lowest when VDDL is around 200 mV–300 mV. At this operating point the combination of the contention between pull-up and pull-down transistors and the leakage energy, is the lowest. However, the reduction of VDDL

A. Hasanbegovic, S. Aunet / Microprocessors and Microsystems 35 (2011) 1–9 30f Energy consumption per transition MDCVSLP Static power consumption MDCVSLP

2n

25f

1.5n

20f

1n

0.5n 0.1

15f

0.2

0.3

0.4

0.5

0.6

0.7

10f 0.8

1.25

1.0

.75

V (V)

Stat ic power consumption (W)

2.5n

Energy consumption per transit ion (J )

6

.5

.25

0

VDDL (V) -.25

(a) Static power- and energy consumption

0

1.0

.5

2.0

1.5

Time (us) 30n

0n 0.1

20n

0.2

0.3

0.4

0.5

0.6

0.7

15n 0.8

VDDL (V)

(b) Propagation delay and average power consumption Fig. 8. Level shifter (MDCVSLP) performance with varying VDDL when VDDH = 1 V and the input signal frequency is 500 kHz.

below Vtn gives rise to crowbar currents due to increasing contention between pull-up and pull-down transistors. The contention results in higher propagation delay and thereby an increase in the active energy consumption, since the active energy consumption is determined by the time period necessary to perform a voltage transition. This is also reflected in the average power consumption illustrated in Figs. 7b and 8b, where the active energy is the dominating power consumption contribution when VDDL < Vtn. When VDDL is in the subthreshold region, the propagation delay has exponential dependency on VDDL, arising from the exponential behavior of Ids of Mn1, Mn2, Mn3 and Mp3. Figs. 7b and 8b show how the propagation delay varies with VDDL. The decrease in propagation delay with increasing VDDL confirms the level shifters ability to work at higher operational frequencies as the VDDL increases. The average power consumption is increased with an increase in VDDL where the main contribution is due to an increase in dynamic (switching) power consumption in the above threshold region. The robustness of the level shifters is verified with Monte Carlo simulations both for the case of MDCVSLP and MDCVSHS, for all the stated simulation conditions. Fig. 9 illustrate the worst case simulation condition for the level shifters, being low temperature operation. Proper operation behavior is verified across a temperature range of 40 °C ? 150 °C. When the level shifters are put in sleep-mode, the MDCVSHS shows an average power consumption of 175 pW while MDCVSLP shows 48 pW.

130p

120p

28f

110p

26f

100p

24f

90p

22f

80p 0.3

The simulation results of the 65 nm implementation are based on the same design parameters and simulation specifications as

0.4

0.5

0.6

0.7 0.8 VDDL (V)

0.9

1

20f 1.1

(a) Static power- and energy consumption 80n

28n Propagation delay MDCVS65 Average power consumption MDCVS65

60n

26n

40n

24n

20n

22n

0n 0.3

5.2. Simulation results of 65 nm level shifter

30f Energy consumption per transition MDCVS65 Static power consumption MDCVS65

Energy consumption per transition (J)

50n

the simulation results in the 90 nm process. The simulation results of the MDCVS65 show the same trends as the 90 nm implementation in respect to the design parameters. Since the MDCVS65 is based on the exact same topology as the level shifters in 90 nm, the same contention problems between pull-up and pull-down are observed in the subthreshold region. Fig. 10a and b show the simulation results of the MDCVS65. We observe a dramatic decrease in static power consumption in the 65 nm implementation compared to the 90 nm implementation, as seen in Fig. 10a. The main source of impact to the low static power consumption is that the process is a low power process, which inherently provides low leakage transistor behavior. Due to the jVthj being relatively higher in the 65 nm process compared to the 90 nm process, the contention currents become apparent when VDDL shifts approximately below 475 mV. This is observed in the increase of the energy con-

0.4

0.5

0.6

0.7

0.8

0.9

1

Average power consumption (W)

25n

Static power consumption (W)

100n

Fig. 9. Level shifter (MDCVSHS) output when VDDL = 180 mV and VDDH = 1 V at 40 °C (300 post layout Monte Carlo simulations).

Propagation delay (s)

P ropagat ion delay (s)

Average power consumption MDCVSLP Propagation delay MDCVSLP

Average power consumpt ion (W)

150n

20n 1.1

VD DL (V)

(b) Propagation delay and average power consumption Fig. 10. Level shifter (MDCVS65) performance with varying VDDL when VDDH = 1.2 V and the input signal frequency is 500 kHz.

7

Static power consumption (W)

1.25 1.0

.5 .25

1n

60f

100p

10p

0 -.25 2.0

80f Static power consumption MDCVS65 Energy consumption per transition MDCVS65

2n

40f

−40

−20

0

20

40

60

80

100

120

140

20f 160

Temperature (degrees Celsius)

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

200n

Propagation delay (s)

Time (us)

(a) Level shifter output when VDDH = 1.2 V 1.25 1.0

150n

80n

100n

60n

50n

40n

0n

.75

100n Propagation delay per transistion MDCVS65 Average power consumption MDCVS65

−40

−20

0

20

40

60

80

100

120

140

20n 160

Average power consumption (W)

V (V)

.75

6n 4n

Energy consumption per transition (J)

A. Hasanbegovic, S. Aunet / Microprocessors and Microsystems 35 (2011) 1–9

V (V)

Temperature (degrees Celsius)

.5

Fig. 12. Performance of the level shifter (MDCVS65) with temperature variations across a temperature range of 40 °C ? 150 °C.

.25 0 -.25 2.0

2.5

3.0

3.5

4.0 Time (us)

4.5

5.0

5.5

6.0

(b) Level shifter output when VDDH = 1 V Fig. 11. Level shifter (MDCVS65) output when VDDL = 350 mV and the input signal is 500 kHz at 40 °C (300 post layout Monte Carlo simulations).

sumption when VDDL is around the threshold voltage, Vtn, of Mn1 and Mn2. When put in sleep-mode, the MDCVS65 shows an average power consumption of 9 pW. The 65 nm implementation displays the same robustness qualities as seen in the 90 nm simulations of the level shifter topology. Fig. 11 shows Monte Carlo simulation of the level shifter output, at 40 °C. It can be seen that there is a propagation delay difference between the results in Fig. 11a and b. For the case of VDDH = 1 V, a small increase in propagation delay is observed compared to the VDDH = 1.2 V. The reduction of the supply voltage reduces the Vds in all transistors supplied by VDDH, which in turn contributes reduced power consumption and an increase in propagation delay. Also, transistors Mp7 and Mp8 need to be sized wide enough in order to enable VDDH scaling in the range of few hundred mVs. However, a wide VDDH scaling range is difficult to achieve due to the Vds variation sensitivity of the off-biased transistors Mp7 and Mp8. As seen previously, the performance trends for the 65 nm and 90 nm level shifters are very similar, and this is also true for the case of temperature variations. Fig. 12 shows the performance as a function of temperature variations for the MDCVS65, and the performance trends also yield for the 90 nm level shifters. The temperature dependence of the static power consumption exhibits an exponentially increasing trend with increasing temperature. This is due to the exponential leakage-temperature relation of CMOS transistors [13]. Similarly, the energy consumption per transition also increases with increasing temperature. However, the variation in energy consumption across the temperature range is smaller then the variation in the static power consumption due to the total switching energy being higher then the total leakage energy.

When temperature variations are concerned in the specified temperature range of 40 °C ? 150 °C, the level shifters display a general propagation delay decrease as the temperature increases. Since the level shifters ability to cope with temperature variations is primarily limited by the transistors operating in the subthreshold region, the speed of the circuit is therefore highly dependent on this specific relation. The temperature dependent carrier transport by diffusion governs the propagation delay by contributing to low ION/IOFF currents at low temperature and high ION/IOFF currents at high temperatures. Thereby the transistors operating in subthreshold region dominate the propagation delay trend across the specified temperature range.

6. Discussion The level shifters are primarily aimed for converting voltage signals from subthreshold voltage to voltage levels several hundred mVs above. Nevertheless, the level shifters shows acceptable performance while converting from a wider range of voltage levels. This makes the level shifters suitable for applications where dynamic voltage scaling (DVS) is required to satisfy speed requirements by dynamically increasing/decreasing VDDL. When interfacing two voltage domains, level shifter performance is of critical importance. Our analysis shows that by adjusting transistor-sizing and type, we are able to modify the performance of the level shifter while using the same topology. This adjustment will however have an impact of the physical layout size of the level shifter, but will most probably not extend the dual-height cell specification of the level shifter since these adjustments can be implemented while exploiting the cell width instead. For VDDL below the threshold voltage, we see a rapid increase in propagation delay. This indicates that this level shifter topology is highly susceptible to supply bounce and IR drop. In order to achieve intended performance of the level shifters, it is critical to minimize the effects of supply bounce and IR drops. Alternatively, the transistor-sizing and type may be adjusted to meet the delay requirements based on the expected supply bounce and IR drop behavior. The resulting decrease in delay will therefore come at an expense of increased power- and potentially, area consumption.

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A. Hasanbegovic, S. Aunet / Microprocessors and Microsystems 35 (2011) 1–9

Table 4 Level shifter comparison. Design parameter

DSLS2b [14]

LC [8]

CMLS [7]

WCMLS [15]

MDCVSLP

MDCVSHS

MDCVS65

Level shifter design Propagation delay Energy cons. per trans. Static power cons. VDDL/min. VDDL VDDH Process

110 ns 21.8 pJ n/a 0.35 V/0.35 V 1.2 V SOI 0.25 lm

10 ls 8 nJ n/a 0.2 V/0.13 V 1.2 V 0.18 lm bulk

50 ns 25 pJ 5 nW 0.18 V/0.1 V 1.2 V 0.13 lm bulk

18.4 ns 93.9 fJ 6.6 nW 0.2 V/0.1 V 1V 90 nm bulk

120 ns 21 fJ 1 nW 0.18 V/0.18 V 1V 90 nm bulk

32 ns 17 fJ 2.5 nW 0.18 V/0.18 V 1V 90 nm bulk

64 ns 23 fJ 84 pW 0.35 V/0.35 V 1.2 V 65 nm bulk

When process- and mismatch variations are concerned, the proposed level shifters has the typical properties as subthreshold circuit dominated exponential current dependencies. The most vulnerable transistors to process- and mismatch variations are Mn1, Mn2, Mn3, Mp3, Mp7 and Mp8 due to being operated in the subthreshold region. Since Mp7 and Mp8 are larger then the other transistors, the impact of process- and mismatch variations in the level shifters would be limited by the smaller transistors. Post layout simulations do however confirm satisfactory circuit performance across process-, mismatch-, VDDH-, VDDL- and temperature variations at operational frequencies of 500 kHz and 1 MHz with subthreshold input signals. When compared to the conventional level shifter, the proposed level shifter topology is less efficient when converting lower above threshold signals to higher above threshold signals. The input transistors in the proposed topology are low threshold transistors and thereby contribute to increased static power consumption when higher gate voltages are applied (VDDL increases). When the pull-up/pull-down ratio in the conventional level shifter is close to unity, the power consumption is smaller than for the proposed level shifter topology. However, when VDDL changes in the conventional level shifter, the pull-up/pull-down ratio is altered, introducing increase in power- and energy consumption due to contention between pull-up and pull-down transistors. This is the main drawback of the conventional level shifter, therefor it is only suited for applications where small changes in VDDL occur, and when VDDL is above the threshold voltage of the input transistors. The utilization of the proposed level shifter topology provides more flexibility by enabling both subthreshold and above threshold conversion. In addition, it also offers compatibility with a much larger VDDL span, which is highly advantages for systems that utilize a wide range of supply voltages in the DVS scheme. Table 4 illustrates the how the level shifter performance varies across different processes with emphasis on subthreshold to above threshold conversion.2 The energy and power needed to complete a voltage shift from subthreshold level to above threshold level is substantially reduced in a deep submicron process. To the authors knowledge, according to simulation results, this is the lowest power- and energy consumption reported regarding subthreshold to above threshold level shifters with similar design parameters.

7. Conclusion Our work shows that by applying MTCMOS design technique to subthreshold level shifter design, low power- and energy consumption may be achieved while maintaining reliable performance

2 The values in Table 4 are extracted from the respective papers. Although the design parameters are similar, some parameters which have an impact on these values may differ, such as load capacitance, pre-/post layout simulations, input rise-/ fall times, temperature, etc.

in 90 nm and 65 nm process. The level shifters also demonstrate compatibility with dynamic voltage scaling, at the expense of variations in power- and energy consumption. We also illustrate a physical implementation approach which confirms effective integration of the level shifters in a larger design, in terms of maximum area utilization. The proposed level shifters are designed with sleep-mode and isolation capability while making use of a single dual-height cell physical implementation strategy. For applications requiring voltage level shifting from subthreshold voltages to above threshold voltage, the proposed level shifters may serve as a good solution. However, if subthreshold level conversion is not required and the VDDL scaling requirements are low, then the conventional level shifter may be more efficient in terms of power and energy consumption.

References [1] V. Gutnik, A.P. Chandrakasan, Embedded power supply for low-power dsp, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 5 (4) (1997) 425–435. [2] A. Wang, B.H. Calhoun, A.P. Chandrakasan, Sub-threshold Design for Ultra LowPower Systems (Series on Integrated Circuits and Systems), Springer-Verlag New York, Inc., Secaucus, NJ, USA, 2006. [3] C. Mead, Analog VLSI and Neural Systems, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, USA, 1989. [4] S. Mukhopadhyay, A. Raychowdhury, K. Roy, Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 24 (3) (2005) 363–381. [5] K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand, Leakage current mechanisms and leakage reduction techniques in deep-submicrometer cmos circuits, Proceedings of the IEEE 91 (2) (2003) 305–327. [6] C.Q. Tran, H. Kawaguchi, T. Sakurai, Low-power high-speed level shifter design for block-level dynamic voltage scaling environment, in: Proc. International Conference on Integrated Circuit Design and Technology ICICDT 2005, May 9– 11, 2005, pp. 229–232. [7] T.-H. Chen, J. Chen, L.T. Clark, Subthreshold to above threshold level shifter design, Journal of Low Power Electronics 2 (2) (2006) 251–258. [8] H. Shao, C.-Y. Tsui, A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic, in: Proc. ESSCIRC 33rd European Solid State Circuits Conference, September 11–13, 2007, pp. 312– 315. [9] J. Kao, A. Chandrakasan, D. Antoniadis, Transistor sizing issues and tool for multi-threshold CMOS technology, in: Proc. 34th Design Automation Conference, June 1997, pp. 409–414. [10] M. Seok, S. Hanson, D. Sylvester, D. Blaauw, Analysis and optimization of sleep modes in subthreshold circuit design, in: Design Automation Conference, 2007. DAC ’07. 44th ACM/IEEE, June 2007, pp. 694–699. [11] B. Calhoun, F. Honore, A. Chandrakasan, Design methodology for fine-grained leakage control in mtcmos, in: Low Power Electronics and Design, 2003. ISLPED ’03. Proceedings of the 2003 International Symposium on, August 2003, pp. 104–109. [12] F. Ishihara, F. Sheikh, B. Nikolic, Level conversion for dual-supply systems, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 12 (2) (2004) 185–195. [13] D. Helms, E. Schmidt, W. Nebel, Leakage in CMOS circuits – an introduction, in: E. Macii, V. Paliouras, O. Koufopavlou (Eds.), Lecture Notes in Computer Science, vol. 3254, Springer, Berlin, Heidelberg, 2004. [14] A. Chavan, E. MacDonald, Ultra low voltage level shifters to interface sub and super threshold reconfigurable logic cells, in: Proc. IEEE Aerospace Conference, March 1–8, 2008, pp. 1–6. [15] S. Lütkemeier, U. Rückert, A subthreshold to above-threshold level shifter comprising a wilson current mirror, Circuits and Systems II: Express Briefs, IEEE Transactions on 57 (9) (2010) 721–724.

A. Hasanbegovic, S. Aunet / Microprocessors and Microsystems 35 (2011) 1–9 Amir Hasanbegovic earned his master’s degree in Micro- and nanoelectronics at the Nanoelectronics group, University of Oslo, in June 2010. Since 2009, he has published several peer-reviewed papers, as well as being involved in teaching Mixed-Signal CMOS design at the Department of informatics, University of Oslo. He is currently pursuing his Ph.D degree at the Nanoelectronics group, University of Oslo. He is also a visiting scholar at the Heinz Nixdorf Institute in Paderborn, Germany, through the DAAD researcher exchange program. His main research interests are low power- and radiation hardened circuit design in nanoscale CMOS technologies.

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Snorre Aunet received the Dr. Ing. degree in physical electronics from the Norwegian University of Science and Technology (NTNU), Trondheim, Norway, in 2002. He has worked for Nortroll A/S, ABB Corporate Research, NTNU, and Nordic VLSI, in Norway. He is currently Associate Professor at the Department of informatics, University of Oslo. He has published approximately 80 peer reviewed papers, books and patents. His research interests include ultra low power biologically inspired defect-tolerant nanoarchitectures. He was the co-chair of the Norchip Conference in Trondheim, 2009.