Low temperature CMOS—a brief review

World Abstracts on Microeleetronics and Reliability Low temperature CMOS---a brief review. WILLIAMF. CLARK et al. IEEE Transactions on Components, Hybrids, and Manufacturing Technology 15(3), 397 (1992). Device improvements obtained from exploiting the dependence of physical characteristics of silicon at low temperature are above and beyond those improvements obtained from the usual geometric scaling of device dimensions. As device geometries continue to shrink into the deep submicrometer regime, second-order effects begin to limit further increases in device speed from scaling alone. Temperature scaling provides an additional variable for system optimization. The gain in performance at cryogenic temperatures, however, is at the expense of inconvenience and additional cost for system refrigeration, and of increased susceptibility to hot carrier degradation. Optimizing CMOS technology and design for low temperature applications can increase performance and reduce power dissipation without increasing hot carrier degradation. Growth of thin thermal silicon dioxide films with low defect density. R. SINGH. Microelectronics Journal 23, 273 (1992). The use of thin gate oxides in scaled MOS-VLSI devices demands good control over oxide thickness, oxide defects, hot carrier instability and breakdown behaviour. In the quest to grow high quality SiO2 films with low defect density, an investigation on the effect of growth and annealing ambients on oxide properties is reported. Thin SiO2 films (10-60 nm) grown at 900-1000°C in 05/05 + N2 were characterized by C - V and I - V techniques using Al/SiO2/p-Si and poly-Si/SiO2/p-Si structures. Quality oxides with a very low density of physical defects due to contamination/pinholes (responsible for dielectric breakdown at fields lower than the intrinsic breakdown fields), H20-related and intrinsic defects (acting as electron and hole traps) have been demonstrated. The effect of post-oxidation annealing in N 2 and 05 on defect-related low-field and intrinsic breakdown behaviour was studied. The occurrence of low-field pre-breakdowns can be reduced by a short 05 anneal, in agreement with our earlier results. Oxide device worthiness was tested by fabricating N-MOSFETs. A novel technique for the simultaneous measurement of ambipolar carrier lifetime and diffusion coefficient in silicon. MATS ROSLING et al. Solid-State Electronics 35(9), 1223 (1992). Using the classical semiconductor continuity equation, a new method for the simultaneous extraction of the ambipolar carrier lifetime and the ambipolar diffusion coefficient for high injection levels is developed. The method uses carrier decay measurements based on the free-carrier absorption (FCA) technique. The measurements are performed in the base of p-i-n type diodes, where the middle region is a lightly n-doped base region. By varying the forward bias, the ambipolar lifetime and

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diffusion coefficients are studied for different excesscarrier concentrations ranging approx. 2-4 decades above the base doping. Both the lifetime and diffusion coefficients agree well with theoretical models. The theoretical ambipolar diffusion coefficients agree well with theoretical models. The theoretical ambipolar diffusion coefficient is calculated using the values of D n and Dp, which, in turn, are determined from mobility models and the Einstein relation. The mobility models used include carrier-carrier scattering effects which are important in the explanation of high-injection dependence. Growth by molecular beam epitaxy (MBE) and structural characterization of GaAs and AIGaAs on silicon. B. BARTENLIAN. Revue Technique Thomson-CSF 24(2), 313 (1992). (In French.) The growth of compound semiconductors such as GaAs and AIGaAs on silicon substrates is of increasing interest since it allows the monolithic integration of optoelectronic devices with silicon based electronic circuits. The difference in lattice parameter between these two materials (Aa/a=4.1%) and the difference in thermal expansion coefficient, create linear and planar defects in the overgrown films which can be electrically active. An islanding nucleation give rise to surface and interface roughness. During the coalescence of these islands, defects are created. We optimized the GaAs/Si growth with MBE by using a vicinal silicon surface, a nucleation with migration enhanced epitaxy (MEE) and a two-temperature growth procedure. Transmission electron microscopy, X-ray photoelectron spectroscopy, Xray photoelectron diffraction, reflection high energy electron diffraction and X-ray double crystal diffraction, have been used to characterize the different steps of the growth, especially at low temperature (30if'C). The influence of thermal annealing (600'C) at the different stages of growth has also been studied. We show that the substrate temperature during the deposition of the first monoatomic layer of As has an influence on the final orientation of the GaAs with respect to the ledges of the silicon steps. Nucleation with MEE results in surface roughness smoothing with increasing layer thickness. The relaxation of the stress in GaAs on Si grown at low temperature (300°C) is done by the migration of partial dislocations which create between them stacking faults and microtwins. Thermal annealing (600C) of layers, with thicknesses less than 50 nm, give rise to facetting islands of GaAs. Using thermodynamic considerations, we calculate an interface energy of 3" 10-5 J cm -2, which we correlate to the energy of the Lomer dislocation network. Thermal annealing and growth at greater thicknesses (~>50nm) have a smoothing effect on the surface. Stacking faults disappear by creating a Lomer dislocation network at the interface and threading dislocations in the bulk material. We have fabricated and studied metal semiconductor field effect transistors (MESFETs) and