LV circuits: state of the art and prospects

MICROELECTRONIC ENGINEERING

ELSEVIER

Microelectronic Engineering 39 (1997) 1 ~

LP/LV circuits : state of the art and prospects J. Borel SGS-THOMSON Microelectronics, Crolles, France 1. I N T R O D U C T I O N The silicon semiconductor business is becoming a strategic part of the worldwide economy (and will reach the top market position around year 2000) both in size and in pervasion into the global system business. This is due to the ever increasing complexity of integration of a complete system on a chip. This has impacts on system performance (speed and power consumption) and cost and opens new markets where these parameters are of crucial importance (portable equipments, consumer, automotive, etc.) The industry structure is given Figure 1 where the food chain from semiconductor industry to electronic equipment industry has shown respectively a 2x and 1.4x increase during the past 5 years and will continue this trend in the coming years. This also shows that we will have more and more semiconductor content in the equipment cost.

Figure 1 : Industry Structure "The food chain in 1996 (in $B)"

- Allows coping with complexity increase on the chip (system integration). - Is mandatory for portable equipments : at least 8 hours autonomy. - Devices quality - Reliability needs to use less logic transitions giving less stress and consequently less failures. - C o s t issue concerns plastic packages versus ceramic packages (25% savings) - Environmental aspects : "Green P.C.'s". 2. SYSTEM E V O L U T I O N The main reason for the evolution mentionned above is the electronics drive for increased productivity (Figure 2) which as been covering the following domains : - from 1970 to 1980 : infrastructure productivity - from 1980 to 1990 : G and A productivity -then moving to individual productivity and concerning more people (and also a larger market)

Figure 2 : Electronics drives productivity 1.4 x

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2 x

Electronic System Sales SBSlB ($920B)

COMPOUNDANNUALGROWTHRATE 1995-2000-% ~ M

Semiconductor Sales ~) $140B ($155B)

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emiconductor Equipment iz)

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(in 5 years) (1)IncludingC a p t (21Inciu~++~.Wafer ~ f-'ab+ Assembly~ncf , TestE'~up~r~Jr~l

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PORTABLEPC

SITE.BASED PBX ENERGY TELECOM TERMINAL INTERACTIVITY INDUSTRIAL FAX MILITARY MAINFRAME 1970.~..1911Q ............1980~19~. . . . . . . . . . . :199Q~2000. . . . . . . . . . . INFRASTRUCTUREI + " ~ & A " l PRODUCTIVITY I PR°t)'JCT=VrCL_i PR°°ucT=~rrv I .................................................... J

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1996 and 1997 Worldwide Electronics Marketplace

Going to higher complexities at chip level also bring particular emphasis on low power design for which the benefits are summarized below :

0167-9317/97/$17.00 © Elsevier Science B.V. All rights reserved. PII: S0167-9317(97)00164-0

In the various phases mentionned above, the compound annual growth rate of these applications has been moving from a few 3 to 5% to 15 to 20% and will continue to increase in the foreseable future. Presently for an average value of semiconductor cost of 14% in the equipment cost, the corresponding

2

~. Borel/Microelectronic Engineering 39 (1997) 1-6

figures for the various significantly different :

market

segments

are

nearly 35% of semiconductor communication equipment.

cost

10% of. semiconductor equipment.

consumer

cost

in

in

These are average values with very different figures for each individual equipment in the corresponding market (a mobile phone has 50% of semiconductor cost).

3. T E C H N O L O G Y E V O L U T I O N

The process technology evolution is key to increase transistor complexity on a single chip and this has been a constant evolution since the early times of the CMOS technology as seen Figure 4 : DRAM complexity has been evolving by a 1.5x factor per year and logic (microprocessor) by a 1.35x factor per year in the time frame 1970 to 1990.

Figure 4 : CMOS integration trend : Moore's law

CMOS integration trend : Moore's law When comparing the application growth and the corresponding semiconductor content (Figure 3) there is a clear indication that semiconductor evolution drives the application ; a lot of new systems appears on the market simply because the semiconductor evolution allows to make them with the good performances and at a price which is acceptable on this market. This is particularly true when such electronic equipments increase significantly productivity in other market sectors, as this is the case for mobile communications allowing services "anywhere, at any time".

Figure 3 : Semiconductors drive the applications

SEMICONDUCTORS DRIVE THE APPLICATIONS 36%

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%d-, 25~' MARKET GROWTH

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Since recently the possibilities of the deep submicron processes (0.251am critical dimensions and 5 to 6 metal interconnect layers) allows to integrate a full system on a chip ; this is due to the possibility of integrating various kinds of memories (static RAMs, DRAMs, and ROMs) with logic and to the design methodology allowing HW and SW codesign on the same chip.

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Process options are extending the range of functionalities that can be put on the silicon as can be seen Figure 5, including analog, mixed analogdigital options and radiofrequency modules and then covering additional application capabilities (like the single chip radiotelephone).

J. Borel/Microelectronic Engineering 39 (1997) 1-6 Figure 5 : CMOS options increase

3

Figure 6 : Delays in deep submicron technologies

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This evolution is not without introducing problems that need to be solved at the design level :

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4. MARKET

- Power consumption can increase at a level where cost and performances are not acceptable. - In low power application the architecture of the system on chip must be carefully optimized to strictly limit power consumption where data is processed, and for the requested throughput needs.

-

Interconnections are more and more contributing to delays, crosstalk and power consumption by adding extra capacitances between wires on the same metal level. An example of their contribution to delays is given figure 6.

TRENDS

The design trends are to decrease as much as possible the power consumption of the system in all application cases : for lower cost (packaging, heat removal). for higher performances (lower silicon temperature). - and obviously to minimize active (and passive) power consumption in portable devices. The market trends are : increasing use of portable and battery operated devices in the consumer and business market place. - exploding growth of hand held electronics. -

A few examples are given below for the computer and telecom market.

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J. Borel/Microelectronic Engineering 39 (1997) 1-6

4.1 Worldwide mobile PC forecast

Figure 8 : Worldwide total handheld market forecast Thousands of Units

Though the mobile PC suffers from an additional cost (500 to 15005) compared to the desktop PC it is forecasted to take from 16 to 18% of the PC market in the time frame 1995-2000. The compound annual growth rate (CAGR) for the total market is 16.9 percent versus 18.9 percent for the mobile PC market (US and Japanese markets are leaders) as seen Figure 7.

8,000 7,000 6,000 5,000 4,000 3,000 2,000

Figure 7 : Total PC shipments and mobile PC shipments as percentage of total

1,000 0 1995

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4.3 Network Computers market forecast

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Network computers use JAVA programming languages to develop distributed applications where platform independence is key. Their recent introduction does not allow a clear view of their market penetration (target price is 5005) ; hand held version will be a great challenge for low power design and optimization. A preliminary forecast is given Figure 9.

2000

Figure 9 : Network computer forecast in-stat 10.0 9.0

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4.2 Worldwide handled market forecast

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The windows CE handled PC will not have a significant effect on notebook PC unit shipments in the 1995-2000 period for presentation and productivity reasons, though their price is attractive (_7_5005). Their market forecast is given Figure 8.

4.0 3.0 2.0 1.0 0.0 1997

1990

1999

2000

J. Borel/Microelectronic Engineering 39 (1997) 1-6 4.4

5

Figure I1 : Power and delay improvement in scaled CMOS

Wireless market forecast

This is an evolving market in 1997 where new solutions will emerge and new markets will appear. The worldwide cellular subscribers evolution by region is given Figure 10 and shows an interesting 15.2%. CAGR over the period (includes only the 800/900MHZ cellular bands without DCS, PCS or PHS).

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Figure 10 : Worldwide cellular subscribers by region (in thousand)

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This market is typically requesting more and more low power design solutions through a combination of technology evolution and architecture optimization for low power. It is moving from analog solution to digital in the considered time frame.

Then the next factor to consider is design optimization, mainly at the architectural level, as shown figure 12 where significant savings can be met.

Figure 12 : HW/SW and Low Power Challenges

Powersavings

5. TRENDS IN LOW POWER - LOW VOLTAGE DESIGN TECHNIQUES

The use of the advanced CMOS process (scaling down below 0.5~tm gate length) is bringing a significant impact on power reduction because of the need to operate at lower voltage (scaling devices conlIaints). This gives very significant gains as seen Figure 11, keeping improving performances even at those low supply voltages.

ArchRec~rdAlgodtlm~ sch~luling o~iml z~tol~ PotentJai gain :10x m l(g)x Implementation optimization Ooglc style, lay out, sizing) Potential gain : 1(1%to 50% Technology optimization (Device engineenng - low VDO) Potential gain : 2x to 23x (Sv---> Iv)

6

J. Borel/Microelectronic Engineering 39 (1997) 1-6

6. C O N C L U S I O N As a conclusion, the low voltage operation of devices is mandatory with deep submicron technologies and brings significant power reduction in complex portable systems. System optimization can also significantly decrease power consumption. The main guidelines can be summarized below : 1. Use hardware resources at minimal performance level to achieve needed throughput. • Optimize for throughput not frequency. • Minimize switching activity (synthesis, retiming of data, glitch elimination ...). • Trade off area and power consumption. • Use adequate clocking scheme to allow multiple clock frequencies on the same chip. • Use CAD tools for low level power optimized design (synthesis, power estimation, statistical design ...). • Possibly use different VDD's on the same chip. • Improve bus architecture. • Use flash memory blocks for zero stand by power consumption. 2. Optimize all consumption:

aspects

to

reduce power

• Optimization of process, versus needs (device, process flow ...). • VDD choices (below max voltage sustained by process). • P/R for min interconnection loads. • Low voltage, low power libraries (minimum device sizes). • I/O pads (peripheral versus area). • Device optimization versus VDD. • Low power SRAMs and flash memory cells. • Packaging for low power (reduced capacitance, flip chip ...).