- Email: [email protected]
Machine fault diagnostics using a transputer network
~
Computers ind. Engng Vol. 30, No. 2, pp. 269-281, 1996
Pergamon MACHINE
0360-8352(95)00171-9
FAULT
DIAGNOSTICS
USING
Copyright© 1996ElsevierScienceLtd Printed in Great Britain.All rightsreserved 0360-8352/96 $15.00+0.00
A TRANSPUTER
NETWORK H S I N - H A O H U A N G 1 and H.-P. BEN W A N G 2 ~Department of Industrial Engineering, National Yun-Lin Polytechnic Institute, Yun-Lin, Taiwan 2Department of Industrial Engineering, Florida A&M University-Florida State University College of Engineering, Tallahassee, FL 32316, U.S.A. Abstract--This paper describes the implementation of a machine-fault diagnostic system on a transputer network. The fault diagnostic system includes an artificial neural network and a fuzzy logic-based hypothesis and test program. The performance of this transputer network is compared with that of a 486 33 MHz personal computer. It is found that a single T800 25 MHz transputer is much slower than the 486 PC. However, the performance is improved substantially when transputers are implemented in parallel. With the hardware cost of transputers continuing to drop, it is economicallyfeasibleto introduce this technology to the shop floor, and to use it to perform many routine tasks.
INTRODUCTION The demand for higher-performance computers has increased significantly, due to the advance in technologies which enable sensors to produce more data, and to make manufacturing equipment, processes and systems, more sophisticated. Almost all the computers on the market today are so-called sequential or von N e u m a n n computers, where each instruction is individually interpreted and executed before the next one may begin. Therefore, the speed of this class of computer system is ultimately determined by the C P U power of the system. The conventional approach in the search for higher performance has been the increase of C P U power of sequential computers (i.e. making the CPU go faster and execute each instruction in less time). Although sequential computers can execute up to 200 MIPS (millions of instructions per second), technology is already pushed to the limit, with small gains in speed costing vast amounts of money, as in the vector machines--supercomputers. This approach, therefore, is not realistic without a major breakthrough in chip-design technology. An alternative for achieving higher performance is the exploration of parallel processing technology. In fact, recent studies show that parallel computing based on PC-class microprocessors outperforms vector machines in performance and cost. Parallel computing utilizes a number of CPUs that perform multiple tasks simultaneously. These CPUs can be linked together in many ways, allowing a wide variety of parallel processing architectures. Commonly, parallel processing architectures are classified into three categories: • Single instruction-stream multiple data-stream (SIMD)--Several CPUs simultaneously execute the same instruction using different data. • Multiple instruction-stream single data-stream (MISD)--Several CPUs simultaneously execute different instructions on the same data. • Multiple instruction-stream multiple data-stream ( M I M D ) - - S e v e r a l CPUs simultaneously execute different instructions on different data. A m o n g them, M I M D appears to be most flexible, since both S I M D and M I S D are subsets of the M I M D architecture. An M I M D machine, known as a transputer network, has been specifically developed for parallel processing over the years. A transputer is a 32-bit computer chip designed and manufactured by I N M O S . It is a complete computer with its own C P U and local memory. Each transputer has four serial links for interprocessor communications. Through these links, a transputer can be connected with other transputer units to form a high-performance, concurrent system. In additon, networks 269
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Hsin-Hao Huang and H.-P. Ben Wang
of transputers can have any desired topology, such as pipeline, tree or array structure, which means that they have the flexibility to suit a wide range of applications. The transputer network is therefore an ideal platform for parallel processing. Over the years, several transputer-based applications have been developed, including robot control and image processing. Examples are the research work of Arabnia and Oliver [l], Peng and Kawamura [2], Zalzala and Morris [3] and Ramaswamy and Bose [4]. Recently, some studies have been conducted to implement neural networks on transputers. Mahadevan and Patnaik [5] implemented an artificial neural network architecture called hi-directional associative memory on a transputer network. Chang and Fallside [6] implemented a back-propagation learning algorithm on transputers. More recently, Foo et al. [7] implemented a back-propagation network on a network of four transputers. Their results showed that transputers helped to improve network learning efficiency. Due to the increased use of robots, automation and more sophisticated machines in today's manufacturing environment, manufacturing companies are making their products at much higher speeds. Under such circumstances, any abnormality in the manufacturing process might result in a tremendous loss of productivity and quality. Hence, today's machine-fault diagnostic systems are required to posses on-line processing capabilities in order to respond quickly to abnormalities in manufacturing. With fast and correct diagnosis, machine failure can be pinpointed immediately, without jeopardizing productivity and quality. In this study, transputer technology was adopted for machine fault diagnostics in order to improve diagnostic efficiency in a cost-effective way. A fault-diagnostic system, which includes a fault-diagnostic neural network and a fuzzy-logic based hypothesis and test procedure, was implemented on a transputer network.
FAULT DIAGNOSTIC SYSTEM Fault diagnostic network (FDN) The objective of using a fault diagnostic network (FDN) is to provide rapid and accurate diagnosis of machine faults. The underlying model of the fault diagnostic network is a modified ARTMAP neural network. The modified ARTMAP network is selected because of its robustness, efficiency and incremental learning capabilities.
TargetOutputVector
Mal~ Field
000
, ...O ART 2
F11
I Input Vector
Fig. 1. ModifiedARTMAP architecture.
.A
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The A R T M A P neural network is an extension of the ART (adaptive resonance theory) network, which autonomously learns to classify arbitrarily ordered vectors into recognition categories based on predictive success. This supervised learning system is built up from a pair of ART modules and a map field which controls the mapping between two ART recognition categories (details can be found in Carpenter et al. [8]). In this study, only one input pattern (i.e. vibration signal) was used for the network. Therefore, a modification of the A R T M A P network was made in order to perform supervised learning. Figure 1 shows the modified A R T M A P architecture, in which the second ART module is replaced by a target output vector provided by the user. In addition, an ART 2 neural network architecture is chosen as the underlying ART module to handle analog input patterns (e.g. vibration signals). The F~ layer of the ART 2 network includes three processing levels which enable the network to separate signal from noise and enhance the contrast of activation signals. Each level performs two computations: integration of intrafield and interfield inputs to that level, and normalization of the integrated activation signal. In Fig. 1, the filled circles represent the gain control systems that normalize the integrated signals. Computational details in this layer are discussed in Appendix A. Each node in the F2 layer represents a particular fault class to be trained. During the network training phase, both the input vector and the target vector are presented to the network. Once the F~ layer receives an input vector from the environment, it starts the normalization process. The normalized input signal is then propagated to the F2 layer. Once the F2 nodes receive the input signal from Ft, the matching score for the F 2 nodes is computed according to the following equation: (1)
#j= ~ p , B , j , i
B~j are the bottom-up weights. Then, the F 2 node with the largest matching score is activated. The activation of F2 is given below:
{d g (J) =
ifthejthF2nodeisactive, otherwise,
(2)
d is a constant between 0 and 1. At this point, the F2 activation is propagated back to the F~ layer, and the vigilance test is carried out to determine whether the top-down signal matches the input pattern. The vigilance test is given as follows: ri =
u~+ cp~
e + II u II + II cp II P > e + IIr [I
-
,
1?
(3) (4)
c is a constant, and 0 < p < 1. If the match fails to pass the vigilance test, a reset is sent to F2, forcing it to deactivate the selected Fz node and search for the next best match. Otherwise, the bottom-up and top-down weights are adapted from the following equations: B,j.(t + 1) = d [ p , - Bij.(t)],
(5)
Ty.i(t + 1) = d i p , - Tj.,(/)],
(6)
j * is the selected F 2 node. Once the ART module is presented with an input vector, it selects and F2 node that passes the vigilance test. Then, the F2 activations are propagated to the map field through the weighted connections between F2 and the map field. The signals received from F2 are calculated using the following equations X = %.. (7) In the map field, a second vigilance is performed to determine the level of match between the predicted output from F2 (X) and the target output pattern (Y). A mismatch between X and Y will
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trigger a map field reset to the underlying ART module. This occurs whenever the following condition holds: -
IIx II < p'. II Y II
(8)
-
p' denotes the associative memory vigilance parameter. If the map field reset occurs, the vigilance of the underlying ART module is raised to prevent the system from making repeated errors. At this point, a reset is sent to F2, forcing it F2 to find the next-best match. This process will continue until the second vigilance test succeeds. Once the second vigilance test is passed, the top-down and bottom-up weights between F~ and F2 are then adapted according to equations (5) and (6) and the weights between F2 and the map field are updated with the following equation: %.~ = Yk.
(9)
For the bottom-up and top-down weights, the weight adaptation process is done iteratively for each training pattern. This is because the normalized input vector, represented by p, is also updated after each update iteration is completed. Then, the new vector p in the F~ layer is used for next weight update iteration [see equations (5) and (6)]. In this work, the weight adaptation iteration is set at 1000. During the diagnosis phase, only an input vector is provided to the network. The F 2 node which passes the F~ vigilance test represents the network's output (i.e. predicted fault class). Hypothesis and test procedure
In this study, the primary technique used for machine fault diagnostics is a fault diagnostic network. As mentioned previously, a network is first trained with examples so that it is able to
Acquire data
• Bearinggeometry I] • Shaftspeed • Normalvibrationsignals
Generate fault signatures
E
model
Generate I referencepatternsI
Unknown _ _ ~ vibrationsignal (Allparameters)
Fuzzy logic i Display all | identifiablefaults| with possibility [
Fig. 2. Fuzzy logic-basedhypothesisand test procedure.
Machine fault diagnostics
273
recognize a pattern when it has characteristics similar to one of the examples. However, there are times when an entirely new pattern has developed, which the network has not "experienced" previously. Under such circumstances, the network will diagnose it as an "unknown pattern". In order to help the human diagnostician pinpoint the exact problem, physical bearing models and fuzzy logic were merged to perform a hypothesis and test task. The reason for using fuzzy logic is that it is one of the most effective tools for taking into consideration uncertainties and ambiguities in the fault reasoning process. Therefore, the hypothesis and test mechanism was implemented based on fuzzy logic methodology. Figure 2 illustrates the fuzzy logic-based hypothesis and test procedure. This procedure is invoked when the FDN encounters an unknown signal. It starts by retrieving bearing geometry parameters, and then the shaft speed, for calculating the corresponding bearing defect frequencies using the equations listed in Appendix B. Each defect signal is combined with normal vibration signals to generate a set of fault signatures. These signatures are then fitted by an AR model to create a set of AR parameters. A reference (virtual) pattern for each bearing defect is generated by averaging a set of AR parameters for that defect. Hypothesis and test are then carried out with the following fuzzy logic methodology. A fuzzy membership function is first assigned to the parameters for each reference pattern. A linear membership function (as shown below) may be used, where a and b are appropriate ranges of the parameter value: 1.0
b
I(x - a )
/J(x)= / ( b _ a ) LO.O
a
(10)
x ~
Then, the fuzzy logic unit hypothesizes possible defects, and tests these hypotheses by comparing the similarity between the reference patterns and the unknown vibration signal. The similarity between pattern X~ and Xj is defined as follows: P
m
-
(x,, L) = l _k=,P
(ll)
k=l
Here, p is the number of AR parameters in the pattern, and m is a weighting factor for increasing the distance between sample reference patterns. A similarity score close to I means that two patterns are very similar, and vice versa. The hypothesis and test procedure described above was programmed to list all identifiable possible faults and to present their similarity indices to the user for further confirmation. TRANSPUTER IMPLEMENTATIONS This section describes the hardware and software configurations of a transputer network. It also discusses various implementations of FDN diagnosis and training procedures and the fuzzy-logic based hypothesis and test procedure on a transputer network. The performance of these procedures on the transputers is evaluated and compared with that on a 486 33 PC.
Hardware and software configurations The parallel processing hardware used in this research is a MicroWay Quadputer board. A Quadputer is a single slot AT form factor board that includes the control logic for four T800 25 transputers, each with 4 MB of external memory for a total of 16 MB on a board. The clock speed of each transputer is 25 MHz. Because each transputer node on the board has its own local memory which cannot be accessed directly by other transputers, it is necessary to communicate directly by actively sending and
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Fig. 3. Physical connections of transputers in the quadputer.
receiving information across the connections between transputers. Figure 3 illustrates the physical connections of transputers on the Quadputer board. It can be seen from this figure that there are four uncommitted links, T1L0, T2L1, T3L2 and T4L3. These links can be used to connect with other transputer boards or to produce multiple connections between two transputers on the same board, except for T1L0, which is dedicated to connection with the host computer. The role of this root transputer is very important since it has to interface with the host computer to perform data I/O functions. In other words, all the information on the other transputers has to be transferred to the root transputer first in order to be displayed on the host computer. In this research, a 486 PC which runs at a speed of 33 MHz is used as the host computer. Because every information transfer has to go through the root transputer, the complexity of communication in the network is increased. A programmer must be fully aware of the detailed communications in the network--such as which node is connected via which link--while implementing a parallel program on the network. In order to resolve this problem, a communication package called Express is selected. With this package, any transputer is able to send/receive messages directly to/from each other, including the host computer, regardless of the specific hardware or configuration involved. There are two programming models provided by the Express; one is the Cubix model and the other is the " H o s t - N o d e " model. The Cubix model is conceptually simple. In this model, the parallel program including data and file I/O, graphics, user interface, etc. has to be loaded and executed on the transputer nodes. The advantage of this approach is that the program is easy to debug, expand and maintain. One disadvantage of this approach is that it may require more memory than necessary of the transputer nodes. The "Host-Node" model entails writing a program to run on the host computer, which coordinates and controls the activities on the transputer nodes. In this model, all the I/Os are handled by the host program, and then sent in messages to the transputer nodes. The advantage of this approach is that the I/O speed is higher; in addition, it is able to provide a more complex graphical user interface. These two properties are crucial to our application. Moreover, it may be wasteful to port the developed graphical user interface and data acquisition codes to the transputer environment under the Cubix model when it may run intact on the host computer. Therefore, the " H o s t - N o d e " model was selected as the programming model throughout this research. In this study, the programming language used for the host PC is Turbo C + + , and the parallel programs for the transputer nodes are written and compiled using Logical Systems C.
Machine fault diagnostics ~ HOST
!
~
|
275
]
First possible fault
r ~ ~ 4
second possible fault
a. One tnmsputer
Fast possible fault HOST Second possible fault
b. Two transputers Fig. 4. (a) One transputer; and (b) two transputers.
Transputer implementation of FDN diagnosis procedure In this study, the diagnosis procedure of the FDN is designed to find the two most likely faults for each pattern that is presented. Searching for these two possible faults is done sequentially on the 486 PC, which means that FDN finds the first F2 node that passes the vigilance test as the first possible fault, then finds the next one as the second possible fault. Figure 4 shows two transputer implementations of the FDN diagnosis procedure: the use of one transputer without dividing the diagnosis task, and the use of two transputers by dividing the diagnosis into two sub-tasks, one for each transputer node. The program for the FDN diagnosis procedure, except for I/O and user interface parts, is loaded into each transputer node. Each node has the same code. The assignment of subtasks to each node is performed by using the following logic: If (env.procnum = = 0){ Search for the first possible fault; If (env.procnum = = 1){ Search for the second possible fault;
};
"env.procnum" presents the identification number of the transputer node. The role of the host PC is to handle file I/O and the user interface. More specially, its tasks include the following: • • • •
read in network parameters and weights, read in input vector, load program onto transputers, broadcast network parameters, top-down and bottom-up weights, input vector, etc. to transputers, • receive the outputs from transputers, • interface with the user, such as information display and input acquisition. Table 1. Diagnosis time comparison of three different methods of implementation
486-33 PC One transputer Two transputers
No. of tests
Maximum time taken (s)
Minimum time taken (s)
Average time taken (s)
SD
5t 5 5
0.11 0.30 0.22
0.11 0.16 0.08
0.11 0.19 0.11
0 0.06 I 0.060
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Hsin-Hao Huang and H.-P. Ben Wang
486-33 PC
Ou~ Transputer
Two
Transputers ! 10
I 20
! 30
! 40
I 50
| 60
I 70
I 80
Hundredths of a Second Fig. 5. C o m p a r i s o n of diagnosis times for five tests.
Table 1 shows the results of comparing three different methods of implementation (i.e. 486 33 PC, one transputer, and two transputers) where the FDN size is 22-10-10 and the network parameters a, b, c, d, e, 0, p and p' are set to be 5, 5, 0.225, 0.8, 0.000001, 0.3, 0.7 and 1, respectively. There are five tests for each method, as shown in the first column. In other words, the FDN is asked to diagnose five different patterns continuously. The rest of the columns represent the time statistic (in s) of this diagnosis session. It can be seen from the table that a single T800-25 transputer is much slower than a 486 PC. This is not only because the CPU of the T800-25 transputer is slower than the 486 PC, but also because there is a communication overhead involved in the transputer implementation. However, the parallel processing advantage of transputers becomes significant when comparing the efficiency of using one transputer to that of using two. As we can see, the efficiency of diagnosis increased about 42% (from 0.19 to 0.11 s). The performance of two transputers in diagnosing five patterns is the same as that of a 486 PC. The deviation of diagnosis time is larger on transputers. As shown in Fig. 5, transputers tend to take more time in the first attempt. This is because all the network information has to be transferred the first time, while only the input vector has to be transferred thereafter.
Transputer implementation of the FDN training procedure The most time-consuming task in the FDN training procedure is the adaptation of bottom-up and top-down weights. This is because the weight adaptation must be performed iteratively for each training pattern. In this section, the procedure of FDN weight adaptation is implemented on a transputer network. Transputer implementations of the FDN training procedure are illustrated in Fig. 6. Different ways of implementation were considered; as in the use of one, two and three transputers to search for an activated F2 node which passes both vigilance tests and performs the weight adaptation procedure. In the first case, all the weight adaptations are performed sequentially on one transputer. In the second case, the update of weights between the F 2 layer and the map field is carried out on one transputer, while bottom-up and top-down weight adaptions are done on the other one. Bottom-up and top-down weights are then further separated to work on two transputers in the last case. As mentioned earlier, the normalized input vector p in the F~ layer is updated every time a weight update iteration is performed. Hence, in transputer node 1, calculations of vector p are performed after the top-down weights are updated. Then, the new updated vector p is sent to transputer node 2 to be used for bottom-up weight adaptation. Therefore, there is a single direction communication link from node 1 to node 2. The programming logic for this procedure on transputers is the same as for the diagnosis. The only difference is that both the target output vector and the weights between the F2 layer and the map field have to be sent to the transputers. Table 2 summarizes the comparison of training times for different methods of implementation. In this table, it is clearly seen that the 486 PC is much faster than the other three transputer implementation configurations. In addition, the improvement
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Machine fault diagnostics
[
HOST
~ 1 ~ [
NODEOl
B
& OneTransputer
i
I°1
NODE 1 I B b. TwoTransputers
NODE 0 [ HOST
NODE 1 [ T
c. Three Transputers
Fig. 6. Transputer implementations of the FDN training procedure.
Table 2. Training time comparison of four different methods of implementation
486-33 PC One transputer Two transputers Three transputers
No. of tests
Maximum time taken (s)
Minimum time taken (s)
Average time taken (s)
SD
5t 5 5 5
|.93 3.49 3.33 5.48
1.65 3.29 3.13 5.27
1.80 3.42 3.25 5.37
0.107 0.084 0.08 I 0.085
of training performance from the use of one transputer to two transputers is not significant (about 5%). The worse training performance happens when three transputers are used. Then, it is almost three times slower than the 486 PC. The reason for which is that there is a large communication overhead involved between nodes 1 and 2. As for the deviation in training time, the 486 PC has a larger deviation. This is because the number of network resets tends to be higher for later training patterns, which means that more training time is needed. However, the deviation for the transputer is not as large as the 486 PC,
48@33
PC
One
Transput~r
Two
Transputers Three
Transputers
I
200
I
400
I
600
I
800
I
I
I
1000 1200 1400
Hundredths of a Second Fig. 7. Comparison of training times for five tests. CAIE 30/2--1
I
1600
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Hsin-Hao Huang and H.-P. Ben Wang
486-33 PC
[]
Node 0
I1
Node
Host
• User&FileI/O ~ Data Transfer Time [ ] Weight Update Time
I 200
I 400
I 600
I 800
I 1000
12~30
I~0
1~0
Hundredths of a Second
Fig. 8. Training components and time distribution.
since there is a communication overhead involved in training; and as shown in Fig. 7, later tests took longer. Another approach was investigated in this research. This approach took advantage of the use of multiple processors by having both the host PC and transputers work in parallel. When the host PC finishes file and data I/O for the first training pattern, it continues to receive the information for the next training pattern from the user, while transputers receive the data from the host PC and start the training process. This approach is illustrated in Fig. 8, in which the two-transputer case is compared with the 486 PC since it has the best performance among three different transputer implementations. The total I/O and training time reduction from this approach after five tests is about 12.6% (from 45.02 to 39.35 s).
Transputer implementation of the hypothesis and test procedure This section discusses transputer implementations of the fuzzy logic-based hypothesis and test procedure. As described previously, the use of this procedure is to perform "deep" fault-reasoning for the patterns that the fault diagnostic network is not able to recognize. The fuzzy logic-based hypothesis and test procedure first generates several reference patterns based on given bearing parameters, machine running condition and baseline vibration signature; then it compares those generated patterns with the given unknown vibration signature to determine the similarity among them. Figure 9 shows implementations of the hypothesis and test procedure using one and three transputers. For the case of using one transputer, the generation and comparison of all six bearing
NODE 0
HOST
I innerrace+ outerrace rollerspin + cagedefect imbalmace+ misaligrmaenl
a. OneTransputer
~
1
NODE 0 ] innermce+outcrrace i
NODE
~
rollerspin+ cagedefect
NODE2 I imbalance+misalignment
b. ThreeTransputers Fig. 9. Transputer implementations of hypothesis and test procedure.
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Machine fault diagnostics
486-33PC One transputer Threetransputers
Table3. Hypothesisand test timecomparisonof threedifferentmethodsof implementation Maximumtimetaken Minimumtimetaken Averagetimetaken No. of tests (s) (s) (s) 5t 0.61 0.56 0.60 5 0.85 0.80 0.83 5 0.39 0.36 0.38
SD 0.022 0.020 0.011
defects are done sequentially on the single transputer. In the case of using three transputers, all the transputers work in parallel, with each one assigned to work on two defect patterns. The host transputer is responsible for I/O and user interface, as well as for sending bearing parameters, machine running conditions etc., to the transputer nodes, and receiving the outputs (i.e. similarity) from all three transputers. The comparison results of the implementations are tabulated in Table 3. As can be seen in the table, the 386 PC is clearly much faster than a single transputer. However, when the task is divided into three pieces and performed by three transputers, the average time reduction is about 37% (from 0.60 down to 0.38 s). Therefore, it is clear that the performance of the hypothesis and the test procedure can be greatly improved if more defects are included in the model, and at the same time, if more transputers are used to implement the procedure. CONCLUSIONS Transputer implementations of F D N training and diagnosis as well as a fuzzy logic-based hypothesis and test procedure were investigated and discussed here in detail. The " H o s t - N o d e " programming model was used in the implementation. In implementing the F D N diagnosis procedure, two cases were investigated: the use of one transputer and the use of two transputers to search for two possible faults. The performance of each transputer implementation was compared with the performance of a 486-33 PC It is found that the 486-33 PC is much faster than a single T800-25 transputer, however, the diagnosis time taken for five tests on the 486 PC is the same as when two transputers are used. As for the implementation of the F D N training procedure, all three cases studied have lower performances than a 486-33 PC. Moreover, the worst training performance occurs when there are communications between transputer nodes, since a huge communication overhead is involved. An alternative approach, where file I/O and the training process work in parallel, was also investigated. The results show a 12.6% reduction in total I/O and training time when compared with the 486 PC. Finally, the implementation of the hypothesis and test procedure was performed. The comparison results indicated that there was a significant saving (about 37%) in processing time when three transputers were used to match an unknown pattern with six reference patterns. It is noted that the saving can be largely increased if more defects are included in the physical model and in addition, if more transputers are used to implement the procedure. The transputer implementations of the fault diagnostic procedure show encouraging results in favor of using parallel processing technology. Further exploration of this technology will focus on the use of more transputers to perform vector and matrix computations in the modified A R T M A P network. In addition, further research will investigate the use of transputers to monitor a number of machines or components simultaneously.
REFERENCES 1. H. R. Arabnia and M. A. Oliver. Transputer network for fast operations on digitized images. Comput. Graphics Forum 8, 3-11 (1989). 2. A. Peng and K. Kawamura. Parallel image processing on a transputer-based system. Proc. 22nd Southeastern Syrup. on System Theory, Cookeville, TN, pp. 235-238 (1990) 3. A. M. S. Zalzala and A. S. Morris. Distributed robot control on transputer network, lEE Proc., Part E: Comput. Dig. Techn. 138, 169-176 (1991). 4. P. S. Ramaswamy and S. C. Bose. Real time distributed adaptive control of industrial robots in a transputer network. Proc. of Manufacturing International--Ml '92, Dallas, TX, pp. 91-99 (1992). 5. I. Mahadevan and L. M. Patnaik. Transputer-based parallel systems for performance evaluation of bidirectional associative memory. Process. International Joint Conf. on Neural Networks (IJCNN), pp. 2478-2483 (1991).
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6. M. W. H. Chang and F. Fallside. Implementation of neural networks for speech recognition on a transputer array. Technical Report, Cambridge University, U.K. (1988). 7. S. K. Foo, P. Saratchandran and N. Sundararajan. A study on implementation of backpropagation neural networks on transputers. Technical Report, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore (1993). 8. G. A. Carpenter, S. Grossberg and J. Reynolds. ARTMAP: supervised real-time learning and classification of nonstationary data by a self-organizing neural network. Neur. Netw. 4, 569-588 (1991). 9. S. Braun, Mechanical Signature Analysis: Theory and Applications. Academic Press, London (1986). 10. J. Sandy. Monitoring and diagnostics for roiling element bearings. Sound vibrat. Jun, 16-20 (1988).
APPENDIX A The following is a list of the equations needed to calculate the activities in the F~ layer of an ART 2 network. Figure AI shows the three processing levels in the F~ layer. The equations for calculating the activities of each element in the processing level are: w i = I i + au i ,
(AI)
wi e + I[w II
(A2)
X i --
vi =f(xi) + bf(q~), ui =
/)i
(A3)
,
(A4)
Pi q~ e + liP [1'
(A5)
Pi = ui + ~ g(J ) T~i,
(A6)
e + IIv II
J
i= a, b = e= g(j) = Tji =
the ith node at the F L layer and a is a constant, constant, constant close to zero, the activation of the jth F2 node, the top-down weight between the jth F2 node and the ith Ft node.
The linear signal function f in equation (A3) is: f(x) =
(A7)
{Ox i f O < ~ x < O ' if x I> 0,
where 0 is a threshold value.
qi .
~
ri
bf(qi
vi
f(xi)l --
~aui
Xi
i
Fig. A1. The F 1 layer of an ART 2 Network.
APPENDIX B The theoretical equations for calculating bearing defect vibration signal frequencies are listed as follows [9, 10]: fr = ~ 0 ( n ) ( l + d cos g )
(BI)
for=~(n)
(B2)
N (1
f°=~6
I
-~
D cos~t , dcos~t),
(B3)
Machine fault diagnostics
N t,O)[l =
(B4) _2
N
N
~m=~0' where N n d D
= = = = = fr = for = f~ = fr~ = fm= fm=
281
shaft speed (CPM), number of rotation elements, rolling element diameter, bearing pitch diameter (to roller center), contact angle, inner race defect, outer race defect, cage defect, roller spin, misalignment, shaft imbalance.
(BS)
(B6)
Computers ind. Engng Vol. 30, No. 2, pp. 269-281, 1996
Pergamon MACHINE
0360-8352(95)00171-9
FAULT
DIAGNOSTICS
USING
Copyright© 1996ElsevierScienceLtd Printed in Great Britain.All rightsreserved 0360-8352/96 $15.00+0.00
A TRANSPUTER
NETWORK H S I N - H A O H U A N G 1 and H.-P. BEN W A N G 2 ~Department of Industrial Engineering, National Yun-Lin Polytechnic Institute, Yun-Lin, Taiwan 2Department of Industrial Engineering, Florida A&M University-Florida State University College of Engineering, Tallahassee, FL 32316, U.S.A. Abstract--This paper describes the implementation of a machine-fault diagnostic system on a transputer network. The fault diagnostic system includes an artificial neural network and a fuzzy logic-based hypothesis and test program. The performance of this transputer network is compared with that of a 486 33 MHz personal computer. It is found that a single T800 25 MHz transputer is much slower than the 486 PC. However, the performance is improved substantially when transputers are implemented in parallel. With the hardware cost of transputers continuing to drop, it is economicallyfeasibleto introduce this technology to the shop floor, and to use it to perform many routine tasks.
INTRODUCTION The demand for higher-performance computers has increased significantly, due to the advance in technologies which enable sensors to produce more data, and to make manufacturing equipment, processes and systems, more sophisticated. Almost all the computers on the market today are so-called sequential or von N e u m a n n computers, where each instruction is individually interpreted and executed before the next one may begin. Therefore, the speed of this class of computer system is ultimately determined by the C P U power of the system. The conventional approach in the search for higher performance has been the increase of C P U power of sequential computers (i.e. making the CPU go faster and execute each instruction in less time). Although sequential computers can execute up to 200 MIPS (millions of instructions per second), technology is already pushed to the limit, with small gains in speed costing vast amounts of money, as in the vector machines--supercomputers. This approach, therefore, is not realistic without a major breakthrough in chip-design technology. An alternative for achieving higher performance is the exploration of parallel processing technology. In fact, recent studies show that parallel computing based on PC-class microprocessors outperforms vector machines in performance and cost. Parallel computing utilizes a number of CPUs that perform multiple tasks simultaneously. These CPUs can be linked together in many ways, allowing a wide variety of parallel processing architectures. Commonly, parallel processing architectures are classified into three categories: • Single instruction-stream multiple data-stream (SIMD)--Several CPUs simultaneously execute the same instruction using different data. • Multiple instruction-stream single data-stream (MISD)--Several CPUs simultaneously execute different instructions on the same data. • Multiple instruction-stream multiple data-stream ( M I M D ) - - S e v e r a l CPUs simultaneously execute different instructions on different data. A m o n g them, M I M D appears to be most flexible, since both S I M D and M I S D are subsets of the M I M D architecture. An M I M D machine, known as a transputer network, has been specifically developed for parallel processing over the years. A transputer is a 32-bit computer chip designed and manufactured by I N M O S . It is a complete computer with its own C P U and local memory. Each transputer has four serial links for interprocessor communications. Through these links, a transputer can be connected with other transputer units to form a high-performance, concurrent system. In additon, networks 269
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of transputers can have any desired topology, such as pipeline, tree or array structure, which means that they have the flexibility to suit a wide range of applications. The transputer network is therefore an ideal platform for parallel processing. Over the years, several transputer-based applications have been developed, including robot control and image processing. Examples are the research work of Arabnia and Oliver [l], Peng and Kawamura [2], Zalzala and Morris [3] and Ramaswamy and Bose [4]. Recently, some studies have been conducted to implement neural networks on transputers. Mahadevan and Patnaik [5] implemented an artificial neural network architecture called hi-directional associative memory on a transputer network. Chang and Fallside [6] implemented a back-propagation learning algorithm on transputers. More recently, Foo et al. [7] implemented a back-propagation network on a network of four transputers. Their results showed that transputers helped to improve network learning efficiency. Due to the increased use of robots, automation and more sophisticated machines in today's manufacturing environment, manufacturing companies are making their products at much higher speeds. Under such circumstances, any abnormality in the manufacturing process might result in a tremendous loss of productivity and quality. Hence, today's machine-fault diagnostic systems are required to posses on-line processing capabilities in order to respond quickly to abnormalities in manufacturing. With fast and correct diagnosis, machine failure can be pinpointed immediately, without jeopardizing productivity and quality. In this study, transputer technology was adopted for machine fault diagnostics in order to improve diagnostic efficiency in a cost-effective way. A fault-diagnostic system, which includes a fault-diagnostic neural network and a fuzzy-logic based hypothesis and test procedure, was implemented on a transputer network.
FAULT DIAGNOSTIC SYSTEM Fault diagnostic network (FDN) The objective of using a fault diagnostic network (FDN) is to provide rapid and accurate diagnosis of machine faults. The underlying model of the fault diagnostic network is a modified ARTMAP neural network. The modified ARTMAP network is selected because of its robustness, efficiency and incremental learning capabilities.
TargetOutputVector
Mal~ Field
000
, ...O ART 2
F11
I Input Vector
Fig. 1. ModifiedARTMAP architecture.
.A
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The A R T M A P neural network is an extension of the ART (adaptive resonance theory) network, which autonomously learns to classify arbitrarily ordered vectors into recognition categories based on predictive success. This supervised learning system is built up from a pair of ART modules and a map field which controls the mapping between two ART recognition categories (details can be found in Carpenter et al. [8]). In this study, only one input pattern (i.e. vibration signal) was used for the network. Therefore, a modification of the A R T M A P network was made in order to perform supervised learning. Figure 1 shows the modified A R T M A P architecture, in which the second ART module is replaced by a target output vector provided by the user. In addition, an ART 2 neural network architecture is chosen as the underlying ART module to handle analog input patterns (e.g. vibration signals). The F~ layer of the ART 2 network includes three processing levels which enable the network to separate signal from noise and enhance the contrast of activation signals. Each level performs two computations: integration of intrafield and interfield inputs to that level, and normalization of the integrated activation signal. In Fig. 1, the filled circles represent the gain control systems that normalize the integrated signals. Computational details in this layer are discussed in Appendix A. Each node in the F2 layer represents a particular fault class to be trained. During the network training phase, both the input vector and the target vector are presented to the network. Once the F~ layer receives an input vector from the environment, it starts the normalization process. The normalized input signal is then propagated to the F2 layer. Once the F2 nodes receive the input signal from Ft, the matching score for the F 2 nodes is computed according to the following equation: (1)
#j= ~ p , B , j , i
B~j are the bottom-up weights. Then, the F 2 node with the largest matching score is activated. The activation of F2 is given below:
{d g (J) =
ifthejthF2nodeisactive, otherwise,
(2)
d is a constant between 0 and 1. At this point, the F2 activation is propagated back to the F~ layer, and the vigilance test is carried out to determine whether the top-down signal matches the input pattern. The vigilance test is given as follows: ri =
u~+ cp~
e + II u II + II cp II P > e + IIr [I
-
,
1?
(3) (4)
c is a constant, and 0 < p < 1. If the match fails to pass the vigilance test, a reset is sent to F2, forcing it to deactivate the selected Fz node and search for the next best match. Otherwise, the bottom-up and top-down weights are adapted from the following equations: B,j.(t + 1) = d [ p , - Bij.(t)],
(5)
Ty.i(t + 1) = d i p , - Tj.,(/)],
(6)
j * is the selected F 2 node. Once the ART module is presented with an input vector, it selects and F2 node that passes the vigilance test. Then, the F2 activations are propagated to the map field through the weighted connections between F2 and the map field. The signals received from F2 are calculated using the following equations X = %.. (7) In the map field, a second vigilance is performed to determine the level of match between the predicted output from F2 (X) and the target output pattern (Y). A mismatch between X and Y will
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trigger a map field reset to the underlying ART module. This occurs whenever the following condition holds: -
IIx II < p'. II Y II
(8)
-
p' denotes the associative memory vigilance parameter. If the map field reset occurs, the vigilance of the underlying ART module is raised to prevent the system from making repeated errors. At this point, a reset is sent to F2, forcing it F2 to find the next-best match. This process will continue until the second vigilance test succeeds. Once the second vigilance test is passed, the top-down and bottom-up weights between F~ and F2 are then adapted according to equations (5) and (6) and the weights between F2 and the map field are updated with the following equation: %.~ = Yk.
(9)
For the bottom-up and top-down weights, the weight adaptation process is done iteratively for each training pattern. This is because the normalized input vector, represented by p, is also updated after each update iteration is completed. Then, the new vector p in the F~ layer is used for next weight update iteration [see equations (5) and (6)]. In this work, the weight adaptation iteration is set at 1000. During the diagnosis phase, only an input vector is provided to the network. The F 2 node which passes the F~ vigilance test represents the network's output (i.e. predicted fault class). Hypothesis and test procedure
In this study, the primary technique used for machine fault diagnostics is a fault diagnostic network. As mentioned previously, a network is first trained with examples so that it is able to
Acquire data
• Bearinggeometry I] • Shaftspeed • Normalvibrationsignals
Generate fault signatures
E
model
Generate I referencepatternsI
Unknown _ _ ~ vibrationsignal (Allparameters)
Fuzzy logic i Display all | identifiablefaults| with possibility [
Fig. 2. Fuzzy logic-basedhypothesisand test procedure.
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recognize a pattern when it has characteristics similar to one of the examples. However, there are times when an entirely new pattern has developed, which the network has not "experienced" previously. Under such circumstances, the network will diagnose it as an "unknown pattern". In order to help the human diagnostician pinpoint the exact problem, physical bearing models and fuzzy logic were merged to perform a hypothesis and test task. The reason for using fuzzy logic is that it is one of the most effective tools for taking into consideration uncertainties and ambiguities in the fault reasoning process. Therefore, the hypothesis and test mechanism was implemented based on fuzzy logic methodology. Figure 2 illustrates the fuzzy logic-based hypothesis and test procedure. This procedure is invoked when the FDN encounters an unknown signal. It starts by retrieving bearing geometry parameters, and then the shaft speed, for calculating the corresponding bearing defect frequencies using the equations listed in Appendix B. Each defect signal is combined with normal vibration signals to generate a set of fault signatures. These signatures are then fitted by an AR model to create a set of AR parameters. A reference (virtual) pattern for each bearing defect is generated by averaging a set of AR parameters for that defect. Hypothesis and test are then carried out with the following fuzzy logic methodology. A fuzzy membership function is first assigned to the parameters for each reference pattern. A linear membership function (as shown below) may be used, where a and b are appropriate ranges of the parameter value: 1.0
b
I(x - a )
/J(x)= / ( b _ a ) LO.O
a
(10)
x ~
Then, the fuzzy logic unit hypothesizes possible defects, and tests these hypotheses by comparing the similarity between the reference patterns and the unknown vibration signal. The similarity between pattern X~ and Xj is defined as follows: P
m
-
(x,, L) = l _k=,P
(ll)
k=l
Here, p is the number of AR parameters in the pattern, and m is a weighting factor for increasing the distance between sample reference patterns. A similarity score close to I means that two patterns are very similar, and vice versa. The hypothesis and test procedure described above was programmed to list all identifiable possible faults and to present their similarity indices to the user for further confirmation. TRANSPUTER IMPLEMENTATIONS This section describes the hardware and software configurations of a transputer network. It also discusses various implementations of FDN diagnosis and training procedures and the fuzzy-logic based hypothesis and test procedure on a transputer network. The performance of these procedures on the transputers is evaluated and compared with that on a 486 33 PC.
Hardware and software configurations The parallel processing hardware used in this research is a MicroWay Quadputer board. A Quadputer is a single slot AT form factor board that includes the control logic for four T800 25 transputers, each with 4 MB of external memory for a total of 16 MB on a board. The clock speed of each transputer is 25 MHz. Because each transputer node on the board has its own local memory which cannot be accessed directly by other transputers, it is necessary to communicate directly by actively sending and
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Fig. 3. Physical connections of transputers in the quadputer.
receiving information across the connections between transputers. Figure 3 illustrates the physical connections of transputers on the Quadputer board. It can be seen from this figure that there are four uncommitted links, T1L0, T2L1, T3L2 and T4L3. These links can be used to connect with other transputer boards or to produce multiple connections between two transputers on the same board, except for T1L0, which is dedicated to connection with the host computer. The role of this root transputer is very important since it has to interface with the host computer to perform data I/O functions. In other words, all the information on the other transputers has to be transferred to the root transputer first in order to be displayed on the host computer. In this research, a 486 PC which runs at a speed of 33 MHz is used as the host computer. Because every information transfer has to go through the root transputer, the complexity of communication in the network is increased. A programmer must be fully aware of the detailed communications in the network--such as which node is connected via which link--while implementing a parallel program on the network. In order to resolve this problem, a communication package called Express is selected. With this package, any transputer is able to send/receive messages directly to/from each other, including the host computer, regardless of the specific hardware or configuration involved. There are two programming models provided by the Express; one is the Cubix model and the other is the " H o s t - N o d e " model. The Cubix model is conceptually simple. In this model, the parallel program including data and file I/O, graphics, user interface, etc. has to be loaded and executed on the transputer nodes. The advantage of this approach is that the program is easy to debug, expand and maintain. One disadvantage of this approach is that it may require more memory than necessary of the transputer nodes. The "Host-Node" model entails writing a program to run on the host computer, which coordinates and controls the activities on the transputer nodes. In this model, all the I/Os are handled by the host program, and then sent in messages to the transputer nodes. The advantage of this approach is that the I/O speed is higher; in addition, it is able to provide a more complex graphical user interface. These two properties are crucial to our application. Moreover, it may be wasteful to port the developed graphical user interface and data acquisition codes to the transputer environment under the Cubix model when it may run intact on the host computer. Therefore, the " H o s t - N o d e " model was selected as the programming model throughout this research. In this study, the programming language used for the host PC is Turbo C + + , and the parallel programs for the transputer nodes are written and compiled using Logical Systems C.
Machine fault diagnostics ~ HOST
!
~
|
275
]
First possible fault
r ~ ~ 4
second possible fault
a. One tnmsputer
Fast possible fault HOST Second possible fault
b. Two transputers Fig. 4. (a) One transputer; and (b) two transputers.
Transputer implementation of FDN diagnosis procedure In this study, the diagnosis procedure of the FDN is designed to find the two most likely faults for each pattern that is presented. Searching for these two possible faults is done sequentially on the 486 PC, which means that FDN finds the first F2 node that passes the vigilance test as the first possible fault, then finds the next one as the second possible fault. Figure 4 shows two transputer implementations of the FDN diagnosis procedure: the use of one transputer without dividing the diagnosis task, and the use of two transputers by dividing the diagnosis into two sub-tasks, one for each transputer node. The program for the FDN diagnosis procedure, except for I/O and user interface parts, is loaded into each transputer node. Each node has the same code. The assignment of subtasks to each node is performed by using the following logic: If (env.procnum = = 0){ Search for the first possible fault; If (env.procnum = = 1){ Search for the second possible fault;
};
"env.procnum" presents the identification number of the transputer node. The role of the host PC is to handle file I/O and the user interface. More specially, its tasks include the following: • • • •
read in network parameters and weights, read in input vector, load program onto transputers, broadcast network parameters, top-down and bottom-up weights, input vector, etc. to transputers, • receive the outputs from transputers, • interface with the user, such as information display and input acquisition. Table 1. Diagnosis time comparison of three different methods of implementation
486-33 PC One transputer Two transputers
No. of tests
Maximum time taken (s)
Minimum time taken (s)
Average time taken (s)
SD
5t 5 5
0.11 0.30 0.22
0.11 0.16 0.08
0.11 0.19 0.11
0 0.06 I 0.060
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486-33 PC
Ou~ Transputer
Two
Transputers ! 10
I 20
! 30
! 40
I 50
| 60
I 70
I 80
Hundredths of a Second Fig. 5. C o m p a r i s o n of diagnosis times for five tests.
Table 1 shows the results of comparing three different methods of implementation (i.e. 486 33 PC, one transputer, and two transputers) where the FDN size is 22-10-10 and the network parameters a, b, c, d, e, 0, p and p' are set to be 5, 5, 0.225, 0.8, 0.000001, 0.3, 0.7 and 1, respectively. There are five tests for each method, as shown in the first column. In other words, the FDN is asked to diagnose five different patterns continuously. The rest of the columns represent the time statistic (in s) of this diagnosis session. It can be seen from the table that a single T800-25 transputer is much slower than a 486 PC. This is not only because the CPU of the T800-25 transputer is slower than the 486 PC, but also because there is a communication overhead involved in the transputer implementation. However, the parallel processing advantage of transputers becomes significant when comparing the efficiency of using one transputer to that of using two. As we can see, the efficiency of diagnosis increased about 42% (from 0.19 to 0.11 s). The performance of two transputers in diagnosing five patterns is the same as that of a 486 PC. The deviation of diagnosis time is larger on transputers. As shown in Fig. 5, transputers tend to take more time in the first attempt. This is because all the network information has to be transferred the first time, while only the input vector has to be transferred thereafter.
Transputer implementation of the FDN training procedure The most time-consuming task in the FDN training procedure is the adaptation of bottom-up and top-down weights. This is because the weight adaptation must be performed iteratively for each training pattern. In this section, the procedure of FDN weight adaptation is implemented on a transputer network. Transputer implementations of the FDN training procedure are illustrated in Fig. 6. Different ways of implementation were considered; as in the use of one, two and three transputers to search for an activated F2 node which passes both vigilance tests and performs the weight adaptation procedure. In the first case, all the weight adaptations are performed sequentially on one transputer. In the second case, the update of weights between the F 2 layer and the map field is carried out on one transputer, while bottom-up and top-down weight adaptions are done on the other one. Bottom-up and top-down weights are then further separated to work on two transputers in the last case. As mentioned earlier, the normalized input vector p in the F~ layer is updated every time a weight update iteration is performed. Hence, in transputer node 1, calculations of vector p are performed after the top-down weights are updated. Then, the new updated vector p is sent to transputer node 2 to be used for bottom-up weight adaptation. Therefore, there is a single direction communication link from node 1 to node 2. The programming logic for this procedure on transputers is the same as for the diagnosis. The only difference is that both the target output vector and the weights between the F2 layer and the map field have to be sent to the transputers. Table 2 summarizes the comparison of training times for different methods of implementation. In this table, it is clearly seen that the 486 PC is much faster than the other three transputer implementation configurations. In addition, the improvement
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Machine fault diagnostics
[
HOST
~ 1 ~ [
NODEOl
B
& OneTransputer
i
I°1
NODE 1 I B b. TwoTransputers
NODE 0 [ HOST
NODE 1 [ T
c. Three Transputers
Fig. 6. Transputer implementations of the FDN training procedure.
Table 2. Training time comparison of four different methods of implementation
486-33 PC One transputer Two transputers Three transputers
No. of tests
Maximum time taken (s)
Minimum time taken (s)
Average time taken (s)
SD
5t 5 5 5
|.93 3.49 3.33 5.48
1.65 3.29 3.13 5.27
1.80 3.42 3.25 5.37
0.107 0.084 0.08 I 0.085
of training performance from the use of one transputer to two transputers is not significant (about 5%). The worse training performance happens when three transputers are used. Then, it is almost three times slower than the 486 PC. The reason for which is that there is a large communication overhead involved between nodes 1 and 2. As for the deviation in training time, the 486 PC has a larger deviation. This is because the number of network resets tends to be higher for later training patterns, which means that more training time is needed. However, the deviation for the transputer is not as large as the 486 PC,
48@33
PC
One
Transput~r
Two
Transputers Three
Transputers
I
200
I
400
I
600
I
800
I
I
I
1000 1200 1400
Hundredths of a Second Fig. 7. Comparison of training times for five tests. CAIE 30/2--1
I
1600
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486-33 PC
[]
Node 0
I1
Node
Host
• User&FileI/O ~ Data Transfer Time [ ] Weight Update Time
I 200
I 400
I 600
I 800
I 1000
12~30
I~0
1~0
Hundredths of a Second
Fig. 8. Training components and time distribution.
since there is a communication overhead involved in training; and as shown in Fig. 7, later tests took longer. Another approach was investigated in this research. This approach took advantage of the use of multiple processors by having both the host PC and transputers work in parallel. When the host PC finishes file and data I/O for the first training pattern, it continues to receive the information for the next training pattern from the user, while transputers receive the data from the host PC and start the training process. This approach is illustrated in Fig. 8, in which the two-transputer case is compared with the 486 PC since it has the best performance among three different transputer implementations. The total I/O and training time reduction from this approach after five tests is about 12.6% (from 45.02 to 39.35 s).
Transputer implementation of the hypothesis and test procedure This section discusses transputer implementations of the fuzzy logic-based hypothesis and test procedure. As described previously, the use of this procedure is to perform "deep" fault-reasoning for the patterns that the fault diagnostic network is not able to recognize. The fuzzy logic-based hypothesis and test procedure first generates several reference patterns based on given bearing parameters, machine running condition and baseline vibration signature; then it compares those generated patterns with the given unknown vibration signature to determine the similarity among them. Figure 9 shows implementations of the hypothesis and test procedure using one and three transputers. For the case of using one transputer, the generation and comparison of all six bearing
NODE 0
HOST
I innerrace+ outerrace rollerspin + cagedefect imbalmace+ misaligrmaenl
a. OneTransputer
~
1
NODE 0 ] innermce+outcrrace i
NODE
~
rollerspin+ cagedefect
NODE2 I imbalance+misalignment
b. ThreeTransputers Fig. 9. Transputer implementations of hypothesis and test procedure.
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Machine fault diagnostics
486-33PC One transputer Threetransputers
Table3. Hypothesisand test timecomparisonof threedifferentmethodsof implementation Maximumtimetaken Minimumtimetaken Averagetimetaken No. of tests (s) (s) (s) 5t 0.61 0.56 0.60 5 0.85 0.80 0.83 5 0.39 0.36 0.38
SD 0.022 0.020 0.011
defects are done sequentially on the single transputer. In the case of using three transputers, all the transputers work in parallel, with each one assigned to work on two defect patterns. The host transputer is responsible for I/O and user interface, as well as for sending bearing parameters, machine running conditions etc., to the transputer nodes, and receiving the outputs (i.e. similarity) from all three transputers. The comparison results of the implementations are tabulated in Table 3. As can be seen in the table, the 386 PC is clearly much faster than a single transputer. However, when the task is divided into three pieces and performed by three transputers, the average time reduction is about 37% (from 0.60 down to 0.38 s). Therefore, it is clear that the performance of the hypothesis and the test procedure can be greatly improved if more defects are included in the model, and at the same time, if more transputers are used to implement the procedure. CONCLUSIONS Transputer implementations of F D N training and diagnosis as well as a fuzzy logic-based hypothesis and test procedure were investigated and discussed here in detail. The " H o s t - N o d e " programming model was used in the implementation. In implementing the F D N diagnosis procedure, two cases were investigated: the use of one transputer and the use of two transputers to search for two possible faults. The performance of each transputer implementation was compared with the performance of a 486-33 PC It is found that the 486-33 PC is much faster than a single T800-25 transputer, however, the diagnosis time taken for five tests on the 486 PC is the same as when two transputers are used. As for the implementation of the F D N training procedure, all three cases studied have lower performances than a 486-33 PC. Moreover, the worst training performance occurs when there are communications between transputer nodes, since a huge communication overhead is involved. An alternative approach, where file I/O and the training process work in parallel, was also investigated. The results show a 12.6% reduction in total I/O and training time when compared with the 486 PC. Finally, the implementation of the hypothesis and test procedure was performed. The comparison results indicated that there was a significant saving (about 37%) in processing time when three transputers were used to match an unknown pattern with six reference patterns. It is noted that the saving can be largely increased if more defects are included in the physical model and in addition, if more transputers are used to implement the procedure. The transputer implementations of the fault diagnostic procedure show encouraging results in favor of using parallel processing technology. Further exploration of this technology will focus on the use of more transputers to perform vector and matrix computations in the modified A R T M A P network. In addition, further research will investigate the use of transputers to monitor a number of machines or components simultaneously.
REFERENCES 1. H. R. Arabnia and M. A. Oliver. Transputer network for fast operations on digitized images. Comput. Graphics Forum 8, 3-11 (1989). 2. A. Peng and K. Kawamura. Parallel image processing on a transputer-based system. Proc. 22nd Southeastern Syrup. on System Theory, Cookeville, TN, pp. 235-238 (1990) 3. A. M. S. Zalzala and A. S. Morris. Distributed robot control on transputer network, lEE Proc., Part E: Comput. Dig. Techn. 138, 169-176 (1991). 4. P. S. Ramaswamy and S. C. Bose. Real time distributed adaptive control of industrial robots in a transputer network. Proc. of Manufacturing International--Ml '92, Dallas, TX, pp. 91-99 (1992). 5. I. Mahadevan and L. M. Patnaik. Transputer-based parallel systems for performance evaluation of bidirectional associative memory. Process. International Joint Conf. on Neural Networks (IJCNN), pp. 2478-2483 (1991).
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6. M. W. H. Chang and F. Fallside. Implementation of neural networks for speech recognition on a transputer array. Technical Report, Cambridge University, U.K. (1988). 7. S. K. Foo, P. Saratchandran and N. Sundararajan. A study on implementation of backpropagation neural networks on transputers. Technical Report, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore (1993). 8. G. A. Carpenter, S. Grossberg and J. Reynolds. ARTMAP: supervised real-time learning and classification of nonstationary data by a self-organizing neural network. Neur. Netw. 4, 569-588 (1991). 9. S. Braun, Mechanical Signature Analysis: Theory and Applications. Academic Press, London (1986). 10. J. Sandy. Monitoring and diagnostics for roiling element bearings. Sound vibrat. Jun, 16-20 (1988).
APPENDIX A The following is a list of the equations needed to calculate the activities in the F~ layer of an ART 2 network. Figure AI shows the three processing levels in the F~ layer. The equations for calculating the activities of each element in the processing level are: w i = I i + au i ,
(AI)
wi e + I[w II
(A2)
X i --
vi =f(xi) + bf(q~), ui =
/)i
(A3)
,
(A4)
Pi q~ e + liP [1'
(A5)
Pi = ui + ~ g(J ) T~i,
(A6)
e + IIv II
J
i= a, b = e= g(j) = Tji =
the ith node at the F L layer and a is a constant, constant, constant close to zero, the activation of the jth F2 node, the top-down weight between the jth F2 node and the ith Ft node.
The linear signal function f in equation (A3) is: f(x) =
(A7)
{Ox i f O < ~ x < O ' if x I> 0,
where 0 is a threshold value.
qi .
~
ri
bf(qi
vi
f(xi)l --
~aui
Xi
i
Fig. A1. The F 1 layer of an ART 2 Network.
APPENDIX B The theoretical equations for calculating bearing defect vibration signal frequencies are listed as follows [9, 10]: fr = ~ 0 ( n ) ( l + d cos g )
(BI)
for=~(n)
(B2)
N (1
f°=~6
I
-~
D cos~t , dcos~t),
(B3)
Machine fault diagnostics
N t,O)[l =
(B4) _2
N
N
~m=~0' where N n d D
= = = = = fr = for = f~ = fr~ = fm= fm=
281
shaft speed (CPM), number of rotation elements, rolling element diameter, bearing pitch diameter (to roller center), contact angle, inner race defect, outer race defect, cage defect, roller spin, misalignment, shaft imbalance.
(BS)
(B6)