- Email: [email protected]
Makers expect ASICs to reverse computer slump
292
World Abstracts on Microelectronics and Reliability
reliability should be analyzed to determine the optimal balance between reliable and unreliable protocols. Static redundancy can be more reliable than dynamic redundancy if the failure-detection time is large. An efficient algorithm to solve inter-programming problems arising in system-reliability design. KRISHNA BEHARIMISRA and USHA SHARMA.IEEE Trans. Reliab. 40(1), 81 (1991). A simple and efficient technique for solving integer-programming problems that normally arise in system-reliability design, is introduced. The algorithm is based on functional evaluations and a limited search close to the boundary of resources. Our experience shows that it is fast to solve even a very large system problem. We believe that it can be effectively used with other general integer programming or Zero-One programming problems from the operations research area, A. consecutive-k-out-of-n:G system: the mirror image of a consecutive-k-out-of-n:F system. WAY Kuo, WEIX1NG ZHANG and MINGJIAN ZUO. IEEE Trans. Reliab. 39(2), 244 (1990). A consecutive-k-out-of-n:F (consecutive-kout-of-n :G) system consists of an ordered sequence of n components such that the system is failed (good) if, and only if, at least k consecutive components in the
system are failed (good). This research studies the relationship between the consecutive-k-out-of-n :F system and the consecutive-k-out-of-n :G system, develops theorems for such systems, and applies available results for one type of system to the other. The topics include system reliability, reliability bounds, component reliability importance, and optimal system design. A case study illustrates reliability analysis and optimal design of a train operation system. An optimal configuration rule is suggested by use of the Birnbaum importance index. The mean time-to-failure of some special series-parailel arrays. SRINIVAS IYER. IEEE Trans. Reliab. 40(1), 20 (1991): Series-parallel (parallel-series) arrays consist of several subsystems in series (parallel) where each subsystem has several components in parallel (series). Each unit and the system itself is subject to two modes of failure, open and short, and all component states are mutually independent. Each item has the same failuretime distribution and the probability of short failure of an item, given the failure of the item, is a constant. It is shown that the distribution of the lifetime of the system is a linear combination of the distributions of lifetimes of systems, each of which is an ordinary series or parallel system of mutually independent components.
4. M I C R O E L E C T R O N I C S - - G E N E R A L IC tester industry gears up for large-memory DRAMs. JEE (Japan), 48 (May 1990). Production of IC testers passed the ¥ 100 billion mark for the first time in 1989. Makers' investment plans remain vigorous as a fast recovery is expected from the current semiconductor device adjustment period. An average growth of nearly 10% is forecast for the mid-range. For memory testers, multiple simultaneous testing is most effective for meeting the larger 4M-bit DRAM production and the increasing number of functions per device. As devices become more complex and multi-functional, the per-pin test architecture is a useful strategy for increasing the logic tester throughput. Electronic system packaging: the search for manufacturing the optimum in a sea of constraints. LARRY L. MORESCO. IEEE Trans. Compon. Hybrids mfg Technol. 13(3), 494 (1990). Generally, the design of "single-chip packages" is equivalent to writing a book with incomplete sentences. Manufacturing electronic systems is a multicomponent, multichip, hybrid design process which spans the life of the product. The design constraint list is not limitless, but if incomplete, can lead to economic loss for the product. This paper details some of the constraints that affect system performance, reliability, materials selection, and the assembly of the product. The electronic constraints include, chip crossing delay, fan out (number of receivers on a driven net), cross-talk (unwanted electromagnetic coupling between independent signal lines and power supplies), d.c. voltage drop, the number of simultaneously switched line drivers (NSSDs), and reflections of signal waves from discontinuities in transmission line networks. The power dissipation constraints include maximum junction temperature, ambient temperature and pressure drop conditions, and component-to-component temperature variation. The cost constraints include materials, fabrication, and assembly. Some of the mathematical constraints are defined along with the coupling between them, optimum solutions are shown graphically. The ability to resolve the system manufacturing constraints through optimization will determine the final success of a product. Makers expect ASICs to reverse computer slump. JEE (Japan), 34 (May 1990). The great slump in sales of mainframe computers and sluggish demand for personal
computers since last year have greatly affected sales of semiconductor products in the United States, and observers believe that the U.S. semiconductor market has hit the bottom of the silicon cycle. Silicon micromechanics: sensors and actuators on a chip. ROGER T. HOWE et al. IEEE Spectrum, 29 (July 1990). Remarkable advances in sculpting minute sensors, motors, valves, and pumps from silicon could affect such diverse fields as optical signal processing and magnetic recording technology. A look at optoelectronic integrated circuits. Nonuo SUZUK1. JEE (Japan), 56 (April 1990). Optoelectronic integrated circuits (OEICs) provide high-level performance by monolithically integrating optoelectronic devices. These circuits will find applications in optical communication, interconnection and information processing. However, because these circuits are produced by integrating different types of devices, various concessions must be made in terms of device structure and production processes. Potential and problems of high-temperature electronics and CMOS integrated circuits (25-250°C)--an overview. F. S. SHOUCAIR. Mieroelectron. J. 22(2), 39 (1991). A brief overview of high-temperature integrated circuit technologies is presented. General comparisons of the hightemperature performance and relative merits of several semiconductor materials, technologies, devices and digital and analog circuits are highlighted. Important advances and developments of the last three decades are outlined, which reflect the prominence of MOSFET technologies. Shortcomings of the temperature models in standard IC computer-aided-design (CAD) programs are summarized and a discussion of near- and long-term research and development needs for high-temperature integrated electronics is presented. Supply formats change with chip use trends. JEE (Japan), 42 (October 1990). Owing to the development of a variety of chip parts, chip manufacturers are changing the formats in which chip parts are supplied to users. While tape formats remain popular, taping techniques have altered
World Abstracts on Microelectronics and Reliability
reliability should be analyzed to determine the optimal balance between reliable and unreliable protocols. Static redundancy can be more reliable than dynamic redundancy if the failure-detection time is large. An efficient algorithm to solve inter-programming problems arising in system-reliability design. KRISHNA BEHARIMISRA and USHA SHARMA.IEEE Trans. Reliab. 40(1), 81 (1991). A simple and efficient technique for solving integer-programming problems that normally arise in system-reliability design, is introduced. The algorithm is based on functional evaluations and a limited search close to the boundary of resources. Our experience shows that it is fast to solve even a very large system problem. We believe that it can be effectively used with other general integer programming or Zero-One programming problems from the operations research area, A. consecutive-k-out-of-n:G system: the mirror image of a consecutive-k-out-of-n:F system. WAY Kuo, WEIX1NG ZHANG and MINGJIAN ZUO. IEEE Trans. Reliab. 39(2), 244 (1990). A consecutive-k-out-of-n:F (consecutive-kout-of-n :G) system consists of an ordered sequence of n components such that the system is failed (good) if, and only if, at least k consecutive components in the
system are failed (good). This research studies the relationship between the consecutive-k-out-of-n :F system and the consecutive-k-out-of-n :G system, develops theorems for such systems, and applies available results for one type of system to the other. The topics include system reliability, reliability bounds, component reliability importance, and optimal system design. A case study illustrates reliability analysis and optimal design of a train operation system. An optimal configuration rule is suggested by use of the Birnbaum importance index. The mean time-to-failure of some special series-parailel arrays. SRINIVAS IYER. IEEE Trans. Reliab. 40(1), 20 (1991): Series-parallel (parallel-series) arrays consist of several subsystems in series (parallel) where each subsystem has several components in parallel (series). Each unit and the system itself is subject to two modes of failure, open and short, and all component states are mutually independent. Each item has the same failuretime distribution and the probability of short failure of an item, given the failure of the item, is a constant. It is shown that the distribution of the lifetime of the system is a linear combination of the distributions of lifetimes of systems, each of which is an ordinary series or parallel system of mutually independent components.
4. M I C R O E L E C T R O N I C S - - G E N E R A L IC tester industry gears up for large-memory DRAMs. JEE (Japan), 48 (May 1990). Production of IC testers passed the ¥ 100 billion mark for the first time in 1989. Makers' investment plans remain vigorous as a fast recovery is expected from the current semiconductor device adjustment period. An average growth of nearly 10% is forecast for the mid-range. For memory testers, multiple simultaneous testing is most effective for meeting the larger 4M-bit DRAM production and the increasing number of functions per device. As devices become more complex and multi-functional, the per-pin test architecture is a useful strategy for increasing the logic tester throughput. Electronic system packaging: the search for manufacturing the optimum in a sea of constraints. LARRY L. MORESCO. IEEE Trans. Compon. Hybrids mfg Technol. 13(3), 494 (1990). Generally, the design of "single-chip packages" is equivalent to writing a book with incomplete sentences. Manufacturing electronic systems is a multicomponent, multichip, hybrid design process which spans the life of the product. The design constraint list is not limitless, but if incomplete, can lead to economic loss for the product. This paper details some of the constraints that affect system performance, reliability, materials selection, and the assembly of the product. The electronic constraints include, chip crossing delay, fan out (number of receivers on a driven net), cross-talk (unwanted electromagnetic coupling between independent signal lines and power supplies), d.c. voltage drop, the number of simultaneously switched line drivers (NSSDs), and reflections of signal waves from discontinuities in transmission line networks. The power dissipation constraints include maximum junction temperature, ambient temperature and pressure drop conditions, and component-to-component temperature variation. The cost constraints include materials, fabrication, and assembly. Some of the mathematical constraints are defined along with the coupling between them, optimum solutions are shown graphically. The ability to resolve the system manufacturing constraints through optimization will determine the final success of a product. Makers expect ASICs to reverse computer slump. JEE (Japan), 34 (May 1990). The great slump in sales of mainframe computers and sluggish demand for personal
computers since last year have greatly affected sales of semiconductor products in the United States, and observers believe that the U.S. semiconductor market has hit the bottom of the silicon cycle. Silicon micromechanics: sensors and actuators on a chip. ROGER T. HOWE et al. IEEE Spectrum, 29 (July 1990). Remarkable advances in sculpting minute sensors, motors, valves, and pumps from silicon could affect such diverse fields as optical signal processing and magnetic recording technology. A look at optoelectronic integrated circuits. Nonuo SUZUK1. JEE (Japan), 56 (April 1990). Optoelectronic integrated circuits (OEICs) provide high-level performance by monolithically integrating optoelectronic devices. These circuits will find applications in optical communication, interconnection and information processing. However, because these circuits are produced by integrating different types of devices, various concessions must be made in terms of device structure and production processes. Potential and problems of high-temperature electronics and CMOS integrated circuits (25-250°C)--an overview. F. S. SHOUCAIR. Mieroelectron. J. 22(2), 39 (1991). A brief overview of high-temperature integrated circuit technologies is presented. General comparisons of the hightemperature performance and relative merits of several semiconductor materials, technologies, devices and digital and analog circuits are highlighted. Important advances and developments of the last three decades are outlined, which reflect the prominence of MOSFET technologies. Shortcomings of the temperature models in standard IC computer-aided-design (CAD) programs are summarized and a discussion of near- and long-term research and development needs for high-temperature integrated electronics is presented. Supply formats change with chip use trends. JEE (Japan), 42 (October 1990). Owing to the development of a variety of chip parts, chip manufacturers are changing the formats in which chip parts are supplied to users. While tape formats remain popular, taping techniques have altered