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Mapping the failure envelope of board-level solder joints
Microelectronics Reliability 49 (2009) 397–409
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Mapping the failure envelope of board-level solder joints L.B. Tan a, Xiaowu Zhang b, C.T. Lim a, V.B.C. Tan a,* a b
National University of Singapore, Impact Mechanics Laboratory, Department of Mechanical Engineering, EA 01-22, 10 Kent Ridge Crescent, Singapore 119260, Singapore Institute of Microelectronics (IME), 11 Science Park Road, Singapore 117685, Singapore
a r t i c l e
i n f o
Article history: Received 13 January 2008 Received in revised form 11 December 2008 Available online 6 March 2009
a b s t r a c t Single solder interconnects were subjected to a series of combined tension–shear and compression–shear tests to determine their failure load. The failure envelope of these interconnects was obtained by plotting the normal component against the shear component of the failure load. The interconnect failure force map was found to be elliptical like the failure envelopes of many materials. The failure map can be described by a simple mathematical expression to give a simple force-based criterion for combine loading of solder joints. Post mortem analyses were conducted on the solder joint specimens to identify the failure mechanisms associated with various segments of the failure map. Computational simulations of actual board tests show that the failure map obtained for joint tests provides good predictions of board-level interconnect failures and hence suggest that such failure maps are useful in the design and analysis of board assemblies subjected to mechanical loads. The industry could adopt the methodology to obtain failure envelopes for solder joints of different alloys, bump size and reflow profiles which they could later use to aid in board-level and system-level designs of their products for mechanical reliability. Ó 2009 Published by Elsevier Ltd.
1. Introduction Although tests to measure the strength of solder joints include ball shearing [1], package peel test [1,2] and board bending [3] have been reported, these tests have certain inherent limitations. For example, to obtain solder joint strengths from board bend tests, finite element analyses are conducted and matched to the experimental deflection or force at failure. Such stress-based failure predictions are normally dependent on mesh density and thus effective comparison across literatures is difficult. While ball-shear tests provide a more direct method of solder joint strength measurement, there are reports indicating the initiation of wrong failure modes. The failure modes observed for samples which have undergone drop impact are those of either pad peel-offs or intermetallic failure at the solder/pad interfaces. However, the method often initiates solder bulk failure instead [1]. The most commonly observed failure models can, in general, be grouped into either overload or fatigue [4,5]. It is increasingly evident that maximum load models are more practical because boards with massive packages and heat dissipation solutions fail within a couple of drops rather than a few hundred drops at the board level. This is especially the case in drop tests of motherboards. End products such as laptops and PDAs are also reported
* Corresponding author. Tel.: +65 6516 8088. E-mail addresses: [email protected], [email protected] (L.B. Tan), [email protected] (V.B.C. Tan). 0026-2714/$ - see front matter Ó 2009 Published by Elsevier Ltd. doi:10.1016/j.microrel.2008.12.013
to fail in less than a handful of drops. The overall mass of these products, including their casing and chassis, are substantial relative to the board itself, and hence inertia loads will also become more significant. This paper presents the failure of single solder joints under combined normal and shear loads. The primary research is to formulate a suitable failure criterion to predict board-level reliability due to massive packages that fail due to overload. Failure forces are derived from single solder joints subjected to a variety of loading states. The failure map is then verified through a series of board-level tests and comparison with finite element simulation to see if the failure of the corner joints of a BGA can be correctly predicted. The force-based approach has also been successfully utilized by Wung [6] in predicting spot welds failures.
2. Test methodology This paper deals with the mapping of solder joint strength under combined loading from results of single solder joint tests. The resultant failure map is then verified for its ability to predict board-level interconnection failures by comparing actual board-level tests with finite element simulations. Many segments of work are involved. They are basically divided into: (1) solder joint and board-level testing. (2) Failure mapping and criterion formulation. (3) Failure analysis of tested joints. (4) Validation of criteria in predicting board-level failures, and (5) Comparison of failure modes of solder joints from board and single joint tests.
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Table 1 Specifications of components. Parts
Material
Solder layout
Solderball material and dimensions
Pad finish
Pad-topad pitch
PCB
FR4 (4-layers) Epoxy resin (Build-up)
SMD (450^)
Eutectic Sn/Pb, 500 lm diameter
ENIG
l mm
Substrate
Only specifications at board-level are given since analysis deals with failure prediction at this level.
cracking during machining and to exclude any experiment data from joints that are not wetted properly. The next step involves the fabrication of fixtures to hold the two surfaces of the solder joint samples. Fig. 1 illustrates the schematics and dimensions of the fixtures used, and Fig. 2a shows an example of the end-product after the single joint specimen are bonded to the fixtures. All joints are tested at the ramp rate of 100 lm/min. The LoctiteTM 4105 kit instant adhesive (Cyanoacrylate) is used to bond the samples to the fixtures because it has a fast curing time
2.1. Solder joint and board-level testing The first phase involves the preparation of single joint samples to be used for mechanical testing. Ready-made or ‘‘as-reflowed” printed circuit board (PCB) assemblies of the same lot are mechanically cut to yield the single joint samples. The specifications for the PCB assembly used in our tests are given in Table 1. Eutectic Sn/Pb solder joints are used due to limited samples available. However, the methodology could also be employed for lead-free solders. A very small end-mill cutting tool, 0.3 mm in diameter, is used to perform the micro-machining at a feed rate of 30 mm/min and 17,000 rpm. Cutting forces from the machining of these joints are less than 30% of the failure force of single joints obtained experimentally and deemed low enough not to cause any damage to the joint. The cut samples (1.2 by 1.2 mm) are then inspected using both X-ray and optical microscopy to select good joint samples for subsequent testing. Further quality control procedures such as SEM helps to ensure the joints do not undergo any stress–corrosion
Fig. 2b. Joint test experimental setup.
Fig. 1. Schematics for fixtures bonded to single joint specimens. Bottom fixture (Steel): a = 50 mm, b = 11.6 mm /; top fixture (Aluminium): a = 5 mm, b = 4.5 mm /. Fig. 2c. 5-Point bend test.
Fig. 2a. Sample bonded on 60° fixtures.
Fig. 2d. Combine bend-shear test.
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and high bond strength. It is also easily dissolved in acetone so that the fixtures can be re-used. The samples are tested on a micro-Instron tester 5848. Tensile loads are applied via a KevlarTM yarn inserted through the hole in the top fixture to avoid damaging interconnects resulting from clamping mounted samples that may be slightly misaligned. For tests having combined compression and shear, a self-aligning swivel compression platen is used for similar reasons. Fig. 2b shows the typical test setup for angled-pull of the single joint samples. Quasi-static five-point bend tests and combined bend-shear tests of PCB assemblies are performed at a later stage to validate the failure map obtained from single joint tests. The PCB’s are loaded until solder joints at the corners of the ball grid array failed. Table 2 provides the test matrix for the quasi-static board-level testing. For board configuration B, built-in daisy chains are series-configured in perimetral links such that when the corner joints fail electrically during a test, a peak in voltage can be observed in the oscilloscope. Hence, the deflection, as well as, the load and time to failure can be accurately recorded via in situ monitoring. In view of the PCB assemblies that do not have active daisy chains to monitor joint failure (A and C), the technique of using strains to capture joint failure was used. This method has been reported by Hsieh and Mcallister (Intel) [7] and Tan et al. [8] and is relatively reliable. It is also able to detect certain failure modes which may not be readily detected by daisy chain monitoring, such as pad/trace delamination [7]. 2.1.1. Experimental setup Figs. 2c–d shows the setup and implementation of the 5-point bend test and the combine bend-shear test, respectively. For the 5-point bend test, the PCB assembly is rigidly bolted at the four corners to a fixture that is clamped to the base of the miniInstron tester. A steel cylindrical plunger with a hemispherical tip and diameter of 11.2 mm is used to deflect the PCB assembly quasi-statically and strain/daisy chain readings are closely monitored for anomalies until corner joint failures occur. For the bend-shear test, the PCB assembly is first rigidly bolted at the edges to form an edge-clamped condition. A bolt is next manually turned at a very slow rate to cause the bend block to move forward to deflect the PCB by the amount of predetermined displacement (2.5 mm in this case). A dial gauge is used to check the amount of deflection applied. The shear blade, which is fixed to the ramp of the mini-Instron, is then lowered gradually to ‘‘shear” the package. In all, three boards each were assessed for the individual quasistatic tests.
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than ±15%. Samples of the resulting force–displacement curves of the various tests are given in Figs. 3a and 3b. 2.2.1. Tension/shear tests Fig. 3a shows the typical failure force versus displacement response of the various tension/shear tests. The profiles are staggered (per 0.2–0.3 mm) instead of directly overlayed to provide a clearer presentation. Comparison of results between the different loading orientations shows that as the specimen changes from pure tension to mixed tension/shear and then to pure shear, the joint failure forces decreases. The failure force is defined as the peak force experienced by the joint. For most tests concerning 0° and 30° loading directions, rapid degradation of force correlated to pad peel-off can be observed, while 60° and 90° tests displayed gradual force reduction often revealing solder yield failure in posttest analysis. 2.2.2. Compression/shear tests As compression of the specimens does not cause separation of the joints, the failure forces obtained from these tests are taken to be the forces causing the joint to yield. The yield forces are obtained by locating the points where the graphs begin to deviate, from its initial linear form (Fig. 3b). This point is easily discernible for tests having large specimen angle orientations. The average re-
Fig. 3a. Typical force–displacement profiles for single joint tension/shear test.
2.2. Joint test results and discussion Several sets of tests are performed for the different angle and tension and compression configurations. The measured joint failure loads generally give good repeatability with an error of less
Table 2 Test matrix and board configurations used. Test batch
Type of test
Board dimensions (mm)
Loading rate (mm/min)
Boundary conditions
Method to detect joint failure
A
5-Point bend 5-Point bend Bendshear
195 195 0.78 (square) 120.2 90.3 1.6 (rectangular) 195 55.2 0.78 (strip)
1
Comers bolted Comers bolted Edges damped
Strain gauges Daisy chain Strain gauges
B C
0.5 0.5
Fig. 3b. Typical force–displacement profiles for single joint compression/shear test.
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Fig. 4. Repeatability of joint failure forces for various tested orientations.
sults for the various sets of single solder joint tests are given in Fig. 4. From Fig. 4, it can be observed that the joint failure forces are the highest for pure tension and pure compression. The former being the value of joint detachment while the latter is that for gross joint yielding. 2.3. Failure mapping and criterion formulation Using the results acquired from the previous section, a mapping of the joint failure forces, in terms of tension, shear
Fig. 5. Failure mapping and criterion formulation.
and compression components, can be plotted. An empirical criterion that approximates the actual failure map is also given. Fig. 5 illustrates the failure map and its accompanying failure criterion.
Fig. 6. (a) PCB pad peel-off; (b) gross bulk yielding; (c) hillock; (d) dimples (1000).
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The empirical expression of the failure criterion is of the form,
ðFT aÞ b
2
2
2
þ
ðFS Þ 1 c2
ð1Þ
where a, b and c are the constants defining the vertical shift of the plot (Bauchinger effect), the averaged value for pure tension/ compression failure (performed at 0° and 180°), and the value for pure shear (performed at 90°). For our solder samples of specified dimension, pad finishing, and reflow history, the values for a, b and c are determined to be 0.5 N, 10 N and 4.65 N, respectively. For any circuit board failures that can be characterized by a similar mathematical form, once the joint failure forces for pure tension, compression and shear are obtained, the failure criterion for the joint can be approximately derived. With the criterion, one can evaluate a particular board’s failure deflection and loads regardless of boundary/load conditions or board geometry. This will help board manufacturers design boards against overload type of loading environment. 2.4. Failure analysis of tested joints Post-test failure analyses using optical microscopy, scanning electronic microscopy (SEM) and energy dispersive spectroscopy (EDX) are conducted on the specimens. The failed joint specimens due to different loading conditions are illustrated below. 2.4.1. 0° Pure tension Depending on the strength of the individual pads, specimens under tension show either gross bulk yielding which gradually leads to joint failure or pad peel-off that is catastrophic and sudden (Fig. 6a and b). Regardless, the failure loads for the two different failure modes are very close to each other. This implies that the pad adhesive-strength is almost that of solder yield strength, however, depending on the failure mode, the resultant failure strain/ displacement could be vastly different. SEM was conducted to analyze the morphology of the failure surface arising from bulk yielding. Fig. 6c reveals the origin of failure to be at the central region where the macro features are that of distinctive hillocks, characteristic of yield-type failure. The height of the hillock features also suggest that the failure initially occurred within the bulk solder and not at the pad/intermetallic interface. The spatial extent and location of the hillock give an indication of the ductility of the material as well as the loading direction. The hillock is at the center of the pad because the applied load was axial tension.
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At a higher magnification of 1000, microstructural features such as microvoid coalescence or dimple fracture can be observed (Fig. 6d). This is shown by depressions in the microstructure called dimples, which occur from microvoids in places of high local plastic deformation. Dimple size and shape depend on the type of loading and extent of microvoid emergence. When a material is put under uniaxial tensile loading, as in this case, equiaxed dimples with complete rims appear. Shear loading has the same features except the dimples are elongated and in opposite directions. The microstructures for joints that have undergone shear loading will be illustrated in subsequent sections. Energy dispersive spectroscopy (EDX) did not reveal any presence of intermetallics on the failure surfaces of the specimens subjected to tensile loading. Intermetallic failure is thus excluded as a probable failure mode for this load condition. 2.4.2. 30° Tension/shear Optical inspection of the failed specimens for this loading condition showed that almost all joints fail by bulk yielding near the substrate interface. A very small number of samples see failures by pad peel-off, which is one of the dominant failure modes observable for pure tension. For failures occurring via bulk yielding, the hillock is characteristically at the leading/trailing edge of the pad in the direction of shear (Fig. 7a). This is in contrast with the centrally located hillock for 0° tension tested specimens.
Fig. 8a. Less deformation of joint than 0° and 30° loading.
Fig. 7. (a) SEM (incline view) 220 and (b) 400.
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Fig. 8b–d. Finite element simulation of joints undergoing (b) 0° tension, (c) 30° tension/shear, (d) 60° tension/shear.
Fig. 8e–g. (e) ‘‘Smooth” failure surface; (f) elongated dimples with in-complete rims (800 magnification); (g) EDX elemental analysis.
SEM pictures on the resultant failure surfaces show elongated dimples which are representative of microvoid coalescence due to shear loading (Fig. 7b). The existence of these features makes the fracture surfaces appear rough and irregular which is characteristic of ductile fracture. EDX performed on the failure surfaces revealed fracture occurring at the bulk solder and no failure at the intermetallic is found. The solder/Au–Ni–Cu pad interface is believed to be intact for this loading condition. 2.4.3. 60° Tension/shear This set of specimens demonstrates much less deformation of solder prior to failure, unlike those seen for 0° and 30° tension/ shear tests (Fig. 8a). At 60° tension/shear the regions of high stress are located only close to the pad interfaces as opposed to the 0° and
30° tests whereby high stresses are concentrated within the core regions of the solderball. The non-uniformity of stress distribution via the application of the 60° tension/shear load causes much localized stresses at the pad edges, which then causes the joint to fail before much deformation can occur. This is illustrated in the Mises stress contours derived from FE simulation of joints undergoing 0°, 30° and 60° tension/shear of a similar applied load (Figs. 8b–d) whereby regions of high stresses (shown in red) are concentrated at the solder/pad interfaces1. The result is a ‘‘smoother” failure surface
1 For interpretation of color in Fig. 8, the reader is referred to the web version of this article.
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than those of 0° and 30° tension/shear, with failures occurring at the substrate interfaces rather than the solder bulk. Fig. 8e shows the elongated dimples typically associated with shear loading. The size of these dimples is approximately similar to those of 30° tension/shear loading. However, the depths of the dimples are much shallower than their 30° counterpart and the elliptical nature of the dimples are more pronounced (Fig. 8f). Further, the overall number of visible elongated dimples is also much less than those from the 30° tension/shear. Some failed surfaces show failure across the solder/metallic pad layer. Results from EDX confirm the existence of nickel, phosphorus and aluminium in addition to the expected tin and lead elements at the failure surface. Fig. 8g illustrates the region investigated and the results of the EDX analysis. This implies that the fracture surface no longer lies purely at the bulk solder region like those observed for specimens loaded at 0° and 30° directions. These patches of ‘‘anomaly” are usually at the trailing edge and traverse across different materials. The intermetallic (IM) layer in our specimens is expected to be minimal since the samples do not undergo thermocycling. However, from the stress contours derived from FE simulation that demonstrates higher stresses at interfacial regions (for a large angle loading), it can be expected that as the IM layer thickness increases, there could be a higher chance of IM failure if boards are loaded such that joints experience a certain degree of shear in addition to the dominant tension experienced in board flexure. Lastly, it is emphasized that the above failure mode is only observed for 60° tension/shear and comes from the same batch of specimens as that used for other loading conditions.
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2.4.5. 60°, 30° Compression/shear and 0° compression Optical inspection of the failed specimens shows that almost all failures due to compression/shear occur at the substrate/solder interface (Fig. 10a). The solder is observed to shear laterally and is flatter than those of 60° tension/shear. However, the amount of overall deformation is much less than those seen for 0° and 30° tension/shear. The failure interfaces on the ball exhibit the crescent shaped shiny surfaces observed for 60° compression/shear samples (Fig. 10b). At the substrate failure interfaces, visibly deep scratch marks can be seen running along the direction of applied loading. These are caused by the compressive component of the force as the joint is forced to shear. Fig. 10c shows the failure surface via SEM at 550 magnification. Almost all surfaces appear rough. The apparent scratch marks are only unique to specimens experiencing compression/shear loading conditions. These scratch marks replace the dimple-macrostructures seen in tension/shear, and is believed to be due to bulk material movement induced by the compression/shear. For 30° and 0° compression loading, the specimens do not readily produce a failure surface since the stress states are predominantly compressive. General observations show global gross shearing and compression of the solder joint as given in Fig. 10d and e. Since only the yield strength of the joint is needed to generate the failure map, tests were stopped when yield is obvious. However, it is prudent to note that although the solder joint is considerably flattened, it is electrically intact, unlike failure due to other loading conditions. Severely flattened joints may lead to solder bridging. 2.5. Validation of criteria in predicting board-level failures
2.4.4. 90° Shear Fig. 9a and b shows the dominant failure modes of specimens undergoing 90° shearing. The specimens generally exhibit gross bulk solder yielding at the solder/pad interface prior to failure. The amount of solder deformation is also visibly less than those of 0° and 30° tension/shear. The dominant failure mode for this loading condition is bulk solder failure which occurs at very close to the pad interfaces. EDX analyses do not reveal foreign metals except for tin and lead. In addition, no pad peel-off is observed. The failure forces obtained are also the most repeatable for this loading condition and the failure modes observed are also very consistent. The resultant failure surface at the substrate shows a rough morphology, indicating possible dimple formation or yieldtype failure.
The ability of the failure map in Fig. 5 to predict interconnect failures is verified through finite element simulations of the board-level tests. The material properties of the different microelectronic components used in the board-level simulation are tabulated in Table 3. Orthotropic properties are applied to the PCB material where the principal directions are given in Fig. 12b. The post-yield characteristic of solder is obtained by quasi-static compression of bulk solder that is performed separately. The stress– strain curves of solder are given in Fig. 11. Fig. 12a shows the 3D finite element models of the various components as well as the PCB assembly configurations (A), (B) and (C). Fig. 12b shows the 5-point bend simulation of (B). A total of 1296 cylindrical ‘‘solderballs” are modeled in an area array format
Fig. 9. (a, b) Gross bulk yielding at pad interface.
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Fig. 10. (a) Scratch marks on failed surface; (b) crescent shinier surface at trailing edge; (c) SEM of scratched surface (550); (d) gross shear compression of solderjoint; (e) compression of solder joint.
between the PCB and the substrate. The element type for all the parts are C3D8R and the ‘‘solderballs” have 60 elements each. The results from finite element simulation are superposed with experimental data to check for good correlation. Fig. 13a and b shows the force–displacement and board strains response between simulation results and experimental data for configuration (A). STPX and STPY denote the experimental strains obtained on the face of the PCB attached to the substrate in the transverse and longitudinal directions, respectively. The exercise serves to illustrate
the accuracy and quality of the FE model before solder joint forces are extracted. The finite element simulations are performed without the modeling for failure of the joints. The jobs are completed when the displacement-to-failure determined from the experiments have been achieved. The corner joint section forces are then extracted from the joint/substrate interface and superposed onto the plot of the single joint failure map to ascertain the ability of the latter in predicting quasi-static board-level joint failures. Fig. 14 shows the
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L.B. Tan et al. / Microelectronics Reliability 49 (2009) 397–409 Table 3 Material properties of components. Components
Young’s modulus (GPa)
Yield/hardening (MPa/ep)
Poisson’s ratio
Density (kg/m3)
Dimensions (mm)
PCB (orthotropic)
El/E2: 16.85, E3:7.375 (out-of-plane) G12:3.4, G13/G23:2.25 12.5 110
180,0 280, 0.01 330, 0.02 100,0; 215,0.006 Nil
m13: 0.39 m23: 0.39 ml2: 0.11
2177
Refer to Table 2
0.3 0.3
2112 8600
40 40 1.5 40 40 2.14
20.4 180 195
Refer to Fig. 11 Nil Nil
0.363 0.3 0.3
8400 2330 8025
Ht: 450 l, cia: 550 l (cylindrical) Big: 12 12 0.4, small: 5 5 0.4 Contact dia: 11.2
Substrate Heatspreader (brass) used only in PCB (B) Solderballs Silicon die Steel plunger
Where El, E, BP G12.G13.G23, m13, m23 and m12 are the orthotropic moduli and poisson’s ratio in the respective corrponent directions. The PCS and substrate post-yield properties are input into Abaqus in tabular form.
2.6. Failure mode compatibility between board and single joint failures After the completion of the respective board-level tests, the failed joints are inspected to determine their failure modes.
Fig. 11. Stress–strain curves of bulk Sn-37Pb solder under quasi-static loading.
single joint failure map together with the corner joint forces obtained from the FE simulation at the end of each simulation. In Fig. 14, the circles denote the forces within the corner solder joints from FE simulations of board assemblies at the same load conditions that caused joint failures in actual board tests. It can be observed that the circles lie closely to the failure map indicating the validity of the single joint failure map in predicting board-level failures.
2.6.1. A. Corner joint failure for board configurations A and B The failure modes of the joints for board test configurations A and B are jointly discussed since both employ similar 5-point bend test method and have considerably higher corner joint tensile force than shear as reflected in Fig. 14. The breakdown of the failure modes observed for the individual corner joints are given in Table 4. Fig. 15a depicts joint failures whereby the corner joint is distinctively detached justifying the legitimacy of using daisy chain/ strain gauge technique in detecting failure. Since the corner joints have visibly failed, the package is pried open delicately to reveal the failure surfaces. Fig. 15b confirms the pad peel-off failure mode experienced by the corner joints. SEM/EDX of the pad peel-off surface on the solder joint shows the presence of copper, nickel and zinc. This is given in Fig. 16a. However, the same analysis yields absolutely no traces of such metals on the remaining PCB pad (Fig. 16b) – the result exactly reproduced that for the pure tension testing of the single joints. It can thus be concluded that if failure at the pad occurs, it will certainly be within the PCB matrix material, since the bonds at the Cu/ Ni pad and solder are much stronger than that at the Cu/Ni and FR4 interface. For corner joints and adjacent joints which do not fail by pad peel-offs, the resulting failure surface exudes the typical dimple fractography. This has been characterized in the previous section
Fig. 12a. Overview of PCB layout (A), (B) and (C) for Abaqus simulation (only (B) has a brass heatspreader over the substrate).
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Fig. 12b. 5-Point bend simulation for board (B).
Fig. 14. Joint force evolution and failure map.
The post-test inspections, in addition to the finite element results, show that not only are the board-level joint failures due to the 5-point bend test correctly predicted, their failure modes are also correctly characterized.
Fig. 13. (a) Force–displacement correlation; (b) board strains correlation.
to be failure attributable to dominant tension. EDX analysis of the surfaces shows no sign of intermetallic failure and hence failure occurs within the bulk solder. Fig. 17a and b illustrates the typical failure morphology for the corner and adjacent joints.
2.6.2. B. Joint failures from board configuration C The loading conditions for configuration C are such that the joints experience both tension and shear. The failure modes of the corner joints closest to the shear blade and that at the bottom edge of the substrate are speculated to be different due to the different stress states experienced by the solders. Table 5 depicts the different types of failure modes observed from board samples. Close-ups of the joints at the region closest to the shear blade reveal that the outermost layer of joints whereby joint forces are predominantly tensile, experience pad peel-off failures, as illustrated in Fig. 18(a). The corresponding solder joint failure forces (overlay with the failure map) are given in Fig. 14 (Board (C) – top edge). In addition, large deformation of the joints is observed for the immediate subsequent inner rows of joints. SEM of the substrate pad surfaces reveals hillocks at the trailing edges and is illustrated in Fig. 18(b). The nature of joint deformation exhibits one due to a combined tension and shear loading (Fig. 7). A few of the corner joints also failed via pad peel-off. The different failure modes for progressively internal joints of the bend-shear specimens are in tandem with FE simulation findings which illustrated dominant tension for outermost joints on the top edge and progressively dominant shear for the more inte-
Table 4 Failure modes observed for corner joints. Board configuration
Sample no.
Observed failure mode
Predicted failure mode (based on location at failure map)
A (without heatspreader)
1 2 3 4 5 6
Pad Pad Pad Pad Pad Pad
Pad peel-off
B (with heatspreader)
peel-off peel-off peel-off peel-off peel-off peel-off
(3) (2) (3) (3) (4) (4)
Intact (1) intermetallic (1) intact (1) intact (1) intermetallic (1)
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Fig. 15. (a) Corner joint failures; (b) pad peel-offs.
Fig. 16. (a) SEM/EDX analysis on ball; (b) SEM/EDX analysis on pad.
Fig. 17. (a) Morphology by SEM for corner joint; (b) morphology by SEM for adjacent joints.
rior joints as caused by the combined bending and shearing of the package. Close-ups of the joints at the region furthest away from the blade reveal significant joint shearing and compression, as oppose to tension. As a result, the predominant failure mode found at this region is solder bulk yielding. Fig. 18c illustrates the joint failures experienced at this region. The corresponding solder joint failure
forces (overlay with the failure map) are given in Fig. 14 (Board (C) – bottom edge). SEM/EDX of these joints reveals scratch marks on the failed surfaces, apparently due to the compression/shear induced on the joints (Fig. 18(d)). Since these scratch marks have also been reported in ball-shear tests, the implication is that the loading caused by the ball shear consists of significant amounts of compression,
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Table 5 Failure modes observed for failed joints. Board configuration
No.
Observed failure mode (corner joints)
Observed failure mode (region)
Predicted failure mode (based on location at failure map)
C (Combined bend-shear)
1
Top edge Bottom edge Top edge Bottom edge Top edge Bottom edge
Top region Bottom region Top region Bottom region Top region Bottom region
Pad peel-off Intermetallic/solder bulk Pad peel-off Intermetallic/solder bulk Pad peel-off Intermetallic/solder bulk
2 3
Intermetallic Intermetallic/solder bulk shear Intermetallic/pad peel-off Solder bulk shear/compression Elongated solderball Solder bulk shear/compression
Pad peel-off Solder bulk Pad peel-off Solder bulk Pad peel-off Solder bulk
Fig. 18. (a) Pad peel-offs for outermost joints and large joint deformation at inner layers (region closest to shear blade); (b) hillocks at trailing edge; (c) shear/compression of joints; (d) scratch marks signifying a compressive/shear load.
and thus joint strength values obtained from the methodology are not representative of board bend or drop failures whereby tension/ shear loading to the joints are expected. No elongated dimples are observable since they could most probably be flattened out. It can be summarized that the observed failure modes on the board samples do coincide with that predicted from the failure map when the region of joints is collectively considered as a whole. However, some corner joints do not uphold the failure modes prediction. The discrepancy is believed to be due to the complexity of the board loading conditions. 3. Conclusions It is demonstrated that the failure mapping obtained from single joint tests predicted board-level joints failure well. Not only is the instant of joint failure well-predicted for different load cases, the failure modes of the joints are also predicted. This illustrates the independent nature of the failure mapping methodology in effectively predicting board failures due to combined loading on various board geometries with different boundary conditions.
Furthermore, the characteristics of the failure surfaces and failure modes due to the different loading conditions have also been identified and characterized and will help researchers in their failure analysis of board-level joints as one may then deduce the load history accrued to them just from the fractography created. A mathematical failure criterion has also been formulated and may be implemented to FE modeling to save computational time and costs. Preliminary board assembly designs against vibration, impact or static loads can then be effectively and accurately evaluated by FEA without the need to go through prototype testing. The methodology may be extrapolated to different types of solders, solderball dimension and pad finishes and even newer forms of board-level interconnect. References [1] Jinlin Wang, Lim HK, Lew HS, Woon Theng Saw, Chew Hong Tan. Peel test metrology for solder joint reliability of FCBGA packages. In: Electronics components and technology conference, IEEE; 2003. [2] Jason Bragg, Justine Bookbinder, George Sanders, Blake Harper. A nondestructive visual failure analysis technique for cracked BGA interconnects. In: Electronic components and technology conference, IEEE; 2003.
L.B. Tan et al. / Microelectronics Reliability 49 (2009) 397–409 [3] Lau John H. Solder joint reliability of flip chip and plastic ball grid array assemblies under thermal, mechanical, and vibrational conditions. IEEE Trans Compon Pack Manuf Technol Part B 1996;19(4) [November 1999]. [4] Tong Yan Tee, Hun Shen Ng, Chwee Teck Lim, Eric Pek, Board level drop test and simulation of TFBGA packages for telecommunication applications. In: Electronic components and technology conference, IEEE; 2003. [5] Tee Tong Yan, Ng Hun Shen, Lim Chwee Teck, Pek Eric, Zhong Zhaowei. Drop test and impact life prediction model for QFN packages. J SMT 2003;16(3).
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[6] Wung P. A force-based failure criterion for spot weld design. Exp Mech 2001:107–13. [7] George Hsieh, Alan Mcallister. (Intel Corporation). Flip chip ball grid array component testing under board flexure. In: Electronic components and technology conference, IEEE; 2005. [8] Tan LB, Seah SKW, Wong EH, Xiaowu Zhang, Tan VBC, Lim CT. Board level solder joint failures by static and dynamic loads. In: Electronics packaging and technology conference, IEEE; 2003.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Mapping the failure envelope of board-level solder joints L.B. Tan a, Xiaowu Zhang b, C.T. Lim a, V.B.C. Tan a,* a b
National University of Singapore, Impact Mechanics Laboratory, Department of Mechanical Engineering, EA 01-22, 10 Kent Ridge Crescent, Singapore 119260, Singapore Institute of Microelectronics (IME), 11 Science Park Road, Singapore 117685, Singapore
a r t i c l e
i n f o
Article history: Received 13 January 2008 Received in revised form 11 December 2008 Available online 6 March 2009
a b s t r a c t Single solder interconnects were subjected to a series of combined tension–shear and compression–shear tests to determine their failure load. The failure envelope of these interconnects was obtained by plotting the normal component against the shear component of the failure load. The interconnect failure force map was found to be elliptical like the failure envelopes of many materials. The failure map can be described by a simple mathematical expression to give a simple force-based criterion for combine loading of solder joints. Post mortem analyses were conducted on the solder joint specimens to identify the failure mechanisms associated with various segments of the failure map. Computational simulations of actual board tests show that the failure map obtained for joint tests provides good predictions of board-level interconnect failures and hence suggest that such failure maps are useful in the design and analysis of board assemblies subjected to mechanical loads. The industry could adopt the methodology to obtain failure envelopes for solder joints of different alloys, bump size and reflow profiles which they could later use to aid in board-level and system-level designs of their products for mechanical reliability. Ó 2009 Published by Elsevier Ltd.
1. Introduction Although tests to measure the strength of solder joints include ball shearing [1], package peel test [1,2] and board bending [3] have been reported, these tests have certain inherent limitations. For example, to obtain solder joint strengths from board bend tests, finite element analyses are conducted and matched to the experimental deflection or force at failure. Such stress-based failure predictions are normally dependent on mesh density and thus effective comparison across literatures is difficult. While ball-shear tests provide a more direct method of solder joint strength measurement, there are reports indicating the initiation of wrong failure modes. The failure modes observed for samples which have undergone drop impact are those of either pad peel-offs or intermetallic failure at the solder/pad interfaces. However, the method often initiates solder bulk failure instead [1]. The most commonly observed failure models can, in general, be grouped into either overload or fatigue [4,5]. It is increasingly evident that maximum load models are more practical because boards with massive packages and heat dissipation solutions fail within a couple of drops rather than a few hundred drops at the board level. This is especially the case in drop tests of motherboards. End products such as laptops and PDAs are also reported
* Corresponding author. Tel.: +65 6516 8088. E-mail addresses: [email protected], [email protected] (L.B. Tan), [email protected] (V.B.C. Tan). 0026-2714/$ - see front matter Ó 2009 Published by Elsevier Ltd. doi:10.1016/j.microrel.2008.12.013
to fail in less than a handful of drops. The overall mass of these products, including their casing and chassis, are substantial relative to the board itself, and hence inertia loads will also become more significant. This paper presents the failure of single solder joints under combined normal and shear loads. The primary research is to formulate a suitable failure criterion to predict board-level reliability due to massive packages that fail due to overload. Failure forces are derived from single solder joints subjected to a variety of loading states. The failure map is then verified through a series of board-level tests and comparison with finite element simulation to see if the failure of the corner joints of a BGA can be correctly predicted. The force-based approach has also been successfully utilized by Wung [6] in predicting spot welds failures.
2. Test methodology This paper deals with the mapping of solder joint strength under combined loading from results of single solder joint tests. The resultant failure map is then verified for its ability to predict board-level interconnection failures by comparing actual board-level tests with finite element simulations. Many segments of work are involved. They are basically divided into: (1) solder joint and board-level testing. (2) Failure mapping and criterion formulation. (3) Failure analysis of tested joints. (4) Validation of criteria in predicting board-level failures, and (5) Comparison of failure modes of solder joints from board and single joint tests.
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Table 1 Specifications of components. Parts
Material
Solder layout
Solderball material and dimensions
Pad finish
Pad-topad pitch
PCB
FR4 (4-layers) Epoxy resin (Build-up)
SMD (450^)
Eutectic Sn/Pb, 500 lm diameter
ENIG
l mm
Substrate
Only specifications at board-level are given since analysis deals with failure prediction at this level.
cracking during machining and to exclude any experiment data from joints that are not wetted properly. The next step involves the fabrication of fixtures to hold the two surfaces of the solder joint samples. Fig. 1 illustrates the schematics and dimensions of the fixtures used, and Fig. 2a shows an example of the end-product after the single joint specimen are bonded to the fixtures. All joints are tested at the ramp rate of 100 lm/min. The LoctiteTM 4105 kit instant adhesive (Cyanoacrylate) is used to bond the samples to the fixtures because it has a fast curing time
2.1. Solder joint and board-level testing The first phase involves the preparation of single joint samples to be used for mechanical testing. Ready-made or ‘‘as-reflowed” printed circuit board (PCB) assemblies of the same lot are mechanically cut to yield the single joint samples. The specifications for the PCB assembly used in our tests are given in Table 1. Eutectic Sn/Pb solder joints are used due to limited samples available. However, the methodology could also be employed for lead-free solders. A very small end-mill cutting tool, 0.3 mm in diameter, is used to perform the micro-machining at a feed rate of 30 mm/min and 17,000 rpm. Cutting forces from the machining of these joints are less than 30% of the failure force of single joints obtained experimentally and deemed low enough not to cause any damage to the joint. The cut samples (1.2 by 1.2 mm) are then inspected using both X-ray and optical microscopy to select good joint samples for subsequent testing. Further quality control procedures such as SEM helps to ensure the joints do not undergo any stress–corrosion
Fig. 2b. Joint test experimental setup.
Fig. 1. Schematics for fixtures bonded to single joint specimens. Bottom fixture (Steel): a = 50 mm, b = 11.6 mm /; top fixture (Aluminium): a = 5 mm, b = 4.5 mm /. Fig. 2c. 5-Point bend test.
Fig. 2a. Sample bonded on 60° fixtures.
Fig. 2d. Combine bend-shear test.
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and high bond strength. It is also easily dissolved in acetone so that the fixtures can be re-used. The samples are tested on a micro-Instron tester 5848. Tensile loads are applied via a KevlarTM yarn inserted through the hole in the top fixture to avoid damaging interconnects resulting from clamping mounted samples that may be slightly misaligned. For tests having combined compression and shear, a self-aligning swivel compression platen is used for similar reasons. Fig. 2b shows the typical test setup for angled-pull of the single joint samples. Quasi-static five-point bend tests and combined bend-shear tests of PCB assemblies are performed at a later stage to validate the failure map obtained from single joint tests. The PCB’s are loaded until solder joints at the corners of the ball grid array failed. Table 2 provides the test matrix for the quasi-static board-level testing. For board configuration B, built-in daisy chains are series-configured in perimetral links such that when the corner joints fail electrically during a test, a peak in voltage can be observed in the oscilloscope. Hence, the deflection, as well as, the load and time to failure can be accurately recorded via in situ monitoring. In view of the PCB assemblies that do not have active daisy chains to monitor joint failure (A and C), the technique of using strains to capture joint failure was used. This method has been reported by Hsieh and Mcallister (Intel) [7] and Tan et al. [8] and is relatively reliable. It is also able to detect certain failure modes which may not be readily detected by daisy chain monitoring, such as pad/trace delamination [7]. 2.1.1. Experimental setup Figs. 2c–d shows the setup and implementation of the 5-point bend test and the combine bend-shear test, respectively. For the 5-point bend test, the PCB assembly is rigidly bolted at the four corners to a fixture that is clamped to the base of the miniInstron tester. A steel cylindrical plunger with a hemispherical tip and diameter of 11.2 mm is used to deflect the PCB assembly quasi-statically and strain/daisy chain readings are closely monitored for anomalies until corner joint failures occur. For the bend-shear test, the PCB assembly is first rigidly bolted at the edges to form an edge-clamped condition. A bolt is next manually turned at a very slow rate to cause the bend block to move forward to deflect the PCB by the amount of predetermined displacement (2.5 mm in this case). A dial gauge is used to check the amount of deflection applied. The shear blade, which is fixed to the ramp of the mini-Instron, is then lowered gradually to ‘‘shear” the package. In all, three boards each were assessed for the individual quasistatic tests.
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than ±15%. Samples of the resulting force–displacement curves of the various tests are given in Figs. 3a and 3b. 2.2.1. Tension/shear tests Fig. 3a shows the typical failure force versus displacement response of the various tension/shear tests. The profiles are staggered (per 0.2–0.3 mm) instead of directly overlayed to provide a clearer presentation. Comparison of results between the different loading orientations shows that as the specimen changes from pure tension to mixed tension/shear and then to pure shear, the joint failure forces decreases. The failure force is defined as the peak force experienced by the joint. For most tests concerning 0° and 30° loading directions, rapid degradation of force correlated to pad peel-off can be observed, while 60° and 90° tests displayed gradual force reduction often revealing solder yield failure in posttest analysis. 2.2.2. Compression/shear tests As compression of the specimens does not cause separation of the joints, the failure forces obtained from these tests are taken to be the forces causing the joint to yield. The yield forces are obtained by locating the points where the graphs begin to deviate, from its initial linear form (Fig. 3b). This point is easily discernible for tests having large specimen angle orientations. The average re-
Fig. 3a. Typical force–displacement profiles for single joint tension/shear test.
2.2. Joint test results and discussion Several sets of tests are performed for the different angle and tension and compression configurations. The measured joint failure loads generally give good repeatability with an error of less
Table 2 Test matrix and board configurations used. Test batch
Type of test
Board dimensions (mm)
Loading rate (mm/min)
Boundary conditions
Method to detect joint failure
A
5-Point bend 5-Point bend Bendshear
195 195 0.78 (square) 120.2 90.3 1.6 (rectangular) 195 55.2 0.78 (strip)
1
Comers bolted Comers bolted Edges damped
Strain gauges Daisy chain Strain gauges
B C
0.5 0.5
Fig. 3b. Typical force–displacement profiles for single joint compression/shear test.
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Fig. 4. Repeatability of joint failure forces for various tested orientations.
sults for the various sets of single solder joint tests are given in Fig. 4. From Fig. 4, it can be observed that the joint failure forces are the highest for pure tension and pure compression. The former being the value of joint detachment while the latter is that for gross joint yielding. 2.3. Failure mapping and criterion formulation Using the results acquired from the previous section, a mapping of the joint failure forces, in terms of tension, shear
Fig. 5. Failure mapping and criterion formulation.
and compression components, can be plotted. An empirical criterion that approximates the actual failure map is also given. Fig. 5 illustrates the failure map and its accompanying failure criterion.
Fig. 6. (a) PCB pad peel-off; (b) gross bulk yielding; (c) hillock; (d) dimples (1000).
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The empirical expression of the failure criterion is of the form,
ðFT aÞ b
2
2
2
þ
ðFS Þ 1 c2
ð1Þ
where a, b and c are the constants defining the vertical shift of the plot (Bauchinger effect), the averaged value for pure tension/ compression failure (performed at 0° and 180°), and the value for pure shear (performed at 90°). For our solder samples of specified dimension, pad finishing, and reflow history, the values for a, b and c are determined to be 0.5 N, 10 N and 4.65 N, respectively. For any circuit board failures that can be characterized by a similar mathematical form, once the joint failure forces for pure tension, compression and shear are obtained, the failure criterion for the joint can be approximately derived. With the criterion, one can evaluate a particular board’s failure deflection and loads regardless of boundary/load conditions or board geometry. This will help board manufacturers design boards against overload type of loading environment. 2.4. Failure analysis of tested joints Post-test failure analyses using optical microscopy, scanning electronic microscopy (SEM) and energy dispersive spectroscopy (EDX) are conducted on the specimens. The failed joint specimens due to different loading conditions are illustrated below. 2.4.1. 0° Pure tension Depending on the strength of the individual pads, specimens under tension show either gross bulk yielding which gradually leads to joint failure or pad peel-off that is catastrophic and sudden (Fig. 6a and b). Regardless, the failure loads for the two different failure modes are very close to each other. This implies that the pad adhesive-strength is almost that of solder yield strength, however, depending on the failure mode, the resultant failure strain/ displacement could be vastly different. SEM was conducted to analyze the morphology of the failure surface arising from bulk yielding. Fig. 6c reveals the origin of failure to be at the central region where the macro features are that of distinctive hillocks, characteristic of yield-type failure. The height of the hillock features also suggest that the failure initially occurred within the bulk solder and not at the pad/intermetallic interface. The spatial extent and location of the hillock give an indication of the ductility of the material as well as the loading direction. The hillock is at the center of the pad because the applied load was axial tension.
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At a higher magnification of 1000, microstructural features such as microvoid coalescence or dimple fracture can be observed (Fig. 6d). This is shown by depressions in the microstructure called dimples, which occur from microvoids in places of high local plastic deformation. Dimple size and shape depend on the type of loading and extent of microvoid emergence. When a material is put under uniaxial tensile loading, as in this case, equiaxed dimples with complete rims appear. Shear loading has the same features except the dimples are elongated and in opposite directions. The microstructures for joints that have undergone shear loading will be illustrated in subsequent sections. Energy dispersive spectroscopy (EDX) did not reveal any presence of intermetallics on the failure surfaces of the specimens subjected to tensile loading. Intermetallic failure is thus excluded as a probable failure mode for this load condition. 2.4.2. 30° Tension/shear Optical inspection of the failed specimens for this loading condition showed that almost all joints fail by bulk yielding near the substrate interface. A very small number of samples see failures by pad peel-off, which is one of the dominant failure modes observable for pure tension. For failures occurring via bulk yielding, the hillock is characteristically at the leading/trailing edge of the pad in the direction of shear (Fig. 7a). This is in contrast with the centrally located hillock for 0° tension tested specimens.
Fig. 8a. Less deformation of joint than 0° and 30° loading.
Fig. 7. (a) SEM (incline view) 220 and (b) 400.
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Fig. 8b–d. Finite element simulation of joints undergoing (b) 0° tension, (c) 30° tension/shear, (d) 60° tension/shear.
Fig. 8e–g. (e) ‘‘Smooth” failure surface; (f) elongated dimples with in-complete rims (800 magnification); (g) EDX elemental analysis.
SEM pictures on the resultant failure surfaces show elongated dimples which are representative of microvoid coalescence due to shear loading (Fig. 7b). The existence of these features makes the fracture surfaces appear rough and irregular which is characteristic of ductile fracture. EDX performed on the failure surfaces revealed fracture occurring at the bulk solder and no failure at the intermetallic is found. The solder/Au–Ni–Cu pad interface is believed to be intact for this loading condition. 2.4.3. 60° Tension/shear This set of specimens demonstrates much less deformation of solder prior to failure, unlike those seen for 0° and 30° tension/ shear tests (Fig. 8a). At 60° tension/shear the regions of high stress are located only close to the pad interfaces as opposed to the 0° and
30° tests whereby high stresses are concentrated within the core regions of the solderball. The non-uniformity of stress distribution via the application of the 60° tension/shear load causes much localized stresses at the pad edges, which then causes the joint to fail before much deformation can occur. This is illustrated in the Mises stress contours derived from FE simulation of joints undergoing 0°, 30° and 60° tension/shear of a similar applied load (Figs. 8b–d) whereby regions of high stresses (shown in red) are concentrated at the solder/pad interfaces1. The result is a ‘‘smoother” failure surface
1 For interpretation of color in Fig. 8, the reader is referred to the web version of this article.
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than those of 0° and 30° tension/shear, with failures occurring at the substrate interfaces rather than the solder bulk. Fig. 8e shows the elongated dimples typically associated with shear loading. The size of these dimples is approximately similar to those of 30° tension/shear loading. However, the depths of the dimples are much shallower than their 30° counterpart and the elliptical nature of the dimples are more pronounced (Fig. 8f). Further, the overall number of visible elongated dimples is also much less than those from the 30° tension/shear. Some failed surfaces show failure across the solder/metallic pad layer. Results from EDX confirm the existence of nickel, phosphorus and aluminium in addition to the expected tin and lead elements at the failure surface. Fig. 8g illustrates the region investigated and the results of the EDX analysis. This implies that the fracture surface no longer lies purely at the bulk solder region like those observed for specimens loaded at 0° and 30° directions. These patches of ‘‘anomaly” are usually at the trailing edge and traverse across different materials. The intermetallic (IM) layer in our specimens is expected to be minimal since the samples do not undergo thermocycling. However, from the stress contours derived from FE simulation that demonstrates higher stresses at interfacial regions (for a large angle loading), it can be expected that as the IM layer thickness increases, there could be a higher chance of IM failure if boards are loaded such that joints experience a certain degree of shear in addition to the dominant tension experienced in board flexure. Lastly, it is emphasized that the above failure mode is only observed for 60° tension/shear and comes from the same batch of specimens as that used for other loading conditions.
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2.4.5. 60°, 30° Compression/shear and 0° compression Optical inspection of the failed specimens shows that almost all failures due to compression/shear occur at the substrate/solder interface (Fig. 10a). The solder is observed to shear laterally and is flatter than those of 60° tension/shear. However, the amount of overall deformation is much less than those seen for 0° and 30° tension/shear. The failure interfaces on the ball exhibit the crescent shaped shiny surfaces observed for 60° compression/shear samples (Fig. 10b). At the substrate failure interfaces, visibly deep scratch marks can be seen running along the direction of applied loading. These are caused by the compressive component of the force as the joint is forced to shear. Fig. 10c shows the failure surface via SEM at 550 magnification. Almost all surfaces appear rough. The apparent scratch marks are only unique to specimens experiencing compression/shear loading conditions. These scratch marks replace the dimple-macrostructures seen in tension/shear, and is believed to be due to bulk material movement induced by the compression/shear. For 30° and 0° compression loading, the specimens do not readily produce a failure surface since the stress states are predominantly compressive. General observations show global gross shearing and compression of the solder joint as given in Fig. 10d and e. Since only the yield strength of the joint is needed to generate the failure map, tests were stopped when yield is obvious. However, it is prudent to note that although the solder joint is considerably flattened, it is electrically intact, unlike failure due to other loading conditions. Severely flattened joints may lead to solder bridging. 2.5. Validation of criteria in predicting board-level failures
2.4.4. 90° Shear Fig. 9a and b shows the dominant failure modes of specimens undergoing 90° shearing. The specimens generally exhibit gross bulk solder yielding at the solder/pad interface prior to failure. The amount of solder deformation is also visibly less than those of 0° and 30° tension/shear. The dominant failure mode for this loading condition is bulk solder failure which occurs at very close to the pad interfaces. EDX analyses do not reveal foreign metals except for tin and lead. In addition, no pad peel-off is observed. The failure forces obtained are also the most repeatable for this loading condition and the failure modes observed are also very consistent. The resultant failure surface at the substrate shows a rough morphology, indicating possible dimple formation or yieldtype failure.
The ability of the failure map in Fig. 5 to predict interconnect failures is verified through finite element simulations of the board-level tests. The material properties of the different microelectronic components used in the board-level simulation are tabulated in Table 3. Orthotropic properties are applied to the PCB material where the principal directions are given in Fig. 12b. The post-yield characteristic of solder is obtained by quasi-static compression of bulk solder that is performed separately. The stress– strain curves of solder are given in Fig. 11. Fig. 12a shows the 3D finite element models of the various components as well as the PCB assembly configurations (A), (B) and (C). Fig. 12b shows the 5-point bend simulation of (B). A total of 1296 cylindrical ‘‘solderballs” are modeled in an area array format
Fig. 9. (a, b) Gross bulk yielding at pad interface.
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Fig. 10. (a) Scratch marks on failed surface; (b) crescent shinier surface at trailing edge; (c) SEM of scratched surface (550); (d) gross shear compression of solderjoint; (e) compression of solder joint.
between the PCB and the substrate. The element type for all the parts are C3D8R and the ‘‘solderballs” have 60 elements each. The results from finite element simulation are superposed with experimental data to check for good correlation. Fig. 13a and b shows the force–displacement and board strains response between simulation results and experimental data for configuration (A). STPX and STPY denote the experimental strains obtained on the face of the PCB attached to the substrate in the transverse and longitudinal directions, respectively. The exercise serves to illustrate
the accuracy and quality of the FE model before solder joint forces are extracted. The finite element simulations are performed without the modeling for failure of the joints. The jobs are completed when the displacement-to-failure determined from the experiments have been achieved. The corner joint section forces are then extracted from the joint/substrate interface and superposed onto the plot of the single joint failure map to ascertain the ability of the latter in predicting quasi-static board-level joint failures. Fig. 14 shows the
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L.B. Tan et al. / Microelectronics Reliability 49 (2009) 397–409 Table 3 Material properties of components. Components
Young’s modulus (GPa)
Yield/hardening (MPa/ep)
Poisson’s ratio
Density (kg/m3)
Dimensions (mm)
PCB (orthotropic)
El/E2: 16.85, E3:7.375 (out-of-plane) G12:3.4, G13/G23:2.25 12.5 110
180,0 280, 0.01 330, 0.02 100,0; 215,0.006 Nil
m13: 0.39 m23: 0.39 ml2: 0.11
2177
Refer to Table 2
0.3 0.3
2112 8600
40 40 1.5 40 40 2.14
20.4 180 195
Refer to Fig. 11 Nil Nil
0.363 0.3 0.3
8400 2330 8025
Ht: 450 l, cia: 550 l (cylindrical) Big: 12 12 0.4, small: 5 5 0.4 Contact dia: 11.2
Substrate Heatspreader (brass) used only in PCB (B) Solderballs Silicon die Steel plunger
Where El, E, BP G12.G13.G23, m13, m23 and m12 are the orthotropic moduli and poisson’s ratio in the respective corrponent directions. The PCS and substrate post-yield properties are input into Abaqus in tabular form.
2.6. Failure mode compatibility between board and single joint failures After the completion of the respective board-level tests, the failed joints are inspected to determine their failure modes.
Fig. 11. Stress–strain curves of bulk Sn-37Pb solder under quasi-static loading.
single joint failure map together with the corner joint forces obtained from the FE simulation at the end of each simulation. In Fig. 14, the circles denote the forces within the corner solder joints from FE simulations of board assemblies at the same load conditions that caused joint failures in actual board tests. It can be observed that the circles lie closely to the failure map indicating the validity of the single joint failure map in predicting board-level failures.
2.6.1. A. Corner joint failure for board configurations A and B The failure modes of the joints for board test configurations A and B are jointly discussed since both employ similar 5-point bend test method and have considerably higher corner joint tensile force than shear as reflected in Fig. 14. The breakdown of the failure modes observed for the individual corner joints are given in Table 4. Fig. 15a depicts joint failures whereby the corner joint is distinctively detached justifying the legitimacy of using daisy chain/ strain gauge technique in detecting failure. Since the corner joints have visibly failed, the package is pried open delicately to reveal the failure surfaces. Fig. 15b confirms the pad peel-off failure mode experienced by the corner joints. SEM/EDX of the pad peel-off surface on the solder joint shows the presence of copper, nickel and zinc. This is given in Fig. 16a. However, the same analysis yields absolutely no traces of such metals on the remaining PCB pad (Fig. 16b) – the result exactly reproduced that for the pure tension testing of the single joints. It can thus be concluded that if failure at the pad occurs, it will certainly be within the PCB matrix material, since the bonds at the Cu/ Ni pad and solder are much stronger than that at the Cu/Ni and FR4 interface. For corner joints and adjacent joints which do not fail by pad peel-offs, the resulting failure surface exudes the typical dimple fractography. This has been characterized in the previous section
Fig. 12a. Overview of PCB layout (A), (B) and (C) for Abaqus simulation (only (B) has a brass heatspreader over the substrate).
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Fig. 12b. 5-Point bend simulation for board (B).
Fig. 14. Joint force evolution and failure map.
The post-test inspections, in addition to the finite element results, show that not only are the board-level joint failures due to the 5-point bend test correctly predicted, their failure modes are also correctly characterized.
Fig. 13. (a) Force–displacement correlation; (b) board strains correlation.
to be failure attributable to dominant tension. EDX analysis of the surfaces shows no sign of intermetallic failure and hence failure occurs within the bulk solder. Fig. 17a and b illustrates the typical failure morphology for the corner and adjacent joints.
2.6.2. B. Joint failures from board configuration C The loading conditions for configuration C are such that the joints experience both tension and shear. The failure modes of the corner joints closest to the shear blade and that at the bottom edge of the substrate are speculated to be different due to the different stress states experienced by the solders. Table 5 depicts the different types of failure modes observed from board samples. Close-ups of the joints at the region closest to the shear blade reveal that the outermost layer of joints whereby joint forces are predominantly tensile, experience pad peel-off failures, as illustrated in Fig. 18(a). The corresponding solder joint failure forces (overlay with the failure map) are given in Fig. 14 (Board (C) – top edge). In addition, large deformation of the joints is observed for the immediate subsequent inner rows of joints. SEM of the substrate pad surfaces reveals hillocks at the trailing edges and is illustrated in Fig. 18(b). The nature of joint deformation exhibits one due to a combined tension and shear loading (Fig. 7). A few of the corner joints also failed via pad peel-off. The different failure modes for progressively internal joints of the bend-shear specimens are in tandem with FE simulation findings which illustrated dominant tension for outermost joints on the top edge and progressively dominant shear for the more inte-
Table 4 Failure modes observed for corner joints. Board configuration
Sample no.
Observed failure mode
Predicted failure mode (based on location at failure map)
A (without heatspreader)
1 2 3 4 5 6
Pad Pad Pad Pad Pad Pad
Pad peel-off
B (with heatspreader)
peel-off peel-off peel-off peel-off peel-off peel-off
(3) (2) (3) (3) (4) (4)
Intact (1) intermetallic (1) intact (1) intact (1) intermetallic (1)
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Fig. 15. (a) Corner joint failures; (b) pad peel-offs.
Fig. 16. (a) SEM/EDX analysis on ball; (b) SEM/EDX analysis on pad.
Fig. 17. (a) Morphology by SEM for corner joint; (b) morphology by SEM for adjacent joints.
rior joints as caused by the combined bending and shearing of the package. Close-ups of the joints at the region furthest away from the blade reveal significant joint shearing and compression, as oppose to tension. As a result, the predominant failure mode found at this region is solder bulk yielding. Fig. 18c illustrates the joint failures experienced at this region. The corresponding solder joint failure
forces (overlay with the failure map) are given in Fig. 14 (Board (C) – bottom edge). SEM/EDX of these joints reveals scratch marks on the failed surfaces, apparently due to the compression/shear induced on the joints (Fig. 18(d)). Since these scratch marks have also been reported in ball-shear tests, the implication is that the loading caused by the ball shear consists of significant amounts of compression,
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Table 5 Failure modes observed for failed joints. Board configuration
No.
Observed failure mode (corner joints)
Observed failure mode (region)
Predicted failure mode (based on location at failure map)
C (Combined bend-shear)
1
Top edge Bottom edge Top edge Bottom edge Top edge Bottom edge
Top region Bottom region Top region Bottom region Top region Bottom region
Pad peel-off Intermetallic/solder bulk Pad peel-off Intermetallic/solder bulk Pad peel-off Intermetallic/solder bulk
2 3
Intermetallic Intermetallic/solder bulk shear Intermetallic/pad peel-off Solder bulk shear/compression Elongated solderball Solder bulk shear/compression
Pad peel-off Solder bulk Pad peel-off Solder bulk Pad peel-off Solder bulk
Fig. 18. (a) Pad peel-offs for outermost joints and large joint deformation at inner layers (region closest to shear blade); (b) hillocks at trailing edge; (c) shear/compression of joints; (d) scratch marks signifying a compressive/shear load.
and thus joint strength values obtained from the methodology are not representative of board bend or drop failures whereby tension/ shear loading to the joints are expected. No elongated dimples are observable since they could most probably be flattened out. It can be summarized that the observed failure modes on the board samples do coincide with that predicted from the failure map when the region of joints is collectively considered as a whole. However, some corner joints do not uphold the failure modes prediction. The discrepancy is believed to be due to the complexity of the board loading conditions. 3. Conclusions It is demonstrated that the failure mapping obtained from single joint tests predicted board-level joints failure well. Not only is the instant of joint failure well-predicted for different load cases, the failure modes of the joints are also predicted. This illustrates the independent nature of the failure mapping methodology in effectively predicting board failures due to combined loading on various board geometries with different boundary conditions.
Furthermore, the characteristics of the failure surfaces and failure modes due to the different loading conditions have also been identified and characterized and will help researchers in their failure analysis of board-level joints as one may then deduce the load history accrued to them just from the fractography created. A mathematical failure criterion has also been formulated and may be implemented to FE modeling to save computational time and costs. Preliminary board assembly designs against vibration, impact or static loads can then be effectively and accurately evaluated by FEA without the need to go through prototype testing. The methodology may be extrapolated to different types of solders, solderball dimension and pad finishes and even newer forms of board-level interconnect. References [1] Jinlin Wang, Lim HK, Lew HS, Woon Theng Saw, Chew Hong Tan. Peel test metrology for solder joint reliability of FCBGA packages. In: Electronics components and technology conference, IEEE; 2003. [2] Jason Bragg, Justine Bookbinder, George Sanders, Blake Harper. A nondestructive visual failure analysis technique for cracked BGA interconnects. In: Electronic components and technology conference, IEEE; 2003.
L.B. Tan et al. / Microelectronics Reliability 49 (2009) 397–409 [3] Lau John H. Solder joint reliability of flip chip and plastic ball grid array assemblies under thermal, mechanical, and vibrational conditions. IEEE Trans Compon Pack Manuf Technol Part B 1996;19(4) [November 1999]. [4] Tong Yan Tee, Hun Shen Ng, Chwee Teck Lim, Eric Pek, Board level drop test and simulation of TFBGA packages for telecommunication applications. In: Electronic components and technology conference, IEEE; 2003. [5] Tee Tong Yan, Ng Hun Shen, Lim Chwee Teck, Pek Eric, Zhong Zhaowei. Drop test and impact life prediction model for QFN packages. J SMT 2003;16(3).
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[6] Wung P. A force-based failure criterion for spot weld design. Exp Mech 2001:107–13. [7] George Hsieh, Alan Mcallister. (Intel Corporation). Flip chip ball grid array component testing under board flexure. In: Electronic components and technology conference, IEEE; 2005. [8] Tan LB, Seah SKW, Wong EH, Xiaowu Zhang, Tan VBC, Lim CT. Board level solder joint failures by static and dynamic loads. In: Electronics packaging and technology conference, IEEE; 2003.