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Matching of GaAs power FETs using a large-signal modelling technique
cuits. It is concluded that, for this application, the harmonic balance method is faster and more accurate than the other solution methods. (18 refs.)
Matching of GaAs power FETs using a large-signal mod. elling technique A.J. HOLDEN, B.T. DEBNEY, J.P. KING, J.G. METCALFE, C.H. OXLEY (Plessey Res. Ltd., Allen Clark Res. Centre, Towcester, England) IEE Proc. H (GB) vol. 133, no. 5, pp. 399-404 (Oct. 1986) A large-signal modelling program based on fundamental frequency harmonic balance is descibed. The model uses nonlinear elements derived from bias-dependent Sparameter measurements and proves to be computationally efficient and suitable for use in modelling power FETs. Simulated output powers and gains as a function of output impedance are presented for the Plessey 4820 power FET. Results from a narrow-band prematched module designed using the large-signal model are presented showing output power within 0.5 dB of the theoretical maximum in the 7.9 to 8.4 GHz band. This was achieved without the need for any fine tuning. (8 refs.) Simulation of bipolar high-voltage devices in the neighbourhood of breakdown Q. WU, F.E. CELLIER (Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA) Math. & Comput. Simulation (Netherlands) vol. 28, no. 4, pp. 271-84 (Aug. 1986) This paper investigates numerical techniques for the solution of the system of nonlinear elliptic PDEs that simulates bipolar semiconductor devices under high reverse bias voltage. Bipolar devices are usually modeled as a set of three elliptic PDEs representing the field equation and the electron and hole current continuity equations. However, these equations can be solved effectively in the case of low-voltage devices only, e.g. by use of the BAMBI program. As shown in this paper, it is possible to simplify the model in case of high-voltage devices. A powerful software toolkit, ELLPACK, is used to solve the resulting two-dimensional Poisson equation. ELLPACK enables numerical solution techniques to be compared for their efficiency to solve this problem. To analyse the effectiveness of the toolkit as a whole, a comparison is made between ELLPACK and a special-purpose program. (I0 refs.) Bit-map CAD system of IC design employing BIT-I language H. KOIDE, C. KIM, K. SHONO (Fac. of Sci. & Technol., Sophia Univ., Tokyo, Japan) Trans. Inst. Electron. & Commun. Eng. Jpn. Part C (Japan) vol. J69C, no. 8, pp. 956-63 (Aug. 1986). In Japanese. The LSI design language BIT-I for a bit map CAD system is constructed on a personal computer. The system has maskpattern design, design rule check, circuit parameter extraction, simulations and data conversion programs. Data processing programs of design rule 44
check and circuit parameter extraction have a mainprogram able to call sub-programs consisting only of logic operations. Only a main-program can be modified, when design rules depending on a wafer process or a device parameter have changed. (6 refs.)
Multiquantity intelligent measurement system for investigating thermal properties of semiconductor devices K. KOWALSKI, H. CHACINSKI, A.J. WIECKOWSKI (Inst. of Radioeleetron., Techn. Univ. of Warsaw, Poland) 5th International IMEKO Symposium on Intelligent Measurement, Jena, Germany, 10-14 June 1986 (Budapest, Hungary: IMEKO 1986) vol. 2, pp. 231-3 The computerised system described enables testing of diodes or transistors by heating the device with continuous or pulse current and measuring various quantities such as junction temperature and thermal resistance. (I ref.) VLSI design methodology for ASIC development B. L E K S E L L 12th Nordic Semiconductor Meeting. Proceedings, Jevnaker, Norway, 8-11 June 1986 (Oslo, Norway: Center Ind. Res. 1986) p. 85 Summary form only given, as follows. Double level metal CMOS technology with 1.6 micron effective channel length permits integration levels up to 40K gates, using structured design techniques. A compiler cell library has been developed to support such structured design methodologies and includes ROM, RAM, PLA and pipe-line/test registers, together with other large functional blocks to permit true system integration in silicon. The author describes the fundamental methodology and describes the compiler cells, together with the "Cell Gen" software which generates the compiler cells and their associated simulation and verification models. Consideration is given to design-for-test and provision of special cells which the designer can use to enhance the testability of complex designs. The design methodology takes the system designer one step towards silicon compilation by encouraging the use of a designer's own engineering workstation to simulate designs and take the flow through all the design stages to a post routing simulated database, while providing assistance with the trade offs necessary for an optimum design. CAD-images of process spread J. KILANDER (R1FA, Stockholm, Sweden) 12th Nordic Semiconductor Meeting. Proceedings, Jevnaker, Norway, 8-11 June 1986 (Oslo, Norway: Center Ind. Res. 1986) p. 90 Summary form only given. Since an IC process will inevitably have a certain spread, it is important to take due account of this in circuit simulation. A CAD level process image must be formed, and it should be realistic. Too conservative images will leave process potential unexploited, and too liberal images will make the customers leave you. Ring oscillators fabricated in a 2#-CMOS process were measured for frequency, and the same structure was simulated with HSPICE using several CAD-images of process spread.
Matching of GaAs power FETs using a large-signal mod. elling technique A.J. HOLDEN, B.T. DEBNEY, J.P. KING, J.G. METCALFE, C.H. OXLEY (Plessey Res. Ltd., Allen Clark Res. Centre, Towcester, England) IEE Proc. H (GB) vol. 133, no. 5, pp. 399-404 (Oct. 1986) A large-signal modelling program based on fundamental frequency harmonic balance is descibed. The model uses nonlinear elements derived from bias-dependent Sparameter measurements and proves to be computationally efficient and suitable for use in modelling power FETs. Simulated output powers and gains as a function of output impedance are presented for the Plessey 4820 power FET. Results from a narrow-band prematched module designed using the large-signal model are presented showing output power within 0.5 dB of the theoretical maximum in the 7.9 to 8.4 GHz band. This was achieved without the need for any fine tuning. (8 refs.) Simulation of bipolar high-voltage devices in the neighbourhood of breakdown Q. WU, F.E. CELLIER (Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA) Math. & Comput. Simulation (Netherlands) vol. 28, no. 4, pp. 271-84 (Aug. 1986) This paper investigates numerical techniques for the solution of the system of nonlinear elliptic PDEs that simulates bipolar semiconductor devices under high reverse bias voltage. Bipolar devices are usually modeled as a set of three elliptic PDEs representing the field equation and the electron and hole current continuity equations. However, these equations can be solved effectively in the case of low-voltage devices only, e.g. by use of the BAMBI program. As shown in this paper, it is possible to simplify the model in case of high-voltage devices. A powerful software toolkit, ELLPACK, is used to solve the resulting two-dimensional Poisson equation. ELLPACK enables numerical solution techniques to be compared for their efficiency to solve this problem. To analyse the effectiveness of the toolkit as a whole, a comparison is made between ELLPACK and a special-purpose program. (I0 refs.) Bit-map CAD system of IC design employing BIT-I language H. KOIDE, C. KIM, K. SHONO (Fac. of Sci. & Technol., Sophia Univ., Tokyo, Japan) Trans. Inst. Electron. & Commun. Eng. Jpn. Part C (Japan) vol. J69C, no. 8, pp. 956-63 (Aug. 1986). In Japanese. The LSI design language BIT-I for a bit map CAD system is constructed on a personal computer. The system has maskpattern design, design rule check, circuit parameter extraction, simulations and data conversion programs. Data processing programs of design rule 44
check and circuit parameter extraction have a mainprogram able to call sub-programs consisting only of logic operations. Only a main-program can be modified, when design rules depending on a wafer process or a device parameter have changed. (6 refs.)
Multiquantity intelligent measurement system for investigating thermal properties of semiconductor devices K. KOWALSKI, H. CHACINSKI, A.J. WIECKOWSKI (Inst. of Radioeleetron., Techn. Univ. of Warsaw, Poland) 5th International IMEKO Symposium on Intelligent Measurement, Jena, Germany, 10-14 June 1986 (Budapest, Hungary: IMEKO 1986) vol. 2, pp. 231-3 The computerised system described enables testing of diodes or transistors by heating the device with continuous or pulse current and measuring various quantities such as junction temperature and thermal resistance. (I ref.) VLSI design methodology for ASIC development B. L E K S E L L 12th Nordic Semiconductor Meeting. Proceedings, Jevnaker, Norway, 8-11 June 1986 (Oslo, Norway: Center Ind. Res. 1986) p. 85 Summary form only given, as follows. Double level metal CMOS technology with 1.6 micron effective channel length permits integration levels up to 40K gates, using structured design techniques. A compiler cell library has been developed to support such structured design methodologies and includes ROM, RAM, PLA and pipe-line/test registers, together with other large functional blocks to permit true system integration in silicon. The author describes the fundamental methodology and describes the compiler cells, together with the "Cell Gen" software which generates the compiler cells and their associated simulation and verification models. Consideration is given to design-for-test and provision of special cells which the designer can use to enhance the testability of complex designs. The design methodology takes the system designer one step towards silicon compilation by encouraging the use of a designer's own engineering workstation to simulate designs and take the flow through all the design stages to a post routing simulated database, while providing assistance with the trade offs necessary for an optimum design. CAD-images of process spread J. KILANDER (R1FA, Stockholm, Sweden) 12th Nordic Semiconductor Meeting. Proceedings, Jevnaker, Norway, 8-11 June 1986 (Oslo, Norway: Center Ind. Res. 1986) p. 90 Summary form only given. Since an IC process will inevitably have a certain spread, it is important to take due account of this in circuit simulation. A CAD level process image must be formed, and it should be realistic. Too conservative images will leave process potential unexploited, and too liberal images will make the customers leave you. Ring oscillators fabricated in a 2#-CMOS process were measured for frequency, and the same structure was simulated with HSPICE using several CAD-images of process spread.