MDS: A design methodology for switched reactance systems

Mathl. Comput. Modelling Vol. 17, No. 8, pp. 3-10, Printed in Great Britain. All rights reserved

1993 Copyright@

03957177193 $6.00 + 0.00 1993 Pergamon Press Ltd

MDS: A DESIGN METHODOLOGY FOR SWITCHED REACTANCE SYSTEMS R. SOTUDEH School of Science and Technology, University of Teesside Middlesbrough,

Cleveland, TSl 3BA, U.K.

(Received and accepted December

1992)

Abstract-There are many proven formal techniques for design and simulation of digital or analogue systems and circuits. Such techniques are rather cumbersome, and at times inefficient, when they are employed in the design of systems containing both analogue and digital subsystems. This inefficiency, in the majority of cases, leads to separate design methodologies being employed and the designed sub-systems to be brought together at a later stage. The late merger of the designed subsystems also results in further complications and incompatibilities. This paper proposes a technique, referred to as the MDS, for the design of switched reactance (inductive and capacitive) systems. The proposed method is applicable to both event-driven and predefined switching systems. The results submitted reflect the suitability of the method for both software simulation and hardware realisation techniques. It also plays an important role during the hardware debugging stage.

INTRODUCTION Many power electronic systems operate at power frequencies and energies and use Thyristor switches to perform the necessary switching operations. Their operational characteristics are regulated by discrete switching patterns. In an open-loop system, the switching patterns are generated from a pre-defined sequence. In a closed-loop system, the switching patterns may follow a certain sequence with the sequence changing as a function of the system feed-back parameters. In either case, the switching pattern may be synchronised to the supply. If during the separate (or singular) design phases the more infrequent operational conditions are neglected or overlooked, then it may give rise to operational problems when faced with the unaccounted. It is, therefore, of paramount importance to ensure that the switching pattern, for both the closed-loop and open-loop systems, does not fall out of the prescribed sequence at any time. SWITCHED

CAPACITOR

COMPENSATION(SCC):

A CASE

STUDY

For the purpose of demonstrating the design steps, references will be made to the classical switched capacitor network employed for suppression of the white-noise type of disturbance, caused by lagging reactive power flow, on transmission lines [l]. This type of network is usually binarily weighted and Thyristor switches are provided for the necessary switching requirements. The binary weighting of the capacitive arms will provide a linear susceptance variation in direct proportion to the regulation parameter ‘VARreg.’ The diagram in Figure 1 illustrates the system overview and equation (1) shows the simplified relationship between ‘VARreg’ and the various system parameters.

where Vpcc(max) phase angle.

VARreg =

Vpcc(max) Jz

Iload Jz sin(d),

= peak supply voltage;

Iload(max)

= peak load current;

and 4 = load current

Typeset 3

by &S-w

R. SOTUDEH

SOUKZ Networli Switched

Capacitor Compensalor

I

I

I

_SUDDIY

I

I

I

I

T%ta

Synchronisalion

VARngJin (n-bit wide)

Figure 1. Switched capacitor compensator

(SCC).

The system’s ideal operation can be summarised as follows: The randomly varying inductive load creates lagging reactive current flow through the Source network, hence, creating random fluctuations on the supply lines. An assessment of the random fluctuations, ‘VARreg,’ is obtained using one of the many measurement techniques available and applicable to the type of load under compensation 121. (b) The computed parameter, ‘VARreg,’ is then quantised to produce an n-bit unsigned binary number, VARreg-bin, representing the magnitude of the assessed reactive power flow. The number of capacitive arms is equal to n , the length of the quantised parameter. The largest capacitive arm is selected by the Most Significant Bit of ‘VARreg-bin,’ Vbn - 1, and the smallest capacitive arm by the Least Significant Bit, VbO. This particular configuration will accommodate the linear relationship between the reactive power flow and the amount of capacitive susceptance selected by the n-bit binary pattern. At Cc) successive supply peaks the selected capacitive arms will be switched into the supply, hence creating a proportional amount of leading reactive power. The generated leading reactive power will be counteracted by the earlier measured lagging reactive power, hence leaving the transmission lines free from any reactive disturbance. (4 This process is repeated regularly to minimise the supply network disturbances, and its effectiveness over shorter integration periods is purely a function of the accuracy of the measurement algorithms employed in assessing ‘VARreg.’

(4

The system relies on transient-free switching of the capacitive elements. Transient-free switching can only take place when the voltage across a capacitor is equal to the instantaneous supply voltage and the resultant current at the instant of switching is zero. The two conditions specified above can only be satisfied if the capacitors are charged to the peak of the supply and switching takes place at the instant when the supply is at its peak. To minimise the supply network fluctuations the compensator must continually adjust its VAr absorption by closely tracking the random fluctuations. This leads to different capacitors being left with different charges across them as the switching pattern, ‘VARreg-bin,’ changes from instant to instant. The deposited charge must also be topped-up to the appropriate supply peak in order to satisfy the transient-free switching criterion. There are, therefore, two distinct modes of operation that exist and must be satisfied by appropriate switching of the Thyristor switches. The mode during which a capacitor is switched into the supply and is carrying leading current is termed the ‘compensation,’ and the mode whilst a capacitor is switched out of the supply, simply because it was not selected at the last evaluation

Switched reactance systems

5

of ‘VARreg-bin,’ is termed the ‘stand-by’ mode. It is the role of the ‘Digital Sequential Controller’ to satisfy the switching needs of the two modes of operation. MNEMONIC

DOCUMENTED

STATE

DIAGRAM

(MDS)

The following procedure outlines the design steps required to form an MDS diagram using ‘Digital Sequential Controller’ as a vehicle for the basis of the design. The exercise must commence by identifying a relationship between the MDS and the actual system parameters. The MDS philosophy is based on transitional states with each state denoting an actual event taking place. The diagram in Figure 2 illustrates the hierarchical relationship between the physical system parameters and an MDS state or node. The circular node carries its state label depicting the actual action or event that would follow upon entering that state. A state must belong to a mode and should always appear under a column bearing the operational mode name. The top sector of each node denotes the prescribed condition under which the state can be entered, and the bottom sector indicates the before and after conditions of an observed state attribute. In the MDS node shown in Figure 2, the state corresponds to the switching of Thyristor An (the event) during the positive supply half cycle (the prescribed condition) and having deposited a positive charge (the observed attribute) on its capacitor before switching took place (condition of attribute before) and leaving a positive charge on its capacitor after the switching has taken place (condition of attribute after). ---_-c-c

mode

Figure 2. State and system relationship. There are four possible states, since a capacitor may have a +ve or -ve charge deposited on it, and may be requested to operate in any one of the two modes, of compensation or stand-by. The diagram in Figure 3 illustrates the final MDS for the uni-polarised switched capacitor compensator. The MDS diagram conforms to the prescribed conditions required for transientfree switching outlined earlier.

Stand-by= cmp

5

cmp

1

8

Figure 3. MDS for basic SCC. The two column headings of ‘stand-by’ and ‘cmp’ denote the stand-by and compensation modes bf operation, respectively. The Boolean variable ‘cmp’ equals 1 for compensation and 0 for

stand-by.

6

R. SOTUDEH

The arrows, connecting nodes, denote the permissible switching paths that exist between states. These paths can only exist between two states with the originator state having the same polarity after switching (observed attribute) as the destination (next) state’s polarity before switching (observed attribute). The following explains in detail the nature of the permissible paths in Figure 3. [pathl] This path implies the next switching state to be An. This path is taken for as long as the particular capacitor arm is in a ‘stand-by’ mode and has had a +ve charge deposited on it due to the last switching action. The polarity of the capacitor charge (observed attribute) before and after switching is +ue, with switching taking place at the +ve peak of the supply (prescribed condition). [path21 This path implies the next switching state to be Bn. This path is taken for as long as the particular capacitor arm is in a ‘stand-by’ mode, i.e., cmp= 0, and has had a -ve charge deposited on it due to the last switching action. The polarity of the capacitor charge (observed attribute) before and after switching is -we, with switching taking place at the -ve peak of the supply (prescribed condition). [path31 This path implies the transition from stand-by to compensation mode with Bn N being the next state. (path41 This path implies the transition from stand-by to compensation mode with An N being the next state. [path51 This path implies the transition from compensation to stand-by mode with An being the next state. [path61 This path implies the transition from compensation to stand-by mode with Bn being the next state. [path71 This path implies the next switching state to be An N. [path81 This path implies the next switching state to be Bn N. The transitions between An N and Bn N via [path 7] and [path 8] continue for as long as the system is in a compensation mode, i.e., cmp = 1. EXTRACTION

OF BOOLEAN

EQUATIONS

The identified paths are used to define the logical conditions under which transition between states can be made. There are 8 paths and, therefore, there must be eight separate Boolean equations defining each path. The terms in the equations, which define the transition to the next state, are simply a logical AND relationship between: (i) the next state’s operational mode, (ii) the prescribed condition, (iii) the previous (or origin) state. This leads to the following 8 equations: [pathl] = (cmp)(V+)(An) [path21 = (cmp)(V-)(Bn) [path31 = (cmp)(V+)(An) [path41 = (cmp)(V-)(Bn) [path51 = (cmp)(V+)(An

-)

[path61 = (m)(V-)(Bn

-)

[path71 = (cmp)(V-)(Bn

-)

[path81 = (cmp)(V+)(An

-).

The condition prescribing the transition to each state is merely the logical OR relationship of the paths leading to that state. The Boolean equation defining the transition into the various

Switched reactance systems

states is therefore given as: An = [pathl] + [path51 An = {(cmp)(V+)(An)}

(2) + {(cmp)(V+)(An

-)}

+ {(cmp)(V-)(Bn

-)}

Bn = [path21 + [path61 Bn = {(cmp)(V-)(Bn)}

(4)

An - = [path41 + [path71 An N =

{(cmp)(V-)(Bn)l + {(cmp)(V-)(Bn

-)I

(7)

-)I.

(9)

(3)

{(cmp)(V+)(An)l + {(cmp)(V+)(An

MODULATRITY

(5) (6)

Bn N = [path31 + [path81 Bn N =

(3)

AND FLEXIBILITY

Let us now consider the situation where the existing system’s specification changes due to enhancement or modification. To show the versatility of the MDS notation, let us consider the switched capacitor compensator (SCC) again. In practice, the High Voltage capacitors employed in the SCC will be subject to long periods of polarisation. This prolonged subjection to a DC voltage results in Dielectric dissociation. For this reason the capacitors must be repolarised at regular intervals. This leads to the establishment of yet another mode of operation. For the purposes of this paper, only the suggested repolarisation network is shown in Figure 4. The repolarisation network consists of two back-toback Thyristor switches connected across a capacitor arm, forming an oscillator. The value of the inductor in series with the capacitor (the inductor is used to limit the rate of rise of current in the Thyristor switches) must be chosen such that the resonant frequency of the repolsxisation network is much greater than the supply frequency. The repolarisation of a capacitor can be achieved by the switching of only one of the two Thyristors, Cn or Dn. For example, if the polarity of charge across the capacitor was +ve, then by switching Cn the polarity of charge across the capacitor will change to -ve, due to half a cycle of natural oscillation in the repolarisation network. In practice, such a network can not be used for large scale compensation due to large repolarisation currents.

/ Repolarisatlon

m0dc

Figure 4. State and system relationship.

The MDS diagram can now be modified to include the new states and mode. The diagram in Figure 5 illustrates the three modes of stand-by, repolarisation, and compensation. The Boolean variable denoting the modes of operation must now be two bit wide to accommodate the newlyintroduced repolarisation mode. The permissible paths shown in dashed-line format are those that could exist between the nodes but need to be inhibited in order to maximise the efficiency of operations. The inhibition of such paths, and hence their exclusion from the final Boolean equations, will prevent the possibility of transition between their respective states. This is due to the simple fact that repolarisation may only be applied in stand-by mode (implied by the inclusion of [path 91 through to [path 121) since in the compensation mode, the capacitors are

R. SOTUDEH

8

subjected to an AC voltage at all times and hence, there is no need for repolarisation. Similarly, the paths joining Cn and Dn are also inhibited to prevent continuous repolarisation. The paths showing transitions from repolarisation to compensation mode are permissible, i.e., [path 13) and [path 141, since they do not infringe the transient-free criterion.

8

Figure 5. MDS for SCC with repolarization

network.

It must be pointed out that, due to the configuration of the repolarisation network, the said process can take place at any instant or supply cycle since it is supply independent. This explains the (V+) OR (V-) logical relationship that appears in the prescribed condition sector of the Cn and Dn nodes. A new set of equations must now be derived from the diagram to include the newly-introduced states. An = [pathl] + [path51 + (path121 Bn = [path21 + [path61 + [path101 An N = [path41 + [path71 + [path131 Bn N = [path31 + [path81 + [path141 Cn = [path91 An = [pathll]. STATE

REDUCTION

The technique allows for rationalisation, once all the states have been clearly defined in terms of their permissible paths. This process commences by identifying all the states that represent the same switching device (or the same physical component). In the case of the SCC, the states An and An N represent the switching action of the Thyristor switch ‘An.’ Similarly, Bn and Bn N represent the switching action of the Thyristor switch ‘Bn.’ This leads to the logical OR relationship of the terms defining their respective states. An = [pathl] + [path51 + [path121 + [path41 + [path71 + [path131 Bn = [path21 + [path61 + [path101 + [path31 + [path81 + [path141 Cn = [path91 Dn = [pathll]. After simplification, the above set of equations are defined as follows. An = (cmp)(V+)(An

+ Dn) + cmp(V-)(Bn

+ Cn)

Bn = (cmp)(V-)(Bn

+ Cn) + cmp(V+)(An

+ Dn)

Cn = repAn((V+)

+ (V-))

Dn = rep Bn((V+)

+ (V-)),

Switched reactance systems

9

CLRQ Q.

--

bn

f-->

Cn

v

‘”

Y Figure 6. Digital sequential controller for the SCC.

nn”““““““““““”

v+

v-““““““““““““““” cmp mP An

I

n n

rl

n n

Bn

n n

n: n

tn

n

qn\

n standby

\

1 repolarisation standby \‘/

,I, A

I””

n n?

i n I I / n I I / I I I 0 ; mpolarisation & ,n, standby p

Cn

Dn

I

“_

>

Figure 7. Sample timing for the MDS.

where ‘rep’ is a two bit Boolean variable denoting the repolarisation mode. The equations above represent the ‘next state’ (left hand side) Boolean conditions as a function of their previous states (right hand side). To signify the difference in time of the terms on the either side of the equations (lo)-(12), the ‘previous state’ labels should be changed to lower-case.

An = (cmp)(V+)(an

+ dn) + cmp(V-)(bn

+ cn)

(14

Bn = (cmp)(V-)(h

+ cn) + cmp(V+)(an

+ dn)

(15)

Cn = repan((V+)

+ (V-))

(16)

Dn = repbn((V+)

+ (V-)).

(17)

The above equations are now in a form suitable for realisation in hardware (digital synchronous operations using D-type Flip-Flops representing a state) as shown in Figure 6, or could be used to form the nucleus of a software simulation module that would depict the switching sequences of the system under consideration. The diagram in Figure 7 illustrates the switching pattern for all a particular operational scenario. The MDS notation, in the form presented, has been successfully used to design and construct a Uni-polarised SCC with better than 30% improvement factor in elimination of the white-noise

10

R. SOTUDEH

type of disturbances [l]. It has also been used in the design of a package used in simulation of Static reactive power compensators [3]. Additionally, it has proved to be an invaluable teaching aid in the design of digital systems with clearly defined, event or non event-driven, switching sequences. CONCLUSIONS The MDS notation is shown to be a versatile tool in the design of event-driven systems. A direct relationship exists between the states (problem specification and state identification stage), analogue or digital switching devices (state identification stage), and bi-stable devices (implementation stage). The ease of state identification and specification makes the notation ideal for defining complex switching patterns. The hierarchical representation of the MDS notation eases the diagnosis of the specified problem. The rigid rules governing the existance and inhibition of paths will minimise the possibility of errors at the problem specification and analysis stages. REFERENCES 1. FL Sotudeh and J. Holmes, High speed switched capacitor reactive power compensator, Proceedings of the 20th Universities Power Engineering Conference, U.K., (April 1985). 2. S. Etminan and R. Sotudeh, Fast converging reactive power measurement techniques for high speed static VAr compensators, Presented at the 22 nd Universities Power Engineering Conference, U.K., (April 1987). 3. S. Etminan, R. Kitchen and R. Sotudeh, Computer simulation of two types of thyristor switched capacitor compensators, Presented at the 7 th International Conference on Mathematical and Computer Modelling, Chicago, (August 1989).