Metallization and nanostructuring of semiconductor surfaces by galvanic displacement processes

Surface Science Reports 62 (2007) 499–525 www.elsevier.com/locate/surfrep

Metallization and nanostructuring of semiconductor surfaces by galvanic displacement processes Carlo Carraro a , Roya Maboudian a,∗ , Luca Magagnin b a Department of Chemical Engineering, University of California, Berkeley, CA 94720, USA b Dipartimento di Chimica, Materiali e Ing. Chimica G. Natta, Politecnico di Milano, Milan, Italy

Accepted 8 June 2007

Abstract The deposition of metals on semiconductors encompasses a broad range of technologically important processes, with applications ranging from electronic devices to chemical sensors. Recent years have witnessed a surge of research activities in galvanic displacement processes on semiconductor substrates. After a brief review of the fundamental aspects underlying galvanic displacement processes on semiconductor surfaces, this paper discusses applications to micro- and nanoscale devices, including schemes developed for the metallization and nanopatterning of semiconductor substrates with high selectivity and with optimal interfacial properties. c 2007 Elsevier B.V. All rights reserved.

Keywords: Galvanic deposition; Metalization; Semiconductor surfaces; Electrodeposition; Electroless deposition

Contents 1. 2.

3.

4.

5.

Introduction and roadmap ........................................................................................................................................................ 500 Electrolytic and electroless plating ............................................................................................................................................ 500 2.1. Electrodeposition .......................................................................................................................................................... 500 2.2. Autocatalytic deposition ................................................................................................................................................ 501 2.3. Galvanic displacement ................................................................................................................................................... 501 Electrochemistry of semiconductors .......................................................................................................................................... 502 3.1. Silicon ......................................................................................................................................................................... 502 3.2. Germanium .................................................................................................................................................................. 503 Galvanic displacement of metallic films on semiconductors ......................................................................................................... 503 4.1. General ........................................................................................................................................................................ 503 4.2. Displacement of noble metals ......................................................................................................................................... 505 4.3. Displacement of platinum group metals ........................................................................................................................... 507 4.4. Galvanic displacement from fluoride-free solutions ........................................................................................................... 508 4.4.1. Nickel on silicon .............................................................................................................................................. 508 4.4.2. Noble metals on germanium .............................................................................................................................. 508 4.5. Galvanic displacement on III–V semiconductors............................................................................................................... 508 4.6. Galvanic displacement on barrier layers ........................................................................................................................... 509 4.7. Semiconductor–metal interface ....................................................................................................................................... 510 Applications to microstructures and devices ............................................................................................................................... 511 5.1. General ........................................................................................................................................................................ 511

∗ Corresponding author. Tel.: +1 510 643 7957; fax: +1 510 642 4778.

E-mail address: [email protected] (R. Maboudian). c 2007 Elsevier B.V. All rights reserved. 0167-5729/$ - see front matter doi:10.1016/j.surfrep.2007.08.002

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5.2. Process requirements for free-standing microstructures...................................................................................................... 511 5.3. Copper forming by galvanic displacement on silicon microstructures .................................................................................. 512 5.4. Functionalization of galvanically deposited films and their work of adhesion ....................................................................... 512 5.5. Galvanic displacement on AFM microcantilevers.............................................................................................................. 513 5.6. Copper displacement for interconnects ............................................................................................................................ 514 Applications in nanoscale science and devices ............................................................................................................................ 515 6.1. General ........................................................................................................................................................................ 515 6.2. Nucleation of metallic clusters........................................................................................................................................ 515 6.3. Galvanic displacement from microemulsions.................................................................................................................... 517 6.4. Nanowire growth from metal catalysts deposited by galvanic displacement.......................................................................... 518 6.5. Complex nanostructures grown by galvanic displacement processes.................................................................................... 521 Conclusions............................................................................................................................................................................ 523 Acknowledgments................................................................................................................................................................... 523 References ............................................................................................................................................................................. 523

1. Introduction and roadmap The integration of metals with semiconductors has played a crucial role in shaping modern integrated circuit (IC) technology. Electrochemical processes are at the core of several important steps in semiconductor manufacturing. Among these, the damascene electrolytic process, which has allowed the replacement of the Al-based interconnect technology with one based on Cu, may be the most widely known example. However, other technologies are being developed and hold promise to deliver significant advances, especially in regard to the integration of nanoscale processes and devices. One such technology, the deposition of metals on semiconductors by galvanic displacement, has received intense renewed attention from the research community in the past decade, and is the subject of this review. In the galvanic displacement process, reduction of metal ions in solution is effected by the substrate itself upon immersion in the plating bath, without external power sources and without the need of a reducing agent in the bath. It is a versatile process, well suited to yield films with high purity and substrate adhesion, and with complete substrate selectivity. The main thrust of the present work is to review the applications of galvanic displacement on semiconductors to micro- and nanostructures, and to nanoscale processes. Less emphasis is placed on the fundamental chemistry underlying the mechanism of galvanic displacement on semiconductor substrates, since this is intimately related to their surface electrochemistry, for which excellent reviews already exist [1–9]. As such, we shall not attempt to write a comprehensive review of the displacement mechanism, but we shall cover those aspects that are essential for understanding its main thrust, with particular emphasis on the properties of the metal–semiconductor interface created by the immersion plating process. This review is organized as follows. After establishing the unique identity of galvanic displacement among electrochemical processes in general, and electroless processes in particular, we illustrate the process by means of a few well-studied applications involving displacement on metallic substrates (Section 2). The relevant aspects of Si and Ge electrochemistry are introduced in Section 3. The metallization of Si and Ge by galvanic displacement is discussed in Section 4, where the cases

of noble metals and platinum group metals are treated separately. Galvanic displacement on III–V compound semiconductor substrates and on barrier layers is also reviewed. Of particular interest throughout are those studies that address the chemical and mechanical nature of the metal–semiconductor interface obtained by galvanic displacement. Applications of galvanic displacement processes to microdevices are reviewed in Section 5. Intense research efforts are currently devoted to understanding the properties of nanostructures grown by galvanic displacement on various semiconducting substrates. Section 6 presents a review of this rapidly evolving field. 2. Electrolytic and electroless plating The galvanic displacement plating process is sometimes generally, but not satisfactorily, defined as the deposition of a metallic coating on a substrate from a solution that contains the ions of the coating material. This definition of the displacement mechanism is misleading because it can be applied to most of the plating processes from aqueous phase. Also the expression, plating, denoting a general application of a metallic coating, is commonly used to indicate the deposition of metallic films through electrochemical processes. Even if they are commonly grouped together under electrochemical methods or electrodeposition processes, distinctions between electrolytic and electroless deposition processes must be made, as is done below and illustrated in Fig. 1 [10–13]. 2.1. Electrodeposition An electrolytic process is the modification of a substrate surface in an aqueous or non-aqueous electrolytic environment by the application of an external voltage or current flow between two electrodes, one of these consisting of the base material. An electrolytic process may be the deposition of a metallic coating; in this case, the deposition rate, the limiting film thickness and its uniformity, and film properties depend on both the electrolyte formulation and the applied voltage and current. Electrolytic processes are referred to as electrochemical deposition methods due to the charge exchange that occurs at the interface between the solid and the liquid phases.

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Fig. 1. Cell set up for (left) electrolytic deposition process with external power source; (right) electroless deposition with reducing agent R as the source of electrons.

2.2. Autocatalytic deposition Electroless plating processes are defined as the deposition of a metallic coating on a substrate without the use of an external voltage or current. They are commonly referred to as chemical rather than electrochemical methods in order to emphasize the absence of an external power supply, even if their mechanisms can be explained by taking account of their electrochemical redox potential. Among the electroless plating processes, a distinction can be made between autocatalytic and galvanic displacement methods. The autocatalytic method is an electroless process in which the reduction of the metallic ions in solution and film deposition can be carried out through the oxidation of a chemical compound present in the solution itself, i.e., of a reducing agent. This reducing agent, under a defined temperature which depends on the reducing agent itself and on the bath’s composition, spontaneously oxidizes, freeing electrons for the reduction of the metallic ions. It is properly named autocatalytic, because the oxidation of the reducing agent can start or become self-sustained only at the depositing metal surface. This is the reason why for some non-catalytic base materials, the activation of the deposition with catalytic metals such as palladium is required [10–12]. Examples of an autocatalytic process are the well known electroless nickel deposition from hypophosphite based solution (used in electronics as a barrier layer in soldering and in surface engineering applications as a corrosion resistant coating) or the electroless copper process for the deposition of the first thick conductive layer for copper interconnects in integrated circuits [10]. In comparison to electrodeposition, autocatalytic deposition avoids current distribution, improves thickness uniformity and allows film deposition with a thickness that mainly depends on the deposition time. Complexing agents and stabilizers can be added to the solution in order to avoid the reduction and precipitation of metallic powders in the bulk solution. 2.3. Galvanic displacement Galvanic displacement or immersion plating (sometimes also called cementation) on a substrate takes place when the

base material is displaced by a metallic ion in solution that has a lower oxidation potential than the displaced metal ion [14–25]. The base material is dissolved into the solution; meanwhile the metallic ions in the solution are reduced on the surface of the base material. Such a mechanism differs completely from autocatalytic deposition because, in immersion plating, reducing agents are not required to reduce the metal ions to metal, as the base material behaves as the reducing agent. Perhaps the most commonly discussed example of immersion plating is the deposition of copper onto steel in a copper sulfate acid solution through the following reaction: Fe + Cu+2 → Cu + Fe+2 .

(1)

Paradoxically, this process is discussed as an example of a reaction that must be avoided in copper electroplating from an acid electrolyte onto steel during the dipping of the substrate into the solution. The reason is that the deposited copper layers display poor adhesion to the metal layers subsequently electrodeposited. Usually, copper electroplating onto steel is carried out in an alkaline copper cyanide based electrolyte, whereby cementation can be avoided. Regardless, galvanic displacement deposition processes are widely used, since they yield high value finishes on a variety of metals. The following characteristics of the galvanic displacement process can be pointed out: • The thickness of the deposited film obtained by immersion plating is limited (typically, in the range of hundreds of nanometers), because the deposition stops when the entire surface of the base metal is coated. As a consequence of such complete coverage and dense morphology of the film, the source of reducing agent is hindered. • Reaction rates increase with increased temperature. • Stirring is sometimes beneficial to the characteristics of the coating, by improving uniformity and reducing surface roughness. • Immersion reaction rates are not easily controllable, due to the fast exchange of charges between oxidizing and reducing species. Due to the nature of the displacement process, the deposition occurs by downward growth. The surface of the coating reproduces almost exactly that of the base

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Fig. 2. Comparison of energy level distribution and charge exchange under equilibrium conditions between a semiconductor surface and a redox electrolyte system with unnoble (left) and noble (right) normal potential (D stands for density of states.)

material, both in contour and in location, avoiding current distributions issues and the absence of electrical connections among areas of the substrate. Immersion plating is a part of many finishing processes, ranging from decorative or functional coatings to integrated circuit soldering. Zinc immersion plating on aluminium from alkaline zincate solution is fundamental for subsequent decorative plating or hard chromium electroplating [10]. Zinc cementation is required to reduce the activity of the aluminium surface, as a sort of sacrificial layer, which is partially dissolved during the immersion in acidic hexavalent chromium based electrolytes. Many decorative films of the noble or platinum group metals on copper and copper alloys can be deposited through immersion plating, producing adherent, wear resistant and tarnish-free coatings. Immersion gold is used in integrated circuits where soldering is required. The so-called ENIG process, Electroless Nickel Immersion Gold, allows the formation of soldered joints between components with high strength, reliability and conductivity [26,27]. A layer of nickel, about 5 µm thick, is deposited autocatalytically on top of the copper pads, in order to have a barrier layer between the copper and the tin-based solder alloys. A layer of gold, in the 0.1–0.2 µm range, is deposited by immersion plating onto the nickel layer to protect the barrier layer from corrosion and oxidation during storage prior to soldering. The thin gold film is dissolved rapidly into the solder alloy during the subsequent heating cycle. Immersion gold on autocatalytic nickel is commonly carried out from acid cyanide solution in the temperature range of 95–98 ◦ C. Immersion plating allows deposition on difficult surfaces, such as the inside of vias, and on surfaces that are not in the line of sight, or in cases where it is difficult to make electrical connections to isolated areas of the base material. This basis has been used for years for obtaining solder finishes with the highest reliability.

3. Electrochemistry of semiconductors 3.1. Silicon Numerous electrochemical investigations have been dedicated to silicon, particularly to the problems of anodic oxidation, electro-polishing, chemical etching and corrosion under galvanic coupling [28–54]. The electronic properties of silicon are essential in the understanding of silicon as an electrode material in an electrochemical cell. Silicon immersed in an electrolyte behaves as a Schottky diode, a metal–semiconductor contact with the formation of a space charge region if biased or due to surface states [55–60]. Fig. 2 shows the example of a semiconductor in contact with a relatively unnoble redox electrolyte, in which the electron exchange is dominant in the conductance band. In the presence of a relatively noble redox electrolyte, the electron exchange predominates in the valence band. When surface states exist in the region of the semiconductor gap, an additional electron exchange can occur with these energy levels. Silicon has a standard reduction or redox potential of −0.857 V with respect to the standard hydrogen electrode (SHE). Since galvanic displacement on Si is typically carried out in fluoride containing baths, it is useful to examine the potential/pH diagram, also known as the Pourbaix diagram, for the Si–F–H2 O system. The diagram, depicted in Fig. 3, maps out the various equilibrium phases for two different fluoride concentrations. The stable region of silicon is shown to lie below the line of equilibrium conditions for the reduction of water to hydrogen, indicating that silicon is not thermodynamically stable in water and aqueous solutions and readily oxidizes [60]. From the Pourbaix diagrams and considering the effects of pH and fluoride content on silicon stability, electrolytes commonly used for the electrochemical processing of silicon can be selected according to their constituents or their pH. At low pH, silicon can be considered as quite inert due to

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ranging from 4 to 8, the chemical mechanism requires water molecules and starts with the hydrolysis of the Si–H surface bonds at a kink site, as the rate limiting step. The Si–F bond formation that follows weakens the Si–Si back bond, leading to Si dissolution. At pH 4, the effect of undissociated HF must be considered. For lower pH, practically no chemical reactions take place. Under anodic bias and for pH > 4 (Fig. 4(b)), the electrochemical reaction takes place due to the dissociation of the Si–H bond by thermal activation of the electrons in the Si–H bond. Fluoride ions are not direct reactants, but they contribute to the activation of the dissolution reaction. Following a two-step process, an Si–F bond is formed, after which the mechanism proceeds chemically, involving molecular water. At lower pH, anodic reactions do not involve fluoride species due to the fact that F− ions are almost absent in solution. The electrochemical mechanism at OCP for pH > 4 (Fig. 4(c)) involves the dissolution reaction of the Si–H bonds, which becomes reversible. The negatively charged Si(−) surface groups react then with molecular water. The observed variations in the etch rate with the pH at the test potential can be explained through the change in the degree of stability of the Si–H bond – namely, the lower the pH, the lower its tendency to dissociate. 3.2. Germanium

Fig. 3. Potential–pH diagrams for the Si–F–H2 O system at 25 ◦ C [60]. In (a) Si = {10−3 }, F = {1}, and in (b) {Si} = {10−3 }, F = {10−3 }. Reprinted with permission from Ref. [60]. c 2005, IEEE.

the formation of a passive layer of oxide. This oxide film can be dissolved in hydrofluoric acid (HF) solution, while the dissolution rate of bulk Si in HF at open circuit potential (OCP) is negligible. In pure water, silicon tends to be oxidized with formation of hydrogen, silicon hydride, silica and silicates. In presence of fluoride ions, the formation of soluble silicon hexafluoride, SiF2− 6 , particularly in acid solution, takes place. Following etching in fluoride-containing solutions, silicon surfaces are characterized by unique electronic passivation properties, showing the lowest surface recombination velocities, which is attributed to the establishment of a complete Si–H termination [55]. It is also observed that their surface structure is greatly influenced by the pH of the HF or NH4 F solutions, affecting the formation of –SiH2 and –SiH3 groups onto the surface. Ideal flat H-terminated Si(111) surfaces can be obtained by increasing the pH to 8, with buffered ammonium fluoride solutions [61–63], because the reaction follows a chemical rather than an electrochemical mechanism [55]. The dissolution of silicon in fluoride-containing solutions has been the subject of intense research for the past several decades, and can be explained as comprising a chemical and an electrochemical component. As proposed by Allongue et al. [62,63] and illustrated in Fig. 4(a), for solutions with pH

The electrochemistry and wet etching of Ge have been extensively studied [55–58,64,65]. Some mixtures that are frequently used for the wet etching of Ge are mentioned here. The corrosion of germanium in aqueous solutions without oxidants occurs by the formation of soluble GeO with simultaneous hydrogen evolution according to the following reaction: Ge + H2 O = GeO + H2 .

(2)

Germanium resembles the III–V semiconductors with respect to its unstable oxide, which dissolves in water unlike silica. In contrast to silicon, germanium undergoes anodic dissolution in a variety of acidic media, including H2 SO4 , HCl and HClO4 [55]. A wide variety of etching compositions exists that contain HNO3 and HF as basic ingredients, with HNO3 being a strong oxidizing agent and HF being a strong complexing chemical. The behaviour of the etching solution can be related to its composition with the etch rate characterized by an induction period due to the fact that not HNO3 , but a decomposition product such as NO is the actual etching agent. H2 O2 can replace the nitric acid as the oxidizer and these mixtures lead to more controllable behaviour, due to the absence of any induction period. The etch rate is sensitive to the crystallographic orientation in all cases, as is with silicon. 4. Galvanic displacement of metallic films on semiconductors 4.1. General Galvanic displacement on Si from solutions containing HF is a redox reaction in which both anodic and cathodic

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(a) Chemical reaction.

(b) Anodic reaction.

(c) Electrochemical reaction at OCP. Fig. 4. Structural 2-D model proposed for the dissolution of n-type Si in NH4 F solutions of pH 4–8. (a) Chemical reaction; (b) Electrochemical anodic dissolution without illumination (B is an empty surface state); (c) Electrochemical dissolution at open circuit potential (B 0 is state B filled with one supplementary electron). Reprinted with permission from Ref. [162]. c 1995, Elsevier.

− 0 − SiF2− 6 (aq) + 4e = Si (s) + 6F (aq)

E 0 (Si4+ /Si0 ) = −1.20VSHE .

Fig. 5. Mechanism of galvanic displacement of metals on silicon.

processes occur simultaneously at the Si surface while the charge may be exchanged through the substrate, as represented in Fig. 5 [66–71]. Fluoride ions in solution help sustain the reaction by dissolving the silicon substrate as silicon hexafluoride, avoiding the formation of silicon oxide, thus exposing new silicon surface. As commonly reported, the global chemical reaction of the redox couple is: Mn+ (aq) + Si0 (s) + 6F− (aq) = M0 (s) + SiF2− 6 (aq),

(3)

where aq and s indicate the aqueous and solid phases, respectively. Reaction (3) can be divided in two half-cell processes: Mn+ (aq) + ne− = M0 (s)

(4)

(5)

Silicon is dissolved in solution as silicon hexafluoride, while the metal is deposited from solution with a deposition rate related to the concentration of HF in the solution. Usually, the silicon surface shows an increase in surface roughness, particularly at the region close to the metal deposits, and sometime pitting is observed. The oxidation of silicon followed by the galvanic displacement of the metal ions in solution is believed to initiate at defects on the surface such as kinks, steps, contaminated sites, or areas chemically more reactive than H-terminated regions. As such, the deposition rates can be enhanced by increasing the density of surface defects, e.g., by Ar bombardment. Doping of the silicon substrate can affect the deposition mechanism, due to the transfer of the charged carriers through the substrate during displacement [72]. The standard redox potentials for metal reaction are reported in Table 1 [71]. Galvanic displacement is thermodynamically more favourable for metals with higher redox potential values, e.g., for gold or palladium than for copper or nickel. Considering that the redox potential for reaction (4) is much more negative than for hydrogen evolution (e.g., −0.48VSHE in 40% NH4 F and −0.12 V in 0.5% HF) and for noble and platinum group metals deposition, two cathodic reactions must be considered, namely, reaction (4) together with the following one: 2H+ + 2e− = H2 .

(6)

The efficiency of the metal deposition on the silicon surface is expected to vary according to the composition and the pH of the

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C. Carraro et al. / Surface Science Reports 62 (2007) 499–525 Table 1 Redox potentials for metals more noble than hydrogen (referred to the hydrogen standard electrode) Metal

Redox Potential (V vs. NHE)

Au Pt Ir Pd Ru Ag Rh Cu Re Ni

Au+3 /Au Pt+2 /Pt Ir+4 /Ir Pd+2 /Pd Ru+2 /Ru Ag+ /Ag Rh+3 /Rh Cu+2 /Cu Re+3 /Re Ni+2 /Ni

1.42 1.2 0.926 0.83 0.8 0.779 0.76 0.340 0.3 −0.23

Fig. 6. Scanning electron micrograph of a Ge sample plated for 30 min in 1 mM Au bath.

solution. In addition, the presence of the first metallic nuclei on top of the silicon surface can modify the dissolution mechanism and catalytically enhance the evolution of hydrogen [66,73]. 4.2. Displacement of noble metals The reducing behaviour of elemental silicon toward noble metal ions in aqueous solutions containing fluoride ions has long been known [74–80]. These reactions are of interest in microelectronics technology, where fluoride solutions are used to wet etch the native oxide of silicon. Contamination by metallic ions can lead to undesirable deposition of noble metal impurities on the Si surface, compromising the performance of electronic devices [81–83]. The deposition of metal films from fluoride-containing solutions both on silicon (Cu, Au) and germanium (Au) was studied by Balashova et al. [84] and Krikshtopaitis et al. [85] about thirty years ago. A reduction in the metal precipitation rate was observed with time for both silicon and germanium. The evaluation of the germanium potential during deposition indicated that the reduction of gold ions took place predominantly by charge transfer through the valence zone of the electrode. Magagnin et al. studied Au films deposited on Si(111) and on Ge(111) surfaces by the galvanic displacement method in fluoride-containing solutions, as shown in Fig. 6 [86]. While the Au/Si interface formed in this process was found to be weak, the Au films adhered very strongly to the surface of Ge, even in the thick film regime. Adhesion of the gold films on germanium was related to the formation of a chemical bond between the Au and Ge atoms. This was confirmed from the valence band (VB) region of the X-ray photoelectron spectra obtained from germanium coated with gold. In particular, the spectrum showed a shift in the main peak towards higher binding energies as well as an increased density of states at binding energy BE = 0. The deconvolution of the valence band spectrum revealed a second peak at 3.7 eV binding energy after 5 s deposition. This binding energy is 0.5 eV higher than that of the 5d5/2 orbitals in the clean Au VB peak (the VB of clean gold has peaks at 3.2 and 6.1 eV binding energies), see Fig. 7. Such a shift was attributed to the interaction of the metal with the germanium substrate, with the formation of a stoichiometric compound at room temperature, such as in the case of palladium and platinum on silicon and germanium [86–88]. In contrast, no

Fig. 7. X-ray photoemission spectra of the valence band region of clean (a) and Au plated (5 s in 1 mM KAuCl4 bath) Ge. Thick solid line: data. Dashed line: fitted peak constrained to the Au 5d binding energy values. Dotted line: fitted peak at 3.7 eV BE. Thin solid line: residual. The new peak at 3.7 eV binding energy is attributed to the interaction of the Au 5d5/2 electrons with Ge 4(sp) orbitals.

perturbation of the core or valence band electronic structure was detected at the Si–Au interface. Silver galvanic displacement on silicon has been employed to achieve nanostructured films, such as nanopillars, for surface enhanced Raman scattering (SERS) analysis [89]. Galvanic displacement of silver can be carried out in silver nitrate and hydrofluoric acid solutions [89–91]. The displacement reaction is: Si (s) + 6F− (aq) + 4Ag+ (aq) = 4Ag(s) + SiF2− 6 (aq).

(7)

Considering the metal reduction reaction: Ag+ (aq) + e− = Ag(s)

E 0 = 0.8VSHE

(8)

The process is thermodynamically favourable, with a standard cell potential of 2 V. There are a large number of possible steps, and in principle any one of these could be rate determining: (i) diffusion of Ag+ to the silver surface; (ii) adsorption of Ag+ and charge transfer to yield silver on silver; (iii) F− diffusion, charge transfer and reaction at the Si surface to yield 2− 2− SiF2− 6 ; (iv) desorption of SiF6 ; and (v) diffusion of SiF6 away from surface. The overall growth rate was observed to be diffusion controlled by silver species [89]. Metallization plays a key role in the production process of integrated devices. Copper has been pursued as an alternative material to aluminium to address the need for metallic thin films

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Fig. 8. Copper film from ammonium fluoride (NH4 F 40%) 50% vol., copper sulfate (CuSO4 ·5H2 O) 0.01M, ascorbic acid (C6 H8 O6 ) 0.01M, sodium potassium tartrate (KNaC4 H4 O6 ·4H2 O) 0.005M, and methanol 30% vol. after 30 min deposition at room temperature on Si(100) [97].

with low resistivity and high electromigration resistance [92]. Several studies have been carried out on the galvanic deposition of copper from fluoride containing solutions, providing an attractive deposition method for copper interconnects or seed layers for subsequent metallization [93]. Galvanic displacement is also a promising avenue for the integration of metals in micromechanical devices, due to its conformal nature and high substrate selectivity [86]. In the case of copper, the displacement reaction involves reactions (6) and (7) together with the following one: Cu2+ + 2e− = Cu

E 0 = 0.340VSHE .

(9)

Typically, copper deposition has been carried out from a copper sulphate and hydrofluoric acid based solution [74–80,94,95]. A crucial issue in the aforementioned processes is the lack of adhesion between the copper and the Si substrate, which may severely constrain their application [96]. Magagnin et al. reported a new process for the galvanic deposition of copper films with high reflectivity and smoothness onto silicon from ammonium fluoride containing solutions [97]. The deposition

was carried out at room temperature in a solution consisting of ammonium fluoride (NH4 F 40%) 50% vol., copper sulphate (CuSO4 ·5H2 O) 0.01M, ascorbic acid (C6 H8 O6 ) 0.01M, sodium potassium tartrate (KNaC4 H4 O6 ·4H2 O) 0.005M, and methanol 30% vol. (percentages are referred to the final solution volume). The deposition was achieved on single crystalline Si(100) and Si(111), p- or n-type as well as on polycrystalline silicon substrates. The authors observed that the adhesion of the copper film to the substrate was strongly related to the presence of ascorbic acid in solution. The absence of the acid resulted in the formation of a copper film which failed the standard scotch tape test. The good adhesion of the metallic films to the substrate was attributed to the prevention of hydrogen evolution at the silicon–copper interface, due to the hydrogen scavenging action of the ascorbic acid [98]. The nucleation and growth followed a 3D island growth mechanism with nucleation of metal clusters and subsequent growth of a film. The initial displacement was characterized by an extremely fast nucleation with a large number of nuclei. The 3D structure was found to be permeable to fluoride ions, resulting in long plating times and thick deposits. Fig. 8 is a cross-sectional scanning electron microscopy (SEM) image of a copper film deposited by displacement on silicon (100) after 30 min of immersion, corresponding to a thickness of 75 nm. The copper films deposited on p-type Si(100) was found to exhibit a strong preferential orientation along the (111) plane, the close-packed plane for the face centered cubic structure, and a weak peak corresponding to the (100) plane, most likely related to the influence of the substrate. Regarding adhesion, peeling of the deposited copper film was never observed, independently of the substrates (i.e., p- or n-type, single- or poly-crystalline silicon) and film thickness, demonstrating a high degree of adhesion to the substrate and resistance to scratching. As discussed extensively in Section 5.3, the coating process is suitable to plate free-standing polycrystalline silicon

Fig. 9. (a) SEM image of MEMS structures coated with copper by galvanic displacement [97]; (b) close-up SEM (light regions are polycrystalline silicon and darker regions are silicon nitride); (c) Cu EDS micrographs of the same region showing that only the polycrystalline silicon, and not silicon nitride, features are coated.

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micromachined devices. Fig. 9 shows a MEMS structure consisting of an interdigitated comb drive and a suspended shuttle, coated with a conformal metallic Cu film with thickness of about 25–30 nm. The selectivity of the deposition process is evidenced by the absence of copper on the silicon nitride mask. The galvanic displacement of copper on H-terminated Si(111) substrates has been studied also by Ye et al. [99]. After the immersion of the silicon substrate in the HF solution containing Cu+2 , the amount of SiH species decreased, while those of the SiH2 and SiH3 species largely increased, a behaviour that was attributed to the increased density of steps and kinks. The amount of copper deposited was much less than that in the ammonium fluoride solution containing the same concentration of copper ions [99]. This was attributed to the competition between H2 evolution and Cu deposition, and the pH dependent anodic oxidation of Si and SiO2 . In another study, the effect of the micro-roughness and kinksite densities of Si(100) and Si(111) on copper deposition was investigated [100]. Under identical conditions, the copper deposition rate was an order of magnitude lower on flat monohydride terminated Si(100) than on microscopically rough H-terminated Si(100) surfaces. In deionized water without fluoride but containing copper ions, the difference in the densities of dihydride sites on Si(111) and Si(100) was suggested to be the cause of the difference in copper coverage during metal reduction [100]. Zhong et al. studied the behavior of Cu immersion deposition on a Cu substrate in a CuSO4 –HF solution using a Si wafer as anode. The results showed that the weight of Cu substrate increased with bath temperature and plating time before reaching a constant value. The weight gain of the Cu substrate decreased with the distance between the two electrodes. The relationships of the plating time and the weight gain of the Cu substrate revealed that Cu film coated on the Si wafer may prevent electron diffusion to the cathode [101]. Scheck et al. reported on the photoinduced electrochemical deposition of Cu structures on p-type Si substrates by local illumination with a focused laser beam in an ammonium fluoride solution similar to that employed by Magagnin et al. [97]. The lateral dimensions of the structures formed were found to decrease with reduced laser wavelengths or intensities but were independent of the duration of the illumination. The effect of spontaneous background precipitation on the Si surface was studied as a function of the solution composition [102,103]. In the presence of additives such as ascorbic acid, but in the absence of NH4 F, they observed Cu background plating as Cu oxide, while with the NH4 F present in the solution, the background plated Cu was in the metallic state. 4.3. Displacement of platinum group metals Several properties shared among the platinum group metals (and some of their oxides as well) make them attractive for technological and commercial applications. These include their exceptional catalytic activity, their high resistance to

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wear, tarnish and chemical attack, and their stability at high temperatures. A glance at Table 1 shows that these metals are suitable for the immersion plating of semiconductors, and indeed, the galvanic displacement of Pt and Pd on Si and Ge has been observed [73,91,104–106]. In the case of Ge, deposition occurs even in the absence of fluorides or complexing agents [105], due to the solubility of GeO in aqueous environments. The best studied case is the displacement of Pt on Si, using either Pt(II) or Pt(IV) salts. Gorostiza et al. investigated the early stages of Pt(IV) galvanic displacement on Si(100) from HF solutions. Nucleation of polycrystalline platinum silicides was observed, along with the etching of the substrate surface. Etching was more substantial for p-doped than for n-doped samples; higher etching was observed to correlate with higher amounts of deposited Pt. A subsequent study aimed to clarify the reaction mechanism of Pt(II) on Si in the presence of fluorides [73]. The authors used a carefully electropolished silicon sample to minimize the density of surface defects. They exposed the polished side to a solution containing fluoride ions and PtCl2− ions under OCP conditions, and observed two reactions occurring simultaneously on the Si electrode surface. In the cathodic half cell reaction, Pt2+ ions were reduced to metallic Pt, while holes were injected into the Si valence band. In the anodic half cell reaction, silicon oxidation was promoted by the capture of the injected holes by Si atoms in the space charge layer near the sample surface, and the resulting silicon oxide was removed by the fluoride species. Because the holes can travel between injection and capture, cathodic and anodic reactions may occur at different regions of the surface. Hence, the formation of metallic nuclei and etch pits can be observed in different locations of the Si electrode surface. The extent of this etching is such that it leads to the formation of porous Si, accompanied most likely by the incorporation of hydrogen in the electrode. Galvanic displacement of palladium films on silicon has received less attention compared to platinum. Most studies employ the displacement of palladium nuclei for subsequent electroless metallization. Karmalkar et al. reported on the palladium activation of silicon surfaces achieved using a solution of PdCl2 and NH4 F in dilute HF. Palladium activation occurred by a displacement plating reaction, which requires a supply of holes; the authors found that the process was most effective on p+ substrates and least effective on n+ substrates. The activation layer showed poor adhesion to the substrate, even though a silicide layer was readily formed. This characteristic may make this process preferable over other activation methods in applications where a Schottky-type contact is required [108]. Ye et al. proposed the deposition of high-purity Pd films on silicon and germanium surfaces using the supercritical fluid immersion deposition procedure. The deposition reactions involved a precursor, HF, and a substrate (silicon or germanium). The reducing agent was the substrate (Si or Ge) itself, and metal films were formed only on the substrate surfaces. This new metal film deposition process did not require hydrogen gas and high temperature, and HF was introduced by

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a HF-carrier. The palladium films were shown to be converted to palladium silicide by annealing [106,107]. 4.4. Galvanic displacement from fluoride-free solutions 4.4.1. Nickel on silicon Nickel is an attractive metal due to its magnetic properties, which are useful in a wide spectrum of applications including magnetic recording media and magnetic actuators. The fabrication of arrays of magnetic nanodots using metals such as Ni, Co, and Fe is expected to contribute to the realization of ultrahigh-density ROM and RAM devices. It is also known that these metals can be converted to silicides by subsequent heat treatment. The deposition of Ni on silicon by simple immersion plating is a challenging subject from both basic and practical points of view, due to its negative redox potential (see Table 1) [109,110]. Takano et al. [111] and Niwa et al. [112,113] developed an electroless deposition process in aqueous alkaline solutions for Ni plating on Si surfaces. It was found that Ni could be deposited on a Si(100) wafer immersed in a pH-adjusted alkaline NiSO4 solution containing no reductants such as sodium hypophosphite. This process was applied for the selective Ni deposition on patterned Si substrates. This was followed by immersion in a hypophosphite-based bath for further growth by autocatalytic deposition. The authors proposed that the nucleation step proceeded by a galvanic displacement reaction in which Si was oxidized and Ni ions in solution were reduced to Ni nuclei, with the process taking place in an alkaline electrolyte without fluoride. In this regard, it must be noted that Si is normally etched in alkaline solutions, whereas the high pH inhibits hydrogen evolution, a process which would otherwise be more favourable than Ni2+ reduction based on the standard potential table. Gorostiza et al. studied the open-circuit potential deposition of nickel on silicon from fluoride solutions at pH 1.2, where nickel ions are unable to exchange charge with the silicon substrate, and at pH 8.0, where nickel ions in solution can exchange electrons with both the conduction band and the valence band of the silicon substrate. In high pH, deposition of nickel took place due to the coupling between the anodic dissolution of silicon in fluoride media and two competing cathodic reactions, namely, hydrogen evolution and nickel deposition [114]. 4.4.2. Noble metals on germanium Galvanic displacement of metal ions from hydrofluoric acid solutions onto semiconductors initially posed a formidable barrier to electronics fabrication. Recent studies have proposed the galvanic displacement process as a metallization method is competitive with state of the art physical and electrochemical deposition methods. While the majority of the studies has been carried out on Si due to its technological dominance, galvanic displacements on Ge surfaces have also been examined. Although most deposition bath solutions contain hydrofluoric acid as a component, noble metal deposition on germanium has been demonstrated in the absence of HF. The use of HF is not

necessary, due to the fact that germanium oxide is soluble in water, in contrast to silicon oxide. Likewise, the addition of pH adjusters, complexing agents, or any other additives is found not to be necessary. Electroless deposition of noble metal films on germanium substrates is accomplished via immersion of the native oxide-capped wafer into aqueous solutions of AuCl− 4, 2− 2− PdCl4 , or PtCl4 . The proposed process is able to provide control over the surface morphology and deposition rate by careful modulation of such plating parameters as metal ion concentration, temperature, and immersion time [105,115,116]. 4.5. Galvanic displacement on III–V semiconductors Compared to Si and Ge, relatively few studies have dealt with galvanic displacement on III–V semiconductor substrates. To assess the possibility and reaction mechanisms of immersion plating on these substrates, the etching behavior of the group III–V compound must be carefully considered, taking into account that the two components have different corrosion reactivities, and that the number of possible corrosion reactions is very large [117]. Potential–pH Pourbaix diagrams are helpful, although they are themselves quite complex. The Pourbaix diagram of GaAs in water, as shown in Fig. 10, well illustrates the point when compared to the much simpler diagram for Si in water and fluoride shown in Fig. 3. D’Asaro et al. have observed the nucleation of metallic Pd on GaAs immersed in aqueous solutions of PdCl2 in the presence of HCl, which solubilizes the salt by complexing it to PdCl2− 4 , HF and acetic acid. [66] Based on the Pourbaix diagram, they propose that displacement may occur via the following reactions: − − PdCl2− 4 (aq) + 2e = Pd(s) + 4Cl

E 0 = 0.62VSHE Ga3+ (aq) + 3e− = Ga E 0 = −0.54VSHE HAsO2 + 3H+ + 3e− = As(s) + 2H2 O E 0 = 0.25VSHE H3 AsO4 + 5H+ + 5e− = As(s) + 4H2 O E 0 = 0.38 VSHE .

(10)

(11)

(12)

(13)

with the last three proceeding from right to left. Hence, the electrons necessary to reduce the Pd ions can be supplied by either Ga or As atoms on the substrate. It should be noted that galvanic displacement on GaAs does not require the presence of HF in the plating bath, even though it is present in the aforementioned case. Fluorides are required neither by the reaction mechanism nor to dissolve the substrate oxides. The oxides of GaAs are soluble in HCl, and indeed, the earliest work on GaAs metallization by galvanic displacement used a plating bath comprised only of an aqueous solution of tetrachloroauric acid (Ref. [118], more readily accessible in the West through the account provided in Ref. [119]). With the same bath, Donzelli et al. were able

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Fig. 10. Potential–pH diagrams for the GaAs–H2 O system at 24 ◦ C. Reprinted with permission from Ref. [117]. c 1979, Elsevier.

to deposit selectively Au films on photoresist-patterned GaAs and to characterize the resulting Shottcky diodes, and in this manner the obtained information about the dissolution rate of the substrate during plating (e.g., 1.3 nm/s in a 2 g/l aqueous solution of tetrachloroauric acid at 24 ◦ C). Since this early work, galvanic displacement has been employed to deposit Au, Pd, Pt and Ru on various III–V substrates, including GaAs, Alx Ga1−x As, GaP, and InP [66,120,121]. 4.6. Galvanic displacement on barrier layers Although not semiconducting, barrier layers play an important role in semiconductor technology and in device electroplating applications. Thus, it is not surprising that galvanic displacement processes on barrier layers have been the focus of some research efforts, and it seems fitting to review briefly the subject at this point. The main function of the diffusion barrier is to prevent interdiffusion and to improve the adhesion between layers. Nitride barrier materials, such as TiN and TaN, but also pure Ta, are used to avoid the thermal diffusion of Cu into dielectric SiO2 in microelectronic devices. TiN has been used as a barrier material because of its high rigidity, the high melting point of ∼2930 ◦ C, its good thermal and electrical conductivity, high thermal stability, and ease of manufacturing. The properties of TaN approach those of TiN. Usually, copper interconnects are electrochemically deposited on top of a thin copper layer, which is deposited by the vapour phase deposition method on the barrier layer. In order to avoid the vapour phase step, a thin metallic layer may be deposited through a galvanic displacement process [122–124]. The displacement reaction between the nitride barrier layer/Si substrate and metal ions has been reported. Dubin et al. reported that Cu deposition occurs as a result of the displacement reaction with the TiN/Si [125]. Fung et al. also reported such deposition due to the displacement reaction between Cu+2 and the underlying Si with cracks in the intermediate TiN film [126]. Unpublished results from our

Fig. 11. Copper film deposited on TiN/Si(100) substrate from ammonium fluoride (NH4 F 40%) 50% vol., copper sulfate (CuSO4 ·5H2 O) 0.01M, ascorbic acid (C6 H8 O6 ) 0.01M, sodium potassium tartrate (KNaC4 H4 O6 ·4H2 O) 0.005M, and methanol 30% vol., after 60 min deposition at room temperature.

group about copper displacement from an ammonium fluoride and copper ions solution confirm the possibility of metal deposition as a consequence of solution interaction with the silicon underneath, leading to a three dimensional growth of the Cu film with poor adhesion, as shown in Fig. 11. O’Kelly proposed that a Cu layer could be obtained after a pretreatment of TiN surface with Pd, which had been deposited via a displacement reaction [127]. Wu et al. proposed a displacement reaction of TiN according to the following overall mechanism 2− − 4TiN + 12HF− 2 → 4TiF6 + 4NH3 + 4e

(14)

with simultaneous palladium ions reduction and deposition, and hydrogen evolution [128]. Cesiulis et al. proposed a similar mechanism for silver displacement on TiN from silver nitrate baths [129]: TiN + 4Ag+ + 6F− → 4Ag + TiF2− 6 + 1/2N2 .

(15)

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Wang et al. demonstrated that continuous Cu films can be deposited on Ta by a two-step process, namely the galvanic displacement of Ta by Cu from ammonium fluoride solutions and subsequent electroless Cu deposition from a formaldehydecontaining bath [130]. 4.7. Semiconductor–metal interface Deposition of metals on semiconductors is an important and ubiquitous process in the electronic industry. When deposited by electrochemical methods, metallic films tend to grow by a three-dimensional island growth mechanism. On semiconductor surfaces, the process involves conduction and valence bands and surface states. Lower surface electron density and lower rate of charge transfer in semiconductors relative to metals often entail problems in obtaining good film structure and substrate adhesion. Good adhesion is a necessary requirement for good thermal and electrical contacts. The nature of chemical bonding in metals is quite different from the strong covalent bonding prevalent in semiconductors, and hence, it is often difficult to obtain a robust semiconductormetal interface. Indeed, regardless of the deposition method used, the adhesion of metallic films to semiconductors is usually poor, especially for noble metals. Thus, the expensive extra processing steps of interposing adhesion or seed layers in high vacuums are often required. There are multiple factors influencing the adhesion of the deposited film to the substrate. Properties such as the density of nucleation sites, chemical bonding between film and substrate (including, e.g., the existence of stable “intermetallics”), presence of an intervening layer (e.g., oxide layer), gas evolution during deposition (leading to formation of voids), and film morphology (including density and grain structure of the deposit) can all affect the mechanical (and electrical) quality of the interface. As a specific example, consider a gold film on the silicon surface. Based on the rather general argument of incompatibility between the metallic bonding in the film and the covalent bonding in the substrate, poor interfacial adhesion is expected, and is indeed found experimentally [86]. This entails poor mechanical and electrical properties. Thermal treatment is found to sometimes improve the quality of the interface, perhaps by promoting the intermixing with the formation of silicides. But Si and Au do not form stable or even metastable bulk silicides at any temperature, and hence, thermal treatment only speeds up the dewetting of the Au film on the Si surface. Poor adhesion is accompanied by the enhanced oxidation of the Au–Si interface. Ferralis et al. have used ultrahigh vacuum techniques of low energy electron diffraction and Auger electron spectroscopy to study this interface for Au deposited by galvanic displacement [131]. Thermal annealing is found to remove the interfacial oxides and produce films indistinguishable from those evaporated in situ. Furthermore, annealing is shown to produce a stable monolayer of silicide. However, unlike the case of the Au–Ge interface discussed in Section 4.2, this silicide layer does not promote film adhesion.

This is most likely due to the fact that Au (or, during annealing, the Au–Si eutectic alloy) does not wet the silicide monolayer. Quantitative methods for evaluating the strength of the metal–semiconductor interface have been developed to improve upon the quick and commonly employed, but qualitative, ScotchTM tape test. One difficulty encountered in measuring adhesion of immersion plated films is that the metals are generally softer than the substrate. (This is certainly the case for noble metals, although it need not be for Pt-group metals). Magagnin et al. [132] demonstrated the use of microhardness measurements in conjunction with a composite hardness model [133], for the adhesion evaluation of soft films, such as noble metals, galvanically deposited on hard substrates such as Si or Ge. Qualitatively, stronger adhesion corresponds to higher composite Vickers microhardness and produces a more extended deformation zone at the film substrate interface [132, 133]. Quantitatively, one plots the difference between the hardness of the substrate and that of the (softer) substratefilm composite against the ratio of film thickness over the indentation diagonal. For soft films on hard substrates, one expects an approximately straight line [134], whose slope yields the desired quantitative measure of adhesion. In particular, the inverse slope is proportional to the so-called critical reduced depth (i.e., the ratio between the radius of the plastic zone beneath the indentation and the indentation depth), for which larger values denote better adhesion. (The linear relation breaks down at high loads or at very small indentation depths, where the measured hardness is dominated by pure substrate or pure film effects, respectively.) The results of our microhardness tests are shown in Fig. 12(a) for Au films deposited by displacement on Si and Ge. The much higher value of the critical reduced depth, b, obtained for Ge is consistent with the finding of a good chemical bonding at the Ge–Au interface, as discussed in Section 4.2. Fig. 12(b) shows the results of similar tests performed on immersion plated copper films deposited on Si(100) from fluoride containing solutions, with or without adhesion-promoting additives [132]. The highest indicator of adhesion of the metallic film to the substrate is obtained when ascorbic acid is added to the solution. As already discussed in Section 4.2, this additive prevents hydrogen evolution owing to its hydrogen scavenging action, which in turn is likely to produce a more compact Cu film and a void-free interface. Furthermore, the well known strong antioxidant properties of ascorbic acid may result in an interface of higher quality. Antioxidant action alone does not promote the best adhesion; however, as evidenced by the lower b value obtained with baths containing antioxidant sulphites as the only additive with respect to baths containing ascorbic acid. Other studies of the metal–semiconductor interface have generally reported results that are consistent with expectations based on considerations of compatibility between the chemical bonding model and of the equilibrium phase diagram of the system. D’Asaro et al. examined the displacement of Pd on a variety of substrates as a means of promoting adhesion of subsequent electroless Au [66]. They observed a high density

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Fig. 12. Hardness difference vs. ratio between the film thickness and the indentation diagonal for copper films from basic, sulphite and ascorbic solutions after plating for 30 min and gold films from 1 mM gold bath on Si(100). The critical reduced depth b for each system is reported in Ref. [132]. Reprinted with permission from Ref. [132]. c 2003, Elsevier.

of Pd nucleation sites on GaAs. The good adhesion of the electroless film to this substrate was attributed in part to the large number of anchoring points, and in part to the strong interaction between Pd and GaAs (contributing to make each anchor strong). In contrast, they pointed out how the much smaller density of nucleation sites obtained on Si, coupled with the much weaker interaction between the two mutually insoluble elements, produced poorly anchored films. Based on the argument of mutual solubility, they also ruled out good adhesion between Au and Si, while they pointed out that better adhesion may be expected for Au on GaAs. According to Donzelli et al., immersion plating Au on GaAs produces interfaces of high electrical quality, comparable to those formed with evaporated Al, although mechanically they are not stable enough to prevent liftoff by ultrasonication [119]. 5. Applications to microstructures and devices 5.1. General Processes that use copper metallization in the production of integrated circuits have been studied to achieve the deposition

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of conformal metallic thin films with low resistivity and high electromigration resistance [92]. Electrochemical processes at the core of these IC technologies have been extensively investigated. Electroforming offers unique properties, such as the excellent filling of high aspect ratio structures, low stress films, and low temperature and cost-effective processes [135]. Electroless forming is demonstrated to be an alternative deposition method to galvanic forming and to be compatible with silicon technology [136–138]. The forming of nickel by autocatalytic deposition onto high aspect ratio metallic structures has been proposed and studied as a function of the temperature, reaction kinetics and different geometric proportions of test structures. It is found that the formation of gas blankets attached to the walls locally hinders the deposition and hence, ultrasonic agitation is needed [136]. The metallization of silicon micromechanical structures and microelectromechanical systems (MEMS) remains a relatively unexplored subject [139–141]. Copper deposition by electrochemical contact displacement into microtrenches filled with amorphous silicon is investigated as an alternative to electroplating [142]. Electroless deposition of nickel and cobalt alloys is used for the selective metallization of the uppermost surface of silicon beams [141]. In this chapter, we review applications of galvanic displacement methods to coat and functionalize silicon MEMS devices as well as silicon AFM microcantilevers. Metallization of silicon micromechanical structures and devices entails design and processing issues beyond those of concern in IC technology. Mechanical functions are performed by micromechanical devices, thus subjecting the metal films to mechanical stresses, fatigue and wear. Technologies for metal integration in MEMS must consider that these devices are intrinsically non-planar. A high degree of conformality is therefore required. Galvanic displacement methods not only minimize the stress typically found in metal films formed on silicon by physical deposition methods, they also balance the forces by metal coverage on all sides of the free-standing silicon structures owing to their highly conformal nature. Furthermore, their deposition can be tuned to produce homogeneous, smooth and reflective coatings with good substrate adhesion. Lastly, metallic films provide a highly stable coupling layer for subsequent microstructure functionalization via self-assembly, for example, of thiol-based monolayers. Ordered and stable alkanethiol films form on gold as well as on copper and copper oxide [143–146], and are able to provide some protection against oxidation [147]. 5.2. Process requirements for free-standing microstructures There are several issues of concern in immersion plating of microstructures (such as MEMS), namely the uniformity and conformality of the coating process, the surface energy of the copper films, and the film–substrate adhesion. The last issue has been addressed elsewhere. To highlight the importance of the other issues, the deposition process may be evaluated in terms of diffusion to a plate underneath the floating structures. Let us consider a typical MEMS structure, such as a cantilever beam, suspended a distance h above the ground plane. A rectangular

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shape of sides a and b, with b < a, is assumed. (Practical values may be h ≈ 1 µm, b ≈ 5–20 µm, a ≈ 50–1000 µm.) The concentration, ρ, of the coating species in the liquid phase (i.e., the metal ion) is usually in the range 1–10 mM. Neglecting for the moment diffusion processes, to coat an area equal to 2ab, a number of molecules equal to Nc = ρabh is present in the volume of fluid trapped between the ground plane and the underside of the beam. If we consider the typical values of h and ρ, this translates into roughly 1014 –1015 mol/cm2 , i.e., a coating thickness of about one monolayer. Thus, the single most important limiting factor for coatings thicker than a monolayer is diffusion in the liquid phase. Let us now take diffusion into account. Simple dimensional analysis indicates that the number of atoms (per unit area) available to form a coating film must scale as N = ρh Dt/b2 , where D is the diffusion coefficient and t the coating time. With ρh a fraction of a monolayer, times of the order of an hour are required to achieve a coating thickness of a few tens of nanometers on the underside of a microstructure. These considerations have serious implications for the metallization of MEMS by immersion plating. 5.3. Copper forming by galvanic displacement on silicon microstructures Carraro et al. [148] showed that the introduction of suitable additives into the plating bath can overcome diffusion-related problems, thereby allowing the formation of very conformal copper coatings on silicon microdevices. Furthermore, they tailored the surface properties of the copper films with organic self assembled monolayer coatings in order to reduce adhesion of MEMS devices during operation. Microfabricated cantilever beam arrays were used to assess the extent to which the plating process was able to coat suspended high aspect ratio structures conformally. Galvanic deposition was carried out for 30 min. Optical observations after peeling the beams away with adhesive tape confirmed copper film forming both on top and underneath the beams, as well as on the ground plane. Fig. 13 (top) shows a SEM micrograph of the cross section of a beam after plating. Copper has coated the whole structure, forming an adherent and homogeneous film with a thickness in the range of 100 nm. The concentration line profiles reported in Fig. 13 (bottom) for copper and silicon confirm the copper deposition on the ground plane and the coating of the whole beam. The copper concentration line profile along the cross section shows three peaks in correspondence with the ground plane, the underside and the uppermost sides of the beam, respectively. Conformal copper coating was achieved if two ingredients were present in the plating bath. One is methanol, which promotes the wettability of the hydrophobic surface after release in HF and during plating in the presence of either HF or NH4 F. The presence of a surfactant with levelling action, such as PEG, permits the immersion plating for sufficiently long times without the onset of inhomogeneous or dendritic growth. The copper films deposited by displacement on silicon microstructures were also used as seed layer for subsequent ENIG metallization after selective palladium activation.

Fig. 13. (top) SEM micrograph of a polysilicon cantilever beam (shown schematically in the inset) following 30 min selective copper plating; (bottom) copper and silicon concentration line profiles along the line indicated in the above micrograph.

Electroless nickel was deposited for 30 min, corresponding to a thickness of a few micrometers. The autocatalytic deposition of nickel was conformal to the MEMS geometry. Hydrogen evolution was minimized to avoid bubble segregation or the breaking of the suspended silicon structures. The process was then followed by immersion gold plating for 15 min, leading to homogenous gold film of about 0.1–0.2 µm thickness onto the electroless nickel layer. The optical image in Fig. 14 shows a comb drive structure after ENIG deposition. Electroless forming can be considered a viable metallization process of silicon microdevices, particularly if it is coupled with galvanic displacement processes to form adherent and conformal seed layer films onto the silicon substrate. 5.4. Functionalization of galvanically deposited films and their work of adhesion Functionalization schemes are readily available for many of the noble metals listed in Table 1, and can be used to render the surfaces hydrophobic in order to avoid the microstructure adhesion caused by capillary forces. As an example, alkanethiol self assembled monolayer passivation has been applied to microfabricated polysilicon adhesion test structures following copper plating [148]. Hydrophobized copper plated structures possess extremely low adhesion since

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Fig. 14. Polycrystalline silicon comb drive after copper plating from ammonium fluoride solution [97] and ENIG metallization.

they are hydrophobic, very rough, and not susceptible to charge build-up. The apparent work of adhesion of the film is evaluated by testing the cantilever beam arrays (CBAs). Beams are actuated and then the actuation force is removed. Beams shorter than a characteristic length are sufficiently stiff to free themselves completely from the substrate. Beams longer than this characteristic length remain adhered to the surface. The detachment length, ld, is measured as the beam length at which the beams exhibit a transition from adhered to free standing. Adhesion of the beams to the substrate at the transition region is confined at their tips. The work of adhesion, W , between the two surfaces can be calculated by balancing the elastic energy stored within the beam and the beam-substrate interfacial energy. The following equation can be used [149]: W =

3 Eh 2 t 3 , 8 `4d

(16)

where E is Young’s modulus (170 GPa for polysilicon), h is the spacing between the beam and the substrate, and t is the thickness of the polysilicon beams. Eq. (16) is applicable for a homogeneous beam, and therefore it should be used if the thickness of the plated film is small compared to the thickness of the polysilicon beam, a condition that is met in the aforementioned experiments. Fig. 15 shows a picture of a typical CBA after copper plating (20 min) and dodecanethiol coating, as seen under differential contrast microscopy after several actuation cycles, and upon removal of the bias voltage. Adhesion to the substrate of the ninth beam from top is observed at a length of about 500 µm. All the other beams in the picture are free standing. An average detachment length of about 1100 µm, or a work of adhesion of about 3 µJm−2 , was obtained after measurements on several different arrays. For comparison, a detachment length of about 750 µm was obtained with the same test structures, following the state-of-the-art octadecyltrichlorosilane coating process [150]. Considering the similar chemical termination of the surfaces, the lower work of adhesion of the dodecanethiolcoated copper surfaces was attributed to the increased surface roughness. A study performed with a copper coated AFM tip confirms this interpretation (vide infra).

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Fig. 15. Differential interference contrast optical micrographs, after several actuation cycles, of a polycrystalline Si cantilever beam array that is copper plated and dodecanethiol coated. Brightness indicates downward curvature. The shortest beam (top) is 150 µm long, and the longest (bottom) is 900 µm. Reprinted with permission from Ref. [148]. c 2002, Elsevier.

5.5. Galvanic displacement on AFM microcantilevers The functionalization of scanning microprobes by selfassembled monolayers (SAMs) of alkanethiol compounds on gold-coated surfaces and of silanes on silicon is widely employed [151–159], and is useful to probe the effects of chemistry on the tribological properties of surfaces. Because thiol attachment chemistry is generally cleaner and easier to implement than silanization, the coating of cantilevers with a noble metal is a particularly useful process. Conventional vapour deposition techniques for metals are not conformal, require a high vacuum apparatus and the deposition of adhesion promoters such as chromium or seed layers. Furthermore, the thermal expansion mismatch between the metallic coating and the cantilever (which is usually made of silicon) may induce bending of the microprobes. A galvanic displacement technique was used by Fritz et al. to coat silicon scanning force microscopy cantilevers with a copper film [160]. The plating solution contained ascorbic acid, sodium potassium tartrate, methanol and ammonium fluoride, in addition to copper sulphate. An atomic force microscope was then used to perform adhesion measurements in a liquid environment, using copper-coated cantilevers, which were either cleaned and oxidized by a UV–ozone (UVO) treatment or coated with a dodecanethiol (DDT) SAM. The substrates were copper-coated single crystalline Si chips, which were also either treated by UVO or coated with a DDT monolayer. Force–distance curves were obtained in water, methanol and ethanol. The authors reported adhesion values of 0.33±0.10 nN in water, 0.023 ± 0.005 nN in methanol, and 0.008 ± 0.004 nN in ethanol between the UVO cleaned copper tip and sample. After coating the same sample and the tip with the thiol SAM, the adhesion forces became 1.34±0.66, 0.11±0.08 and 0.06± 0.02 nN in the three liquid media, respectively. The results were qualitatively consistent with the expectation of a lower adhesion force between hydrophilic surfaces than between hydrophobic (methyl-terminated SAMs) surfaces in water. Quantitatively, the observed ratio between the measured adhesion forces in water and ethanol for the hydrophobic interaction, equal to

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Fig. 16. (a) Scanning electron micrograph of a silicon scanning force microscopy cantilever. (b) Close-up of the tip after immersion plating in the aqueous copper solution for 3 min. Reprinted with permission from Ref. [160]. c 2004, Springer.

about 22, was noted to be in very good agreement with the expected value of about 25 [161,162]. Contact mechanics theory, in particular, the Johnson, Kendall and Roberts (JKR) approach [163], which is a good model for tip–copper contacts, was employed to derive the (combined) radius of curvature of the copper contacts. Note that this need not be the same as the radius of curvature of the tip, since the film possesses a nontrivial, possibly fractal, structure. JKR theory predicts a force F = −1.5π W R, with R being the radius and W the work of adhesion. Knowing the work of adhesion (88.4 mJ/m2 ) [162] and the adhesion force (1.34 nN) between methyl-terminated alkanethiol films in water, Fritz et al. estimated the radius of the contacting probe to be about 3 nm, which is far smaller than the radius of 200 nm obtained from scanning electron micrograph of the coated tip. This difference was attributed to the presence of a nanometer sized asperity on the otherwise broad tip (Fig. 16). 5.6. Copper displacement for interconnects Galvanic displacement of copper in fluoride solution was employed by Lee et al. to produce copper trenches on a tantalum barrier layer. An amorphous silicon layer was first deposited in the trenches, followed by chemical mechanical polishing to remove the Si from outside the trenches. The silicon remaining in the trenches was then displaced by copper. This selective copper metallization method was evaluated as promising for overcoming the obstacles in the current damascene process, such as the limitations due to high aspect ratio trenches for copper interconnects [142]. Copper trenches can be selectively plated through a galvanic displacement process by using a thermal oxide mask. A silicon ˚ thick wet thermal oxide on top and wafer with a 1000 A grooves cut into the sample with a diamond dicing saw was copper plated by galvanic displacement. The grooves were about 80 µm wide, spaced about 150 µm apart, and 20 µm deep. Thermal oxide masking was used as a template for the selective forming and gap-filling of copper. Galvanic displacement in an ammonium fluoride solution was carried out up to two hours without dissolving completely the oxide mask (the etching rate of wet thermal oxide in concentrated hydrofluoric acid is about 2 µm/min, and in diluted 10:1 hydrofluoric acid, it is about ˚ Fig. 17(a) and (b) show the side view of the sample 230 A/min).

˚ thick wet thermal oxide mask (a) before Fig. 17. Silicon wafer with a 1000 A copper plating and (b) after plating for two hours (side view); (c) top view of the sample in Fig. 17(b).

before and after 2 h of copper plating respectively. The filling of the grooves was better revealed by the top view of the sample in Fig. 17(c).

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6. Applications in nanoscale science and devices 6.1. General The properties of matter confined to zero dimensions, i.e., assembled into structures termed quite interchangeably as clusters, dots, nanoparticles, and nanograins, have been the subject of intense research efforts for three decades. Metals are particularly interesting for the unusual optical and chemical behavior they display in the form of nanoclusters. For instance, the high catalytic activity of gold clusters has been well documented, and is in stark contrast to the inertness of the bulk metal. Moreover, silver, gold, and to a lesser extent, most other metal clusters possess strong plasmon resonances that impart them with novel optical properties. These properties in turn allow the use of nanoclusters as optical reporters and enable a class of ultrasensitive spectroscopies for single molecule detection. In short, the synthesis of metallic clusters of high purity and with precise size and location control is an important subject in nanotechnology research. Galvanic displacement processes offer many attractive characteristics for nanocluster synthesis when the cluster is required to reside on a surface. Indeed, the metals thus deposited are of high purity, and there is no need for the complexing agents that are required to stabilize metallic clusters in colloidal solutions. The process is substrate selective, and this fact enables novel and powerful nanolithographic processes for the integration and localization of metallic [89,105] and semiconducting [164,165] nanostructures. In contrast, nanoclusters produced by reduction in solution to form colloidal suspensions are normally blanketdeposited without any intrinsic substrate selectivity. Although most of the work on galvanic displacement on semiconductor substrates deals with studying and improving properties of galvanically deposited thin films, deposition of clusters by this technique is gaining significant attention because of the marked advantages that it presents over alternative methods. Several important studies concern themselves with the shape and properties of nanoclusters obtained at short deposition times, i.e., at the initial stages of film nucleation; these studies are reviewed in the next section. We shall then review a specific technique, which employs galvanic displacement deposition from microemulsions [166], and is designed to produce clusters of controlled-size distribution and surface coverage. A separate section is devoted to the growth of semiconductor nanowires from catalyst seeds deposited by galvanic displacement. This technique is rapidly gaining favour, because it is an inexpensive and very clean way of depositing noble metal catalysts, selectively and with tight size control. It also holds the promise of enabling the heterogeneous integration of electronically relevant materials, since it applies to a variety of semiconductor substrates. Finally, we review the growth of more complex nanostructures. 6.2. Nucleation of metallic clusters Galvanic displacement processes have been used to create seed layers for the subsequent deposition of metallic films

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by an electroless reaction. These seed layers often consist of clusters of a catalyst metal such as Pd. Thus, the formation of nuclei during galvanic displacement has attracted attention in early studies of film deposition, because the nucleation process is crucial in determining the quality of the final metal film-substrate interface. D’Asaro et al. [66] studied the nucleation of Pd clusters on III–V semiconductors such as GaAs, Alx Ga1−x As, GaP, and InP, as well as on Si and Ge. The clusters form upon immersion of the substrate in an acidified solution of PdCl2 , whereby Pd2+ ions are reduced to metallic Pd by galvanic displacement at nucleation sites on the semiconductor substrate. Subsequent plating in an electroless gold bath containing a reducing agent, such as potassium borohydride, results in films that display excellent adhesion on the III–V substrates, but not on Si or Ge. Transmission electron microscopy has been employed to examine the interface between the Pd clusters and GaAs or Si substrates, revealing remarkably different morphologies and distributions of clusters for the two cases. On GaAs, a uniform and dense distribution of Pd nanoclusters is obtained, indicating that nucleation is highly favoured on this substrate. In contrast, nucleation occurs at a much smaller number of cathodic sites on Si substrate, followed by the growth of these few sparse nuclei into large spherical particles. Thus, nucleation occurs preferentially on the already existing palladium clusters rather than directly on the substrate, which signals a weak interaction between metal atoms and the semiconductor surface. The weakness of the interface between electroless Au film and Si (or Ge) is then attributed to the scarcity and weak bonding of the catalyst Pd nuclei on both substrates, whereas on III–V substrates, the nuclei provide a strong anchor for the electroless Au film. The formation of Au nuclei during the initial stages of thin film deposition on both Si(111) and Ge(111) has been characterized by Magagnin et al. [86] using atomic force microscopy and X-ray photoelectron spectroscopy. The samples were prepared by immersion plating in 0.1 mM KAuCl4 and 5 M HF aqueous solutions. Fig. 18(a) and (b) show tapping mode AFM images of the pristine Si(100) and Ge(100) samples, respectively, after etching in HF. The surfaces are flat, with root-mean-square (rms) roughnesses of 0.08 and 0.24 nm, respectively. After immersion in the plating solution for the specified times, the samples were imaged in air. Fig. 18(c) (Si) and (d) (Ge) show images taken after a 5 s deposition. Small clusters in the range of 10–30 nm are formed on both surfaces with fairly uniform distributions. The cluster density increases with time for both substrates (Fig. 18(e) and (f)) after deposition for 60 s. The Si surface is covered more rapidly, as would be expected of the less noble substrate. It is somewhat surprising that at these very early stages, the difference in Au coverage is accounted for, primarily, by a higher number of nucleation sites, rather than by the larger size of the individual nuclei. Thus, the formation of gold films on Si proceeds from clusters distributed uniformly all over the active surface. However, following the completion of a first layer of nuclei at the Si surface, growth proceeds with the formation of overlayers of large isolated structures, as evidenced in Fig. 18(g) after 10 min deposition. The surface rms roughness is about 18 nm.

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Fig. 18. Atomic force micrographs of clean (a) Si(111) and (b) Ge(111) surfaces, and these surfaces taken after immersion plating in 0.1 mM Au, 5 M HF aqueous bath for 5 s (c, d), 1 min (e, f) and 10 min (g, h). Scan area of 1 × 1 µm2 . The rms roughness values of the various surfaces are (a) 0.08 nm, (b) 0.24 nm, (c) 0.84 nm, (d) 0.96 nm, (e) 1.7 nm, (f) 1.8 nm, (g) 19 nm and (h) 1.9 nm. Reprinted with permission from Ref. [86]. c 2002, American Chemical Society.

In contrast, Fig. 18(h) shows the formation of much smoother overlayers on Ge substrates following the cluster island growth mode of the first layer, with the rms roughness remaining around 2 nm after 10 min plating. At this stage of growth, a resemblance is noted with the previous work [66] on Pd nucleation on Si vs. GaAs, and therefore the different interface strengths of the fully formed films may be attributed to the differences in the number and morphology of the anchoring clusters. As already discussed in Section 4.2, the difference

in chemical bonding between the Si–Au and Ge–Au system is responsible for the difference in interfacial strength of the two systems. Motivated by the quest for high-density memory, Osaka et al. used galvanic displacement to deposit Ni particles on Si [167]. Because the standard electrode potential of Ni (−0.26 V) is lower than that of H, deposition of Ni requires an alkaline bath (pH = 8). The displacement reaction is effected in the absence of fluoride ions, and hence, a thick oxide layer is present at the

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Ni nanodot–Si interface, as revealed by transmission electron microscopy. Subsequent to the nucleation of the metallic Ni dots, the substrate is transferred to an electroless NiP bath to complete the nanodots’ growth. The authors show that nanodot arrays can be fabricated simply by patterning an oxide film on the Si substrate. This selectivity to elemental Si regions of the substrate is due to the fact that the initial nucleation step is a galvanic displacement process. The kinetics of Au nucleation on Si(111) from aqueous solutions of KAu(CN)2 and HF has been studied by second harmonic generation, extinction spectroscopy and atomic force microscopy [168]. By correlating the SHG signal with cluster size, the authors were able to measure the Au cluster growth rate in situ. This in turn was used to determine the order of the displacement reaction with respect to [HF] and 1 [Au(CN)− 2 ], yielding values of 2 and zero, respectively. The latter value indicates an excess of available Au ions, but the Au concentration could only be varied within a fairly restricted range, due to the weakness of the SHG signal at one end, and particle coalescence at the other. 6.3. Galvanic displacement from microemulsions Applications to catalysis, plasmonics and electronics often require a greater degree of control in cluster size distribution than is encountered in metallic dots formed in the early stage of film nucleation. A novel method was devised by Magagnin et al. [166] to tighten the size distribution of nanoparticles deposited by galvanic displacement, based on immersion plating in reversed micellar solutions of the plating bath. A reversed micellar solution is a dispersion of nanometersized water drops in oil, which are stabilized by the presence of a surfactant. Much work has been devoted to the theory and application of micellar solutions [169,170]. A particularly well studied system is that of water, sodium bis(2-ethylhexyl) sulfosuccinate (AOT) as the surfactant, and an n-alkane as the oil. The size of the micelle in these systems is known to be a function of the microemulsion parameter R, defined as the ratio of the molar concentrations of water and surfactant (R = [water]/[surfactant]). For instance, for reversed water micelles in n−heptane, the concentrations of water and AOT and the radius of the micelles follow the linear relation Rmicelle = 0.175R + 1.5,

(17)

where the micelle radius Rmicelle is measured in nanometers. The conventional approach to obtaining metal clusters in solution is based on the mixing and reacting of two different micellar solutions, e.g., one (A) carrying a metal salt and the other (B) carrying a reducing agent [171]. Nanocluster formation ensues upon the collision of micelles of the A and B types, with material exchange between them and the subsequent reduction of the metal ions in A by the reducing agent of B. This nonselective electroless process would lead to blanket cluster deposition upon substrate immersion. In contrast, the method based on galvanic displacement from micellar solutions allows size and location control of the Au nanoclusters deposited on Si surfaces. In this process, only one type of solution is present

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Fig. 19. Schematic of immersion plating from an inverted micelle solution. The continuous medium is oil. The surfactant molecules expose their hydrophobic tails to the oil to solubilize the water droplets, which are in contact with the hydrophilic moiety of the surfactants. The size of a micelle is determined by the ratio of the molar concentrations of water to surfactant. Metal salt and fluoride ions, dissolved in water, are contained inside the micelles and are released upon the micelle–substrate impact. The metal ion is reduced by the substrate atoms, leaving behind a small metallic cluster.

(solution A), which may contain a fluoride species in addition to the metal salt. The solution is stable, with the metal in its oxidized state; however, when a micelle impinges on the semiconductor substrate, it delivers a droplet of plating bath of controlled volume. The solution reacts with the substrate and the metal ions are reduced by the galvanic displacement mechanism (Fig. 19). The average size of the deposited Au clusters was probed by X-ray diffraction in Ref. [166], as the width of the Au(111) diffraction peak is related to Au crystallite size through Scherr’s law. The authors probed the microemulsion parameters R = 1, 50 and 100, and showed that cluster size is determined by R, and not by deposition time. Longer immersion times in the plating microemulsion resulted in higher intensity of the XRD peak, but the peak width depended only on R. In other words, plating time only affected cluster density, but not cluster size. Gao et al. used galvanic displacement from microemulsions to deposit catalyst nanoparticle seeds for the subsequent growth of Si nanowires (vide infra), and probed a larger set of microemulsion parameter values [164]. They used field emission scanning electron microscopy (Fig. 20) to characterize the Au clusters deposited on Si(111) substrates from microemulsions with R values of 16 (a), 25 (b), 50 (c), 100 (d), and 200 (e) respectively. They observed that the size of the Au clusters appears to be fairly uniform on each sample. They extracted the Au cluster diameter as a function of R (see Fig. 21). The mean diameter of the Au clusters increases roughly from about 20 to 140 nm as R increases from 16 to 200, and these measurements are in agreement with the radii previously reported by Magagnin et al. [166]. It is worth noting that when the galvanic displacement process is performed in a water-based solution instead of microemulsions (i.e., without AOT or heptane), the size of the Au clusters has a wide distribution from 30 to 300 nm, and substantial cluster agglomeration is observed (Fig. 20(f)). Thus, the authors concluded that the microemulsions are effective in reducing the aggregation of nanoparticles during the galvanic displacement process, and enable the tuning of the Au nanodots size by tuning the microemulsion parameter R.

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Fig. 20. Scanning electron micrograph of Au clusters deposited on Si(100) substrates by immersion plating from microemulsion solutions with R values of 16 (a), 25 (b), 50 (c), 100 (d), and 200 (e). For comparison, (f) shows the metal deposit obtained by immersion plating from an aqueous solution. Reprinted with permission from Ref. [164]. c 2005, American Chemical Society.

Fig. 21. Average cluster diameters obtained from the analysis of the scanning electron micrographs of Au clusters deposited on Si(100) by galvanic displacement from microemulsions with various R values. Reprinted with permission from Ref. [164]. c 2005, American Chemical Society.

6.4. Nanowire growth from metal catalysts deposited by galvanic displacement Semiconductor nanowires are quasi-one dimensional structures with interesting physical, optical and mechanical properties, which make them good candidates for advanced

applications such as interconnects and functional units in electronic, optoelectronic, electrochemical, and electromechanical devices. Although proofs of concept have been given of various nanowire-based devices for sensing, electron and ion gating, and lasing, researchers face serious challenges in the synthesis, assembly and interfacing of nanowires for high yield batch-fabrication of reproducible devices. Among the synthetic approaches to nanowire fabrication, metal cluster-catalyzed growth from gas phase precursors is probably the most common method for obtaining high quality nanowires. The process is thought to proceed by vapour–liquid–solid (VLS) [172–174] or vapour–solid–solid (VSS) [175] mechanisms. The diameters of the nanowires synthesized in this manner is largely determined by the size of the metal clusters that serve as the nucleation sites during the initial phase of nanowire growth. The metallic clusters are conventionally obtained in either of two ways. One involves the deposition of a uniform Au film, which breaks up into more or less spherical aggregates upon high temperature annealing. These aggregates serve as the clusters to catalyze nanowire growth. This methods suffers from poor cluster size control and from being substrate unspecific, in that the wire growth occurs everywhere.

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Fig. 22. Scanning electron micrograph of silicon nanowires grown on Si(111) substrates by the VLS method, using as catalyst Au clusters deposited by immersion plating from microemulsion solutions with R values of 16 (a), 25 (b), 50 (c), 100 (d), and 200 (e), or from aqueous solution (f). Insets: close-up of the wires, showing the more uniform wire diameters in (a–e) relative to (f) (scale bar = 300 nm). Note the catalyst droplets decorating the tips of most wires. Reprinted with permission from Ref. [164]. c 2005, American Chemical Society.

From the design and manufacturing perspective, the ability to control the nanowires’ size, orientation and location during growth is highly desirable. Indeed, if the growth and assembly of nanowires are combined in a single step, subsequent fabrication processes are facilitated by the epitaxial nature of the wire-substrate interface, which implies good electrical as well as mechanical [176] contacts between wire and substrate. Nanowires synthesized via the VLS or VSS mechanisms generally have a preferred growth direction, whereby they tend to align along the h111i direction, possibly as a consequence of epitaxial growth (the nanowire axis usually, but not always, lies along a close packed crystallographic direction). This characteristic has been exploited to align nanowires by choosing the proper substrate orientation. For example, Si nanowires grow preferentially along the h111i direction, and hence, vertically aligned nanowires can be obtained on a Si(111) substrate, while laterally aligned Si nanowires are obtained on vertical Si(111) planes exposed by a straight etch of a (110)-oriented Si wafer. In those experiments where the nucleating metal catalysts are deposited by physical vapour deposition or by immersion in colloidal gold suspensions, the entire substrate is covered indiscriminately. As a result, a thick

mesh of nanowires grows everywhere, frustrating attempts to fabricate useful devices. For example, in the case of Si nanowire bridges formed between sidewall trenches fabricated on (110) Si substrates, the nanowires grow both inside and outside of the trenches, as well as on top of the electrodes and every other place on the substrate. It is easy to appreciate why the metal catalysts should only be deposited in the locations where the nanowires are desired. Gao et al. have used galvanic displacement to selectively deposit Au catalyst on Si surfaces for the growth of vertically and laterally aligned Si nanowire arrays [164]. Water-in-oil microemulsions were employed to control the size of the Au clusters. The authors showed that cluster size correlates with nanowire diameter, as shown in Fig. 22 for growth on Si(111) substrate. The fabrication process for horizontal nanowire structures used in their work is a recurring motif in horizontal nanowire device processing [177,178], and is schematically illustrated in Fig. 23. The (111) sidewall-exposed structures are etched into a (110) silicon-on-insulator (SOI) substrate. The horizontal surfaces (top of SOI as well as bottom of the trenches) are covered by a thick oxide (hundreds of nm), and thus resist short time etches in hydrofluoric acid. Galvanic

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Fig. 23. Schematic of the fabrication process used to produce horizontally aligned nanowire arrays. (a) Patterning of the oxide-capped Si(110) SOI wafer exposes the (111) sidewalls. (b) Immersion plating in microemulsion solution deposits uniform catalyst clusters selectively on the exposed sidewalls. Reprinted with permission from Ref. [164]. c 2005, American Chemical Society.

displacement deposition of Au as the catalyst results in the presence of metallic nanoclusters exclusively on the vertical sidewalls of the trenches. If microemulsions are employed (as they were in Ref. [164]), the size and coverage of clusters can be tightly controlled. Fig. 24 shows field emission scanning electron microscopy images of the final structures after growing Si nanowires on such structures by the galvanic deposition of Au nanoclusters as catalyst. Dense Si nanowires, with diameters ranging from 100 to 300 nm, are grown laterally from the (111) sidewalls of Si pillars. The nanowires are straight, have a uniform length of about 15 µm, and are well aligned (90◦ to the sidewalls). It is also evident that the nanowires only grow on the Si sidewalls and are absent from the tops and bottoms of the samples where SiO2 (rather than Si) is exposed, as expected from the selectivity towards Si of metal deposition by galvanic displacement. Another advantage of this deposition method is the uniform density of nanowires grown across 80 µm deep trenches. Achieving such a degree of uniformity would be a major challenge if Au were deposited by physical vapour deposition. The process versatility and synthetic advantages of the galvanic displacement method of catalyst deposition have been exploited by San Paulo et al. to design and fabricate novel mechanical beam-like structures comprised of freely suspended single crystalline Si micropaddles alternating with horizontal Si nanowire arrays grown from microemulsion-deposited catalyst Au nanoparticles [165]. The fabrication process flow begins

with the steps outlined in Fig. 23 above. The nanowires are grown for a sufficient time to bridge the gap across the trench. A long HF etch results in the complete underetching of the SOI device layer, resulting in freestanding micropaddles suspended by the nanowire arrays (Fig. 25). This composite mechanical structure yields a low spring constant and an exceptionally high surface area. It illustrates the power of designing in a process that combines bottom-up growth with top-down fabrication and selective catalyst deposition. Doping is a major problem in the so-called bottom-up methods of nanowire fabrication, like the VLS and VSS methods, examples of which have been discussed above. Moreover, since nanowires tend to grow in the closed-pack direction, it is hard to obtain wire growth in an arbitrary crystallographic orientation. In contrast to bottom-up synthesis, straight top-down fabrication methods, by which the wires are etched away from a bulk substrate, obviously do not suffer from either shortcoming. Advanced lithographic techniques can be employed toward the goal of fabricating top-down nanowire devices, but the process flow involved is quite laborious. A simple electrochemical process has been employed by Peng et al. to fabricate highly oriented SiNW arrays by etching single crystalline silicon wafers in an aqueous HF solution containing Fe3+ ions. It is based on the metal-seed-induced excessive local oxidation and dissolution of the substrate [179, 180]. Metal nanoparticles are deposited on the Si substrate by a galvanic displacement reaction. The metallized wafers are subsequently immersed in an aqueous HF/Fe(NO3 )3 solution at 50 ◦ C for 30 min, after which the substrate acquires a blacklooking aspect. The formation of aligned nanowire arrays is confirmed by SEM. The authors proposed an etching mechanism by which the metal nanoclusters catalyze the oxidation of the substrate. This may happen because the higher electronegativity of the metal cluster attracts electrons from the Si substrate, which is then more readily oxidized. In other words, the metal nanoparticles are proposed to act as local microcathodes and promote the cathodic reaction Fe3+ + e− → Fe2+ . The oxidized Si is then rapidly removed by the HF, causing the catalyst to sink into the bulk silicon, and giving rise to either porous Si at low coverage (the pores corresponding to the original location of the disconnected nanoparticles), or to arrays of straight Si nanowires (when the nanoparticles form interconnected networks). The nanowires produced in this manner have cross sections of three main shapes: wires, ribbons, and triangles. Interestingly, the size of a nanostructure appears to influence its shape, with ribbons typically 150–250 nm wide, round wires typically 10–20 nm in diameter, and triangles typically 80–150 wide. These 1D nanostructures are usually smooth from top to bottom and there is almost no diameter variation along the axis, indicative of a straight sidewall formation during the etch [180]. The effect of using different metal catalysts, such as Au, Ag and Pt, in the etch process described above has also been characterized [180]. Differences were observed that could be attributed to two main causes. One is that different catalyst nanocluster film morphologies are obtained in galvanic

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Fig. 24. Scanning electron micrographs of silicon nanowire arrays grown selectively on the sidewalls of a patterned SOI wafer (see Fig. 24 for process schematics). Note the high alignment of the wires, the selectivity of the catalyst deposition process, and hence, of the growth, to the sidewalls, and the uniformity of the areal density of the arrays over the whole depth of the trenches (80 µm). The scale bar is 20 µm (2 µmin inset). Reprinted with permission from Ref. [164]. c 2005, American Chemical Society.

displacements from solutions of different noble metal salts. For instance, the strong reaction between silicon and solutions of HF/AgNO3 tends to produce large quantities of silver dendrites. Gold nanoparticles also have a strong tendency to form dense networks, but platinum particles remain isolated, producing only well separated pores. Another interesting difference is that while Ag and Au nanoparticles sink straight into the substrate, producing straight etch sidewalls and hence, straight nanowires, the pores excavated by Pt clusters are not as straight. This observation points to a difference in the propagation of the Si-metal interface in the two cases. Its cause remains unknown. 6.5. Complex nanostructures grown by galvanic displacement processes In addition to studies establishing the usefulness of galvanic displacement processes for seeding the growth of semiconductor nanostructures, recent work provides a proof of concept that galvanic displacement can be employed to realize a number of metallic nanostructures as well. Porter et al. have reported on metal nanostructure fabrication by static

Fig. 25. Suspended silicon micropaddles joined by sidewall-grown silicon nanowire arrays. Reprinted with permission from Ref. [165]. c 2007, American Chemical Society.

plowing lithography and galvanic displacement plating [116]. The process flow is comprised of the following sequence of steps. First, a layer of polymer resist is applied onto a Ge(111) substrate, and then the resist is patterned by plow nanolithography, in which an atomic force microscope tip is used to scrape off the polymer in a desired pattern. Upon the immersion of the substrate in a dilute metal salt aqueous

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Fig. 26. Galvanic displacement of silver on Ge(100) from 1 mM aqueous AgNO3 . (a) Optical viewgraph of Ge chip (1 cm × 1 cm) denoting areas where scanning electron micrographs (b, c, and d) were obtained; (b) silver platelet stacks (nano-inukshuks); (c, e) region of germanium oxide and some silver deposits (chemical composition determined by EDS); (d, f) dendritic structures are visible near the corners of the chip. Reprinted with permission from Ref. [182]. c 2005, American Chemical Society.

solution, the exposed regions of the Ge substrate displace the metal ion, leading to the formation of nanostructures in the previously patterned shape. Finally, a solvent rinse removes the polymer mask. The lithography steps can be bypassed entirely, however. It is well known that complex patterns arise in the electrodeposition of metals, as a consequence of the strong nonlinearities of the process. This complexity can sometimes be exploited to create new nanofabrication paradigms, the best known of which is perhaps the spontaneous formation of ordered hexagonal arrays of nanopores during the anodization of aluminum films [181]. In galvanic displacement processes, the necessary etching and charge transport in the semiconducting substrate add to the complexity brought about by mass diffusion and charge transport in the solution. The spontaneous formation of complex nanostructures was reported by Aizawa et al. [182] upon immersion of germanium substrates in aqueous silver solutions at room temperature. Systematic studies of the function of Ag+ concentrations reveal a progression from predominant substrate etching (10−5 M), to formation of etch pits with metallic nuclei inside of them (10−4 M), to extended growth of nanostructures with global dendritic aspect for longer deposition times (10−3 M and higher). These structures are comprised of silver platelets of predominantly regular hexagonal shape, regardless of the Ge substrate’s orientation.

Before branching into dendrites, these platelets are stacked upon one another to form structures reminiscent of the (manmade) stone inukshuks, and were thus termed nano-inukshuks (Fig. 26(b)). These structures begin to grow perpendicular to the substrate. Long growth times and/or high growth rates favour the development of branched dendritic structures, which the authors have shown are found predominantly around the edges of the substrate (Fig. 26(a) and 26(d)). The observation is consistent with the finding that the contact angle of hexadecanethiol-coated Au films formed by galvanic displacement and long deposition times regularly exceeds 120◦ , which is indicative of fractal growth [148]. The production of metallic nanostructures of controlled size, shape and structure, as well as their integration with semiconductors, is important for a variety of technological applications. Shape and size have a strong influence on optical, electrical, and catalytic properties of metal nanoparticles. The controlled growth of silver nanostructures of several different regular geometric shapes has been accomplished by the reduction of silver nitrate with ethylene glycol at 160 ◦ C in polyvinylpyrrolidone [183,184]. Galvanic displacement by immersion in aqueous HAuCl4 was then employed to turn the silver solid shapes into (hollow) Au shells. These experiments demonstrated that any method of producing silver nanoparticles of well-controlled shape and size by galvanic displacement can be used to produce Au nanostructures as well by a second displacement process, even though the original method by itself may not lead to regular nanostructure formation when employed directly with Au salts. More generally, a sequence of displacement reactions can be used conveniently to transform any nanostructure built of a less noble metal into one made of a more noble one. The starting point of this sequence of displacement reactions might conceivably be a semiconductor nanostructure as well. Although we are not aware of any report to this effect, we note that immersion plating has been used to metallize Si nanowires grown by metal-catalyzed CVD [185]. The nanowires were decorated by immersion plating in solutions of AgNO3 and NaAuCl4 ·2H2 O, leading to the assembly of Ag (30–100 nm diameter) and Au (5–25 nm diameter) nanodot arrays. The dots are spaced a few nanometers apart. Improved coverage resulted when HF was added to the metal solution, since HF promoted the removal of silicon oxide from the nanowire surface (the growing oxide layer eventually suppresses the formation of metal nanocrystals). The authors suggested that such metaldecorated nanostructures would be useful for sensing of an analyte by optical or electrochemical methods. Since its discovery almost thirty years ago, the enhancement of the Raman signal from molecules adsorbed on nanostructured metallic surfaces continues to receive much attention (an excellent review of the early work in the field is found in Ref. [186]). While great progress has occurred in the theoretical understanding of the effect, the realization of stable and reproducible substrates for surface enhanced Raman scattering has proven to be an elusive goal. Among the metals that are reported to exhibit SERS, silver is the one for which the cross section enhancement is the highest, ceteris paribus. Liu and Green have

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developed a fabrication scheme to produce Ag nanostructures in the shape of rods and tori [89]. The process combines socalled “Island Lithography” and galvanic displacement. Briefly, uniform arrays of holes are etched into a Si substrate through a SiO2 mask. Silver is deposited selectively in the holes from an aqueous solution of AgNO3 containing variable amounts of HF. The authors noted the uniform nucleation of Ag at low HF concentration, with growth of solid metallic nanopillars. However, as the concentration of HF was increased, preferential nucleation along the Si/SiO2 edge of the etched holes was observed, and as a consequence, the resulting Ag nanostructures had toroidal shapes, resembling a bracelet of Ag beads. Interestingly, these toroidal nanostructures were observed to become unstable when subjected to prolonged exposure in solutions of various analytes. The main cause of instability was attributed to the tendency of the largest bead of a bracelet to grow at the expense of the smaller ones. This growth, which is driven by the size-dependent chemical potential of the metallic beads and can be slowed down by the application of surfactants, ultimately leaves nanopillar-like structures in place of the nanotori [187]. Whatever the final shape of the metallic structures, the reported 100 million-fold enhancement of the pyridine signal attests to the suitability of immersion plating for fabrication of SERS substrates.

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Acknowledgments The authors’ work on this subject has benefited greatly from discussions with many colleagues and coworkers over the years. In particular, we wish to thank Pietro Luigi Cavallotti, Michaela Fritz, Di Gao, Roger Howe, Ilaria Lombardi, and Alvaro San Paulo. Financial support from the National Science Foundation and from the Ministero dell’Universit`a e della Ricerca Scientifica is gratefully acknowledged. References [1] [2] [3] [4] [5] [6] [7]

[8] [9] [10]

7. Conclusions

[11]

The development of metal deposition processes based on galvanic displacement on semiconductor surfaces has witnessed a surge in interest among researchers, with many recent applications devoted to patterning and nanostructure fabrication. The complexity of semiconductor electrochemistry and surface structures is certainly the main reason why our knowledge and control of these processes is much less advanced than in the relative mature technology of immersion plating on metal base materials. However, it has become apparent that this very complexity opens up tremendous possibilities in the design and development of functional semiconductor nanostructures and in their integration with microscale probes and devices. The deposition of metals by galvanic displacement requires a tight control of the surface preparation and of the reaction rates. It usually proceeds very fast; hence defects, non-uniformities and impurities at the surface will be sources of uncontrolled growth of the metallic layers, which in turn leads to a loss of adhesion. In this sense, additives to the electrolyte, such as hydrogen scavengers, surfactants, or complexing agents, and the adjustment of the deposition parameters, such as temperature or pH, help us to reach a homogeneous, instantaneous and controlled nucleation, which is required for the subsequent growth of an adherent and uniform metallic film. Adhesion undoubtedly is also promoted by a strong interaction between the metal and the semiconductor, and the formation of intermetallic compounds of the semiconductor and noble metals will generally improve adhesion. However, as for the electroless and electrolytic depositions, a universal rule does not exist.

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