Micro cantilever probe array integrated with Piezoresistive sensor

Microelectronics Journal 35 (2004) 479–483 www.elsevier.com/locate/mejo

Micro cantilever probe array integrated with Piezoresistive sensor Zunxian Yang, Xinxin Li*, Yuelin Wang, Haifei Bao, Min Liu State Key Lab of Transducer Technology, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China Received 27 September 2003; revised 14 November 2003; accepted 3 December 2003

Abstract A micro cantilever-tip silicon probe-array with integrated electro-thermal nano-tip and piezoresistive sensor has been presented for NEMS high-density data storage. After its fundamental working principle has been illustrated, such a 1 £ 10 probe-array has been designed. Both analysis and FEM simulation are used for modeling and designing with their results agreeing well with tolerance of only 5%. The device has been fabricated with silicon bulk micromachining technologies. The relationship between the heating resistance and tip temperature was experimentally obtained and fitted with second order polynomial function. Based on those, the microsecond-instantaneous electro-thermal performance of the device has been gained and the tested results were in agreement with the simulated ones. Under the 4 V pulse power and 3 ms heating time, the tested results were indicative of the 463.15 K temperature on the tip, the 6.2 ms decreasing-temperature constant of the heating resistor and the nearly 100 KHz reading – writing velocity. The sensitivity of piezoresistivity was up to 5.4 £ 104 under the force of 2 £ 1027 N, which was sufficient to read out the data from the polymer indent. q 2003 Elsevier Ltd. All rights reserved. Keywords: Cantilever-tip probe; Nanoelectromechanical technology; Piezoresistive sensitivity; Electro-thermal nano-tip

1. Introduction The rapid development of information technology has shed higher and higher demand on the performance of storage. Even though the storage, as the medium of transferring information, has developed fast in the latest decades, especially in the last decade, it still does not match up to the demand of information technology. A micro cantilever-tip silicon probe-array integrated with electrothermal nano-tip for high-density nanostorage are characteristic of array-integration and batch-production and their area-density up to a few tens or hundreds Gbit/in2 can be achieved. Previous work either uses two probe for independently piezoresistive reading and electro-thermal writing, respectively, or uses one electro-thermal-tip for both reading and writing [1,2]. The former cannot realize reading and writing with the same device. The latter does not facilitate independent optimization of reading and writing performance. Integration of piezoresistive sensor and thermal tip together on a cantilever is a good solution. This paper pays attention to the study of one array probe integrated with piezoresistive-reading and electro-thermal * Corresponding author. Fax: þ 86-21-62513510. E-mail address: [email protected] (X. Li). 0026-2692/$ - see front matter q 2003 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2003.12.001

writing on a cantilever. After its fundamental working principle has been illustrated, the probe-array has been designed by both analysis and FEM simulation. The device has been fabricated with silicon bulk micromachining technologies. Attention has been paid to the analysis and testing of electro-thermal heater and piezoresistive sensor. The tested results are in agreement with the simulated ones.

2. Principle and design The probe-array includes ten cantilever-tip probes with integration of nano-tip, heater and piezoresistor as shown in Fig. 1. In data writing, the cantilever has been applied a little force (1027 N [1]). The heater has been heated by the writing pulse current. The nano-tip is made into contact with spinning polymer medium to form memory indent. However, in data reading, the cantilever has also been exerted a little force. When the nano-tip runs from a flat place to a memory indent, the piezoresistor can sense the difference of the displacement of cantilever by varied electro signal. Because its nanosize, the tip is fast enough to be heated by signal pulse current that helps to form nanometer’s memory indent and realize

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Fig. 1. Schematic of single cantilever probe with piezoresistor and nano-tip integrated.

the ultra-high-density storage with area-density up to a few tens or hundreds Gbit/in2. Based on the data writing and reading, a 2 £ 1027 N force [1] has been applied on the tip. So in terms of a cantilever beam with a concentrated end loading, the max displacement, elasticity coefficient, the max stress and fundamental frequency have been gained in Table 1. In Table 1, the original force on the tip F is 2 £ 1027 N; the length ðLÞ; width ðbÞ and the thickness ðhÞ of the cantilever are 102 £ 1026, 38 £ 1026 and 2 £ 1026 m, respectively; the Young’s modulus of silicon, E is 1.69 £ 1011 Pa; the density of silicon, r is 2330 kg/m3. According to what has been shown in Table 1, the analysis results are in well agreement with the simulated ones.

3. Fabrication For probe fabrication the starting material is an SOI wafer with a 8 mm-thick N-type top silicon layer, 1 mmthick thermal oxide and 350 mm-thick silicon substrate, respectively. After thermal oxidation, the tip region has been patterned and the SiO2 outside the regions is removed with buffered HF, as shown in Fig. 2a. The tip with about 30 nm curvature-radius is formed by KOH etching (Fig. 2b) and oxidation sharpening at 950 8C [4,5]. The sharpened tip is shown in Fig. 3a. Boron is doped three times to heater, piezoresistor and wire connection hole (Fig. 2c –e), respectively. After aluminum interconnection (Fig. 2f), RIE is used from front side to shape the cantilever in top layer of SOI wafer (Fig. 2 g). Then ICP-DRIE is performed from the backside to etch through the substrate. After the SiO2 layer striped with BHF, the cantilevers are released (Fig. 2h) and shown in Fig. 3b and c.

In probe fabrication, especially in tip fabrication, instead of direct oxidation sharpening, all the thermal oxidation processes has been controlled at 950 8C and the oxidation sharpening was completed step by step in all those thermal oxidation. Thus, to some extent, it will prevent the sharpened tip from being blunt in the following processes. Moreover, in heater fabrication, both the cuniform hole by RIE and the whole p-type in the heater region by long time diffusing in nitrogen all contribute to the performance of heater, especially at high temperature.

4. Results 4.1. Static electro-thermal performance of silicon tip For studying the thermal performance of heater, the electro-thermal model (Fig. 4) has been simplified as: (a) The cantilever has been divided into heating region and conducting region (called as variant temperature region) (b) Thermal conductivity in solid dominates, and the temperature at the root of the cantilever is assumed at room temperature, Tr (300 K). According to the flat wall heat exchange equation [6], the quantity of heat transferred by the section of cantilever can be expressed as: Q¼


zKsi hðTh 2 Tr Þ
 29 19 17 þ ln 19 5 12

ð1Þ

where Th is the temperature of heating region, effective heat-transferring factor, z ¼ 0:46, heat conductivity of silicon Ksi ¼ 148 w/m k, thickness of silicon, h ¼ 2 £ 1026 m room temperature, Tr ¼ 300 k. The relationship between the resistance of heater and the temperature of tip has been obtained and fitted with polynomial function (Fig. 5) expressed as: Rh ðTh Þ ¼ Rh ðTr Þb1 þ ah1 ðTh 2 Tr Þ þ ah2 ðTh 2 Tr Þ2 c

ð2Þ

where temperature coefficient ah1 and ah2 are 5.3237 £ 1024 and 3.4992 £ 1026 K22, respectively, the resistance at room temperature Rh ðTr Þ is 560 V.

Table 1 the mechanical parameters of the cantilever Dynamic parameter

Theoretical analysis expression [3]

Theoretical analysis results

FEM simulated results

The max displacement on tip (nm)

4FL3 Ebh3 Ebh3 k ¼ 4L3 Tmax ¼ 6FL bh2 h f0 ¼ 1:0019 2p L2

16.525

17.4

5

12.103 8.0526 £ 105

11.494 9.0551 £ 105

5 11

2.6106 £ 105

2.92814 £ 105

10

Elasticity coefficient (N/m) Max strees (N/m2) Fundamental frequency (Hz)

ymax ¼

qffiffiffi E r

Tolerance(%)

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Fig. 4. Simple thermal–electrical model of cantilever.

On thermal balance, the relation between the applied voltage on the heater and the temperature on the tip is expressed as 2 Vappl Rh ðTr Þ½1 þ ah1 ðTh 2 Tr Þ þ ah2 ðTh 2 Tr Þ2 

¼


Fig. 2. Process flow of the devices (a) oxidation and pattern the tip area, (b) KOH etch for tip, (c) light boron diffusion for heater, (d) dense boron diffusion for hole; (e) light boron diffusion for piezoresist; (f) pattern Al for wire; (g) etching silicon for cantilever; (h) deep trench etch through wafer to release component.

zKsi hðTh 2 Tr Þ
 29 19 17 þ ln 19 5 12

ð3Þ

On the basis of the relationship between the temperature at the tip and the resistance of heater as shown in Eq. (2) and Fig. 5, both the tested and simulated relationships between the temperature at the tip and voltage supply on the heater have been gained, respectively, Fig. 6 shows that tested temperature at the tip versus voltage supply on the heater agrees well with that of the modeling, which, in return, verifies the rationality of the assumption in the electrothermal model. 4.2. Instantaneous electro-thermal performance of silicon tip The thermal characteristics of the heaters can be probed electrically, by using the temperature-dependent resistivity of the heater as an on-board thermometer. Fig. 5 has shown the resistance of heater versus the temperature. When a voltage pulse is applied to the heater, its resistance would increase as it heats up. This increase in resistance can be measured by monitoring the current through the heater.

Fig. 3. SEM and CCD images of the formed structure: (a) the SEM image of tip; (b) the CCD image of probe-array; (c) the CCD image of single cantilever.

Fig. 5. The resistance of heater versus temperature.

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Fig. 6. Relationship between temperature of tip and applied voltage by both testing and modeling.

Fig. 8. The tested and simulated temperature of heater versus time under voltage ¼ 4 V and the heating time ¼ 100 ms.

After the pulse has elapsed, the heater resistance would gradually decrease to its room temperature value as it cools. If a small dc test voltage is present across the heater after the pulse has ended, this decrease in resistance can be measured as well. It is, therefore, possible to measure the temperature of heater during both the heating stage and the cooling stage. The rate of cooling corresponds to the thermal time constant and determines how fast successive marks can be written, i.e. the data writing speed. In the experiment, a 4 V 3 ms heating pulse applied across the heater brings about tested and simulated instantaneous-temperature at tip versus the time as shown in Fig. 7. Also, a 4 V 100 ms heating pulse across the heater gains tested and simulated instantaneous-temperature at the tip versus the time (Fig. 8). Figs. 7 and 8 indicate that the heater be heated to 463.15 K in 3 ms heating time with 4 V pulse supply, which is sufficient for data writing on polymer media film. With the increase of the heating time, even though the temperature will go up, it does very slowly and saturates in the end. Furthermore, the rate of cooling is high enough to ensure the data writing speed. In 3 and 100 ms heating time, the decreasing-temperature-time constants are 6.2 and 119.15 ms, respectively,

with 4 V pulse supply. To a large extent, it is the key factor to shorten heating time and ensure high data writing speed. Therefore, the single-probe data writing speed of about 100 KH2 can be realized by employing 3ms heating pulse. Figs. 7 and 8 has shown that tested instantaneoustemperature at the tip versus the time was on well agreement with the simulated ones except for quicker heating velocity and cooling velocity in testing. It is the oxidation in the SOI that holds back the thermal conductivity and quickens the heating process, however, it is the aluminium wire on the cantilever that accelerates the thermal conductivity and speeds up the cooling process. In analysis simulation, all those have not been considered. 4.3. Sensitivity of the piezoresistor Based on the performance in Table 1, the calculated sensitivity of piezoresistor has been gained with assumption of 20 nm displacement at the tip. The calculated and tested sensitivity and output voltage have been shown in Table 2. Here elasticity coefficient K is 12.1 N/m, piezoresistive coefficient p44 100 £ 10211 /Pa and input voltage on heater Vinput 5 V. For testing the sensitivity of piezoresistor, AFM has been employed to apply force on the tip area. When the cantilever has been exposed to different force, the resistance of Table 2 Sensitivity of the piezoreisistor

Fig. 7. The tested and simulated temperature of heater versus time under voltage ¼ 4 V and the heating time ¼ 3 ms.

Parameter

Expression

Calculated value

Tested value

Force on tip (N) Sensitivity of piezoresistor Output voltage (mV)

F ¼ kx

2.4206 £ 1027 (x ¼ 20 nm) 3.117 £ 1024

2.4206 £ 1027 (x ¼ 20 nm) 5.404471 £ 1024

0.389665

0.67556

0

3p44 Fðh2h Þ DR  R ¼ 1  bh3 L2 2 V DR Voutput ¼ input R 4

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heating time with 4 V pulse supply to be capable of nearly 100 kHz writing rate by single probe. The piezoresistor has been characterized with sensitivity of 5.404 £ 1024/m under 200Nn force applied, which is sensitive enough for data reading.

Acknowledgements The authors are grateful to the NSFC project (60376038), the chinese Major State Research Development Program (G1999033101) and Shanghai R & D Program on Nano-production Technology (0111 NM077). Fig. 9. The tested and calculated resistance of piezoreisistor versus the applied force on the tip.

piezoresistor can be tested and the tested and calculated resistance versus the force on the tip come forth (Fig. 9). Fig. 9 and Table 2 indicate that the tested resistance versus the force on the tip shows a little larger than the calculated one. Maybe, it is because of the smaller piezoresistive coefficient in calculation. On the whole, the calculated are on well agreement with the tested. Thus the probe can read out the displacement of 20 nm on the tip.

5. Conclusion We have fabricated micro cantilever probe-array with integration of electro-thermal nano-tip and sensitive piezoresistor by using silicon bulk micromachining technologies. During fabrication of heater, both cuniform hole by DRIE and high temperature diffusion in nitrogen technologies has been adopted, which in a sense avoid pn-junction’s creepage at high temperature. The second order curve relationship between the resistance of heater and temperature has been gained by temperature-resistance demarcating technology. A suitable electro-thermal model has been brought about, and further the static electro-thermal performance has been characterized and is in agreement with the calculated one. The instantaneous electro-thermal results agree well with the simulated ones. It is sufficient for the probe in 3 ms

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Z.X. Yang received the BS and MS degrees in Resource and Environment Engineering and in Materials Engineering, respectively, from Wuhan University of Technology, Wuhan, China, in 2001. He is currently working towards the PhD degree at Shanghai institute of Shanghai Institute of Microsystem and Information Technology on the intelligent nano-sensors.