Microcomputer based data acquisition for audio signals

AppliedAcousticsIS (1982)49-59

MICROCOMPUTER

BASED DATA ACQUISITION AUDIO SIGNALS

FOR

H. DAVIES, M. KEHAYASand D. J. MCNEILL

Department of Physics, Liverpool Polytechnic, Liverpool L3 3A F, Great Britain (Received: 24 March, 1981)

SUMMARY

The problem of interfacing a low cost microcomputer---the Commodore 3032--to external devices is reviewed. The essential features of a general purpose interface unit are described and an explanation is given, in general terms, of how this unit can be used to transfer digitised samples of audio signals to 3032 user memory for software processing. A specific system is described which allows sampling and storage at rates of up to 71 kbytesper second for a single channel and up to 43 kbytes × 2per second =[or two channels. More than two channels can be sampled at correspondingly lower rates. Some possible applications are indicated.

INTRODUCTION

Microcomputers are now widely accessible both in terms of cost and the technical resources required for their utilisation. This is most generally evident at the purely computational level, but just as significant for the acoustician is the potential r61e of the microcomputer as a central element in acoustic instrumentation systems. A recent paper, 1 for example, describes the use of the Commodore 3032 for the control of analogue devices and the sampling and subsequent processing of the timeaveraged outputs. Another paper 2 describes the use of the same machine for F F T computations on previously sampled impulsive signals. The latter application involves a two-stage process whereby the audio signal is sampled and stored by an external device and then entered into 3032 user memory. Direct sampling under microcomputer control does, however, have its advantages, and if this is extended to the simultaneous sampling of audio signals from two or more channels, inexpensive and flexible signal processing becomes a possibility. 49 Applied Acoustics 0003-6822(/82/0015-0049/$02-75 ~ Applied Science Publishers Ltd, England, 1982 Printed in Great Britain

50

H. DAVIES, M. K E H A Y A S , D. J. Mc'NEILL

The essential requirement is that of interfacing the microcomputer with analogue channels in such a way that the analogue data can be digitised and transferred to user memory at rates comparable with those required for audio signal sampling. The sampling theorem implies that if acoustic signals covering the frequency range up to, say, 15 kHz are to be sampled without loss of frequency information, sampling rates in excess of 30 kHz are necessary. A system capable of sampling at these rates has been constructed and is described in this paper. The main features of a general purpose interface unit for use with the C o m m o d o r e 3032 are first outlined. The way in which the unit can be used for fast data acquisition is explained in general terms, and a specific system is described. Applications of the system are briefly discussed.

GENERAL CONSIDERATIONS

Little needs to be said about the analogue to digital (A D) conversion process. The basic requirements are 8 bit conversion at rates compatible with meaningful sampling of audio signals, and this presents no problem. Commercial A - D converters are available which provide conversion rates which are entirely adequate for acoustic data sampling. The central issues concern the transfer of data into 3032 user memory and the rate at which transfer may be effected. The 3032 system provides two connection ports which are specifically intended for interfacing with external devices. These are the user port and the IEEE port. The ports connect to the processor data and address lines via peripheral interface adapter (PIA) chips. Such chips are capable of providing sixteen data lines which may be configured under software control to act either as inputs or outputs or as a mixture of both. In addition, up to four additional lines are available from each chip to provide a variety of control functions. In the 3032 system, the interface chips which service the two connection ports are partially dedicated to other functions. The IEEE port is intended principally for interfacing with peripheral input/output devices such as floppydisk drives and printers, and the user port shares interface chips with the cassette loader and various system diagnostic operations. As a consequence, the number of lines available for use with other external equipment is rather limited. The user port, for example, has only eight data lines and two control lines available for user application. In situations in which the 3032 is to be used for data acquisition and instrument control on a fairly substantial scale, the limited input/output and control options provided by the two connection ports impose a serious restriction on what is possible. Fortunately, these restrictions can be removed fairly readily by the provision of alternative PIA chips whose function is solely that of servicing external equipmenL. In the system described here advantage is taken of the fact that memory locations from $9000 to SBFFF in the 3032 system are available for R O M expansion and

MICROCOMPUTER BASED DATA ACQUISITION FOR AUDIO SIGNALS

51

constitute a vacant area in the m e m o r y m a p of the machine. Thus, additional peripheral chips may be accessed directly from the memory expansion connector of the machine which gives access to all the necessary data, address and control lines. In order to accomplish this, two steps are involved. Input/output in the 3032 system via PIA chips makes use of the so-called memory m a p p e d process in which the chips are accessed as a section of RAM. Clearly, therefore, it is necessary to modify the internal circuitry of the machine so that the region of the R O M expansion area in which the chips are to be located becomes accessible as R A M via the data lines on the memory expansion connector. An examination of the circuit diagrams for the 30323 shows that when addresses in the entire R O M area ($9000-$FFFF) are accessed, the memory expansion tristate data bus buffers are held in a write state and the data read directly onto the microprocessor data lines from whatever R O M chips may be in place. In order to open up the R O M expansion areas for access as RAM, it is necessary to disable the process which deactivates the tristate data bus buffers when addresses in the range $9000-$BFFF are selected. This is readily achieved by altering the links in jumper switches provided on the 3032 circuit board according to the connection options shown on the circuit diagrams. If this is done, the area $ C O O O - $ F F F F is still a R O M protected area but $900(~$BFFF becomes accessible as RAM, with the data bus buffers active. The area is no longer available for R O M expansion, however~ unless additional control circuitry is added to give partial protection. Once the R O M area has been opened up in this way, the second step involves the provision of external address decoding to provide appropriate signals for peripheral chip selection. The degree of decoding to be used depends upon the number of chips to be selected. In the system described here a general purpose interface unit has been constructed which contains four PIA chips and so the degree of decoding is not very great. The system is shown in block diagrammatical form in Fig. 1. The lower eight ( A ~ A 7 ) address lines are taken from the memory expansion connection to the location which will house the PIA chips. The upper four address lines ( A 8 - A I l) are decoded externally to provide four chip select lines and the final chip selection is rendered unique by the use of the line, SELA. Timing and read/ write control lines are connected directly to the chips from the expansion connector. In this way any one of the three types of PIA c h i p s - - M C S 6520, MCS 6522 or MCS 6 5 3 2 - - m a y be accessed. This system is not particularly economical of memory, with l K of address space dedicated to each chip, but, if necessary, more detailed decoding of the address lines could be used to provide more economical memory usage. The provision of four PIA chips in the interface unit makes it possible to access a variety of instruments and peripherals and extends considerably the usefulness of the 3032 as a controller and data acquisition device in acoustic experiments. Any one of the three types of interface chip could be used for fast access of acoustic data. Control lines are available to c o m m a n d an A - D converter to sample and digitise the signal, and data lines are available from which the data can be read

H. DAVIES,

M. KEHAYAS,

D. J. McNElLL

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MICROCOMPUTER BASED DATA ACQUISITION FOR AUDIO SIGNALS

53

and stored in memory for subsequent processing. It is customary in such operations to use a dual control line arrangement to handshake data transfers. In its simplest form this process uses one line, configured as an output from the machine, to initiate the A - D conversion and a second line, configured as an input, as a flag to indicate conversion is complete and valid data is present on the data lines. The data is then loaded and stored in memory and the cycle is repeated. This process assumes that the limiting factor in determining sample rates is the conversion time of the A - D converter and that the program steps involved in executing the process occupy negligible time. Clearly, if the fastest sampling rates are to be achieved (without recourse to special techniques such as direct memory access), a converter with a sufficiently small conversion time for the program execution to become the ratedetermining factor is necessary. If such a converter is used then the fastest sampling will be achieved by the shortest possible c o m m a n d and storage program execution time and by omitting the second handshake line, as discussed below.

FAST DATA ACQUISITION

Single~dual channel system A dual channel arrangement based on a 6520 chip occupying one location in the interface unit is shown in Fig. 2. For this chip only the first two lines o f A 0 ... A7 are needed for register selection. Briefly, the 6520 registers are configured during system initialisation so that, when the data register (DRA), which reflects the states of lines PA0. •. 7, is accessed by the 3032, a negative transition occurs on the CA2 line. This initiates a single simultaneous A - D conversion and the resulting data on PA0. • • 7 and P B 0 . . . 7 is read and transferred to memory. Another CA2 transition is automatically generated and a fresh set of data is made available. If only one channel is required, the data is applied to P A 0 . . • 7 and the data register (DRB) for P B 0 . . • 7 is not accessed. The 6520 is activated by setting CS 1 and CS2 high and CS3 low. RS0 and RS 1 then allow selection of any of six internal registers as shown in Table 1. Each bit in D D R A / B configures the corresponding line in DRA/B as input or output with '0' causing an input and '1' an output. Hence, during initialisation, D D R A and D D R B are both set to $00. The control line CA2 (CA1, CB1 and CB2 are held high to avoid complications arising from switching transients) is set to output by placing '1' in bit 5 of CRA, and a negative transition is produced on this line whenever DRA is read provided bits 3 and 4 of CRA are set to '1' and '0', respectively. Initialisation is therefore completed by writing $2C and $04 into CRA and CRB, respectively, as explained in Fig. 3. If the system is to operate successfully in the way described above, the conversion time of each A D converter must be less than the c o m m a n d and storage program execution time so that, whenever the 3032 is ready to read the 6520 data registers, data is available. The rate at which data can be sampled and stored is therefore

54

H. DAVIES,

M. KEHAYAS,

D. J. McNEILL

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MICROCOMPUTER BASED DATA ACQUISITION FOR AUDIO SIGNALS

55

TABLE 1 SELECTION OF THE 6520 REGISTERS

Register selected Control register A (CRA) Control register B (CRB) Data direction register A (DDRA) Data direction register B (DDRB) Data register A (DRA) Data register B (DRB)

RSO

RSI

Bit 2 of CRA

Bit 2 of CRB

1

0

$A001

l

l

$A003

0

0

0

l

0

0

0

I

0

Address

$A000 0

l

$A002 $A000

1

$A002

governed by software considerations. Program commands in BASIC cannot achieve the required rates and the system must be controlled by a machine code program. Figure 4 indicates the steps required for system initialisation and subsequent sampling and loading of 4 kbytes x 2 into blocks 2 and 3 of user memory. With this system, a m a x i m u m sampling rate of 43 kbytes × 2 per second (plus an extra 19 ps every 255 samples) is possible. Lower rates are easily achieved by simple modification of the program whilst a higher maximum rate of 71 kbytes per second is available if sampling is for a single channel only.

Multi-channel system The dual channel arrangement described above utilises two separate A - D converters. An alternative approach is to use a single converter combined with a multiplexing facility. This involves a marginal increase in complexity for a twochannel system, but if more than two channels are to be sampled it becomes the natural way of doing things. An arrangement capable of scanning up to sixteen channels is shown in Fig. 5. The 3032-6520 interconnections are exactly the same as in Fig. 2. After each conversion, the multiplexer enable output control increments the counter by one, and when the contents of the counter are equal to the required number of channels, as specified in digitised form on P B 0 . . . 3 , the c o m p a r a t o r output goes high. After the next conversion it goes low and this causes the monostable to produce a positive pulse which resets the counter ready for the next scan. During initialisation, bits 0. - - 3 of the DRB register must be loaded with the required number of channels and P B 0 . . . 3 set to output mode. The software requirements are otherwise basically as described in Fig. 3 except that if only one channel is to be sampled the ' G E T DRB' instruction is omitted; if two channels are to be sampled it is replaced by ' G E T D R A ' and, if more than two channels are required, extra instructions to access D R A are included. The m a x i m u m sampling rates shown in Table 2 have been obtained.

H. DAVIES,

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0 0

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0

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4

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D. J. McNEILL

ADI=$2000 AD2=$3000

I

ACCESS DATADIRECTION REGISTERS

CRA=$OO CRE:$O0

CONFIGUREDRA AND DRB AS I/P

DDRA=$OO DDRB=$OO

l

cRA=$2c

INITIALISE ADDRESS FOR DATASTORAGE

I

SEE FIGURE 3

CRB=$O4

GET DRA

INITIATECA2 PULSE

NO

231aS

OPERATION GET DRB

STORE ADI GET DRA STORE AD2

INITIATECA2 PULSE

I

23~S

INCREMENT I STORE ADDRESSES

PAGE NO ~

IiuS . . . . . . . . . . .

Fig. 4.

L

Flow chart of program operation for the dual channel system.

MCS 6520

7

t

PB~

a

PA~

CA2

~

DIGITAL COMPARATOR

A- D

11

MONOSTABLE

MUX

DIGITAL COUNTER

cH,~

Fig. 5. Multi-channel system for fast data acquisition.

DATA

INITIATE CONVERSION

ANALOGUE INPUTS

ENABLE OUTPUTCONTROL

O¢

MICROCOMPUTER BASED DATA ACQUISITION FOR AUDIO SIGNALS

59

TABLE 2 MULTI-CHANNELSAMPLINGRATES

Number of channels (n) Maximum rate (kbytes x n per second)

I

2

4

8

!6

71

43

24

13

7

APPLICATIONS

The usefulness of the data acquisition system described above depends on what can be done with the data once it is stored in user memory. Just as obviously, the basic constraints are those of limited user memory and program execution time. For many applications these constraints can be relaxed by the use of auxiliary storage and hardware processing devices, but a great deal can be done with the system as it stands. For example, an F F T algorithm can be executed for 1 kbyte of data from one channel with reasonable accuracy, using twelve bit arithmetic, in something like 20s 2. With the two channel system, cross-correlation computations become possible. 8 bit x 8 bit multiplication can be carried out in machine code in less than 130 #s on the 3032, and software is currently being developed to take advantage of this. A substantial reduction in processing time may, in addition, be achieved through the use of hardware arithmetic devices, and the general purpose interface unit is well suited to accommodate such devices. The multi-channel system suffers increasingly from sampling rate limitations as the number of channels increases (Table 2) and applications involving true audio signal sampling become correspondingly unrealistic. However, the feasibility of some limited form of acoustic telescopy seems worth exploring, 4 for, with the eightchannel system described here, sampling rates of up to 13 kbytes x 8 per second are still possible.

REFERENCES 1. N. W. HEAPand D. J. OLDHAM,Low cost computer controlled acoustic measuring systems, Applied Acoustics, 14 (1981), p.43. 2. D. J. McNEILL and G. W. Buggows, A microcomputer system for the analysis of impulse noise, Institute of Acoustics Meeting: Microprocessor Applications in Acoustics, University of Birmingham, 1980. 3. N. HAMPSHIRE, The PET revealed, Computabits Ltd., 1980. 4. J. BILUNGSLEY,Acoustic source location, present techniques and future implications for industrial noise control, Institute of Acoustics Autumn Conference, Windermere 1979.