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Microcomputer systems: A survey
MICROCOMPUTER
SYSTEMS:
RODNAY
A SURVEY
ZAKS
UNIVERSITE DE TECHNOLOGIE DE COMPIEGNE
ABSTRACT R e c e n t p r o g r e s s in metal-oxide s e m i c o n d u c t o r (MOS) l a r g e - s c a l e i n t e g r a t i o n (LSI) technology has y i e l d e d a new type of component, the m i c r o c o m p u t e r , o r " c o m p u t e r - o n - a - c h i p " . Its impact is a l r e a d y p r o v i n g to be s p e c t a c u l a r . The term of microprocessor has been heretofore reserved for microprogrammable processors. A new m e a n i n g h a s b e e n introduced, and is now widely a c cepted: the word " m i c r o p r o c e s s o r " d e s i g n a t e s h e r e an MOS-LSI p r o c e s s o r equipped with C P U - l i k e functions. " M i c r o " is then a r e f e r e n c e to the s i z e . This d o e s not r e f e r to the control philosophy u s e d in the p r o c e s s o r design: a m i c r o p r o c e s s o r is not n e c e s s a r i l y m i c r o p r o g r a m m e d . Other LSI p r o c e s s o r s , equipped with only m i n i m a l a r i t h m e t i c functions (4 to 8 functions) a r e d e s i g n a t e d as c a l c u l a t o r s .
The main c h a r a c t e r i s t i c of an LSI MOS "chip" (silicon s e m i c o n d u c t o r die) is to a c h i e v e v e r y high i n t e r c o n n e c t and logic d e n s i t y in a minute volume. R e c e n t m e m o r i e s i m p l e m e n t a 4K bit RAM in a single chip. The r e s u l t i n g advantages a r e e c o n o m y and p e r f o r m a n c e : low c o s t , s i z e , weight,and p o w e r c o n s u m p t i o n , high r e l i a b i l i t y , logic complexity, and speed. The p r i n c i p a l l i m i t a t i o n is in speed which is c u r r e n t l y l o w e r than b i p o l a r . M i c r o p r o c e s s o r s r e p r e s e n t a natural evolution f r o m c a l c u l a t o r c h i p s , and w e r e f i r s t introduced by Intel in 1971. Most m a j o r c o m p a n i e s a r e now in the p r o c e s s of producing m i c r o p r o c e s s o r s y s t e m s . A f t e r an o v e r v i e w of MOS LSI technology, p o s s i b l e m i c r o p r o c e s s o r o r g a n i z a t i o n s a r e analyzed. The main m i c r o p r o c e s s o r s c u r r e n t l y available, or due to be introduced, a r e p r e s e n t e d . Finally, a p p l i c a t i o n s of m i c r o c o m p u t e r s y s t e m s a r e s u r v e y e d , and t h e i r impact is evaluated.
MOS LSI TECHNOLOGY HISTORICAL EVOLUTION The concept of the MOS field-effect t r a n s i s t o r (FET) can be t r a c e d a s e a r l y a s the 1930's, p r i o r to the bipolar t r a n s i s t o r . The difficulties of the m a n u f a c t u r i n g p r o c e s s h a m p e r e d d e v e l o p m e n t e f f o r t s . Development of the silicon p l a n a r p r o c e s s in the e a r l y 1960's made it p o s s i ble to s t a r t developing MOS F E T ' s . The f i r s t s i m p l e i n t e g r a t e d c i r c u i t s (IC's) w e r e only p r o d u c e d in 1964, ten y e a r s a f t e r production of the conventional silicon t r a n s i s t o r s . It was until 1967 when MOS I C ' s s t a r t e d being p r o d u c e d by a sufficiently well c o n t r o l l e d p r o c e s s to p r o d u c e r e a s o n a b l e y i e l d s . SEVERAL TECHNOLOGIES MOS m a n u f a c t u r i n g t e c h n o l o g i e s can be b r i e f l y s u m m a r i z e d as follows: i. p - c h a n n e l : h o l e s a r e the v e h i c l e of c u r r e n t flow. It is inexpensive, e a s y to m a n u f a c t u r e . ttigh yield, high t h r e s h o l d voltage, r e l a tively slow, r e l i a b l e , l i m i t e d LSI packing d e n s i t y . Typical a c c e s s t i m e for a p channel m e m o r y is 300 ns. 2. n - c h a n n e l : e l e c t r o n s p r o v i d e the v e h i c l e for c u r r e n t flow. C o m p l e x c o n t r o l of m a n u f a c t u r i n g p r o c e s s m a k e s this v e r y r e c e n t technology a difficult one. Low t h r e s h o l d and o p e r a t i n g voltage. Due to higher e l e c t r o n mobility, n - c h a n n e l is typically two to t h r e e t i m e s f a s t e r than p - c h a n n e l , t t i g h e r packing d e n s i t i e s have led to the r e c e n t introduction of 4K RAMs and to s e v e r a l a n n o u n c e m e n t s of m i c r o p r o c e s s o r s , to be introduced soon. 3. CMOS : f r o m a m a n u f a c t u r i n g standpoint, it c o m b i n e s the n - and p - c h a n n e l p r o c e s s e s : e x p e n s i v e , low c a p a c i t y But f a s t e r than
10
4. SOS
5. Special
p - c h a n n e l and c h e a p e r t h a n b i p o l a r . V e r y high n o i s e i m m u n i t y and i n s e n s i t i v i t y to p o w e r supply voltage. However, l e s s d e n s e t h a n n-MOS and difficult m a n u f a c t u r i n g . S i l i c o n - o n - S a p p h i r e (SOS): t h i s new t e c h n o logy p r o v i d e s b e s t s p e e d p r o s p e c t s with r e l a t i v e l y high packing density. Special P r o c e s s F a c t o r s : Ion I m p l a n t a t i o n p r o v i d e s p r e c i s e i m p u r i t y and doping c o n t r o l . R e l a t i v e l y e x p e n s i v e , but r e d u c e s t h r e s h o l d and e l i m i n a t e s o v e r l a p c a p a c i tance. M e t a l - G a t e (Aluminum): i n t r o d u c e s o v e r l a p c a p a c i t a n c e , r e s u l t i n g in l o w e r speed. S i l i c o n - G a t e : r e d u c e s t h r e s h o l d and c a p a c i tance.
THE ADVANTAGES OF LSI LSI d e v i c e s offer two b a s i c a d v a n t a g e s : economy and s y s t e m p e r f o r m a n c e . In p a r t i c u l a r , LSI r e q u i r e s fewer p a c k a g e s , l o w e r p o w e r supply, l o w e r cooling r e q u i r e m e n t s . A s a r e s u l t , fewer PC c a r d s and conn e c t o r s a r e needed, h i g h e r p e r f o r m a n c e is obtained at the s a m e c o s t , b e t t e r r e l i a b i l i t y and m a i n t a i n a b i l i t y a r e achieved. T h e m a j o r l i m i t a t i o n s of LSI a r e e s s e n t i a l l y t h r e e : 1. e c o n o m i c : d e v e l o p m e n t cost, and cost of modifying a chip. 2. t e c h n o l o g i c a l : s l o w e r speed t h a n b i p o l a r . 3. m a n a g e m e n t : long l e a d - t i m e and s t a n d a r d v e r s u s c u s t o m logic. T h e m a j o r i m p a c t of MOS LSI is in r e d u c i n g t h e c o s t p e r - l o g i c - f u n c t i o n so d r a s t i c a l l y t h a t it is no l o n g e r a s i g n i f i c a n t p a r a m e t e r . Computing and logic functions b e c o m e e s s e n t i a l l y f r e e c o m p a r e d to o t h e r c o s t s . T h e c o s t of the whole m i c r o p r o c e s s o r i t s e l f is t y p i c a l l y a s m a l l f r a c t i o n of the total s y s t e m c o s t . THE LSI MICROPROCESSOR MOS b e c a m e a r e a l i t y in 1967/1968. T h e gate count p e r chip s t a r t e d to i n c r e a s e steadily: s m a l l - s c a l e i n t e g r a t i o n (SSI), m e d i u m - s c a l e i n t e g r a t i o n (MSI) (over 2000 t r a n s i s t o r s p e r chip), LSI {over 5000). T h e b a s i c p r o b l e m in LSI technology was to d e s i g n s t a n d a r d p r o d u c t s . In fact, s t a n d a r d i z a t i o n s t a r t e d only two y e a r s ago. F i r s t with r e c e i v e r - t r a n s m i t t e r s (UART's), t h e n c a l c u l a t o r c h i p s (in mid*72), l a r g e a r r a y s , and now m i c r o p r o c e s s o r s . At the s a m e t i m e , a l a r g e n u m b e r of g e n e r a l i z e d a r r a y s a r e b e i n g i n t r o duced: m e m o r i e s , sync g e n e r a t o r s , digital v o l t m e t e r s . T h e m a j o r i t y of such m i c r o p r o c e s s o r s is p r o b a b l y s t i l l c u s t o m - d e s i g n e d . The i n c r e a s i n g a v a i l a b i l i t y of s t a n d a r d m i c r o p r o c e s s o r s m a y r e v e r s e t h i s t r e n d in t h e d o m a i n of p r o c e s s o r c h i p s .
MICROCOMPUTER ARCHITECTURES MICROPROGRAMMED OR HARDWIRED It h a s b e e n explained above that a m i c r o p r o c e s s o r need not b e m i e r o p r o g r a m m e d . T h e c o n t r o l s e c t i o n of a m i c r o p r o c e s s o r m a y b e e i t h e r h a r d w i r e d (low cost) or m i c r o p r o g r a m m e d (flexibility). Both o r g a n i z a t i o n s have m e r i t s which m a k e t h e m v a l u a b l e for specific applications. H i s t o r i c a l l y , m i c r o p r o c e s s o r s w e r e introduced a s m o d ified c a l c u l a t o r d e s i g n s , i . e . , w e r e 4 bit wide and had a h a r d w i r e d i n s t r u c t i o n set. A c o m p e t i n g philosophy a p p e a r e d with 2 - c h i p p r o c e s s o r s : they u s e a RALU and a CROM. The RALU is a r e g i s t e r equipped a r i t h m e t i c logical unit (ALU). The CROM is a r e a d only m e m o r y (ROM) for RALU c o n t r o l . The chip count m a y be i n c r e a s e d a s one CROM c o n t r o l s s e v e r a l R A L U ' s o r s e v e r a l CROM's c o n t r o l one RALU. The flexibility gained with a p r o g r a m m a b l e c o n t r o l chip is b e n e f i c i a l for expanded o r v a r y i n g i n s t r u c t i o n s e t s a s well a s m i c r o c o d e d c o n t r o l a l g o r i t h m s . T h i s m i e r o p r o g r a m m i n g facility m a y p r e s e n t d i s a d v a n t a g e s : i n c r e a s e d e n g i n e e r i n g , d e v e l o p m e n t t i m e for i n s t r u c t i o n set, cost penalty. THE BIT WIDTH T h e f i r s t m i c r o p r o c e s s o r s , d e r i v e d f r o m the c a l c u l a t o r s , w e r e 4 - b i t wide. With i m p r o v i n g technology, 4, 8 and 1 2 - b i t m i c r o p r o c e s s o r s h a v e b e e n r e a l i z e d . The q u a s i - u n i v e r s a l width is now 8 bits, a n o p t i m u m in view of c u r r e n t pin count l i m i t a t i o n s (40 pins) and of c o m p o nent s t a n d a r d i z a t i o n . Often, ALU chips m a y b e used in p a r a l l e l , like m e m o r y chips, r e s u l t i n g in m o d u l a r 12, 16 or 2 4 - b i t s y s t e m s b a s e d on 4 b i t or 8 bit chips. THE CHIP COUNT Although a m i c r o p r o c e s s o r r e s i d e s on a s m a l l n u m b e r of c h i p s (one to t h r e e ) , the c o m p l e t e m i c r o c o m p u t e r s y s t e m r e q u i r e s m a n y m o r e . Typically, a c o m p l e t e s y s t e m will r e q u i r e 14 to 50 I C ' s , with c l o c k s and t i m i n g , c o n t r o l logic, plus p e r i p h e r a l i n t e r f a c e I C ' s (5 to 30 I C ' s ) . T h e total n u m b e r of I C ' s is 19 to 80. New a r c h i t e c t u r e s s e e k to m i n i m i z e the chip count by i n c o r p o r a t i n g m o r e functions within a chip: c o n t r o l , timing, buffering. THE INTERNAL REGISTERS A s p a c k i n g d e n s i t i e s h a v e i n c r e a s e d , it h a s b e c o m e p o s s i b l e to supply an i n c r e a s i n g n u m b e r of i n t e r n a l r e g i s t e r s . F r o m the u s e r ' s standpoint the two e s s e n t i a l functions a r e working r e g i s t e r s and s u b r o u t i n e a d d r e s s s t a c k . Typically, a m i c r o p r o c e s s o r will now include 8 to 16 i n t e r n a l working r e g i s t e r s (8 bit). T h e cost of p r o v i d i n g m o r e r e g i s t e r s is not so m u c h a h a r d w a r e
11 c o s t a s a l o s s of a d d r e s s b i t s i n t e r n a l l y , for r e g i s t e r selection. It will a l s o include a facility for subroutine n e s t i n g , the stack. Two p h i l o s o p h i e s c o m p e t e : an i n t e r n a l s e t of h a r d w a r e r e g i s t e r s , o r a p o i n t e r to m e m o r y . An i n t e r n a l set of 8 to 16 r e g i s t e r s o f f e r s a s p e e d advantage in stacking o p e r a t i o n s (fast i n t e r r u p t r e s p o n s e ) . The d i s a d v a n t a g e s a r e a l o s s of flexibility (the n u m b e r of l e v e l s i s l i m i t e d to t h e n u m b e r of r e g i s t e r s ) and a significant i n c r e a s e in c o m p l e x i t y . The s e c o n d a p p r o a c h u s e s a p r o g r a m c o u n t e r and a s t a c k p o i n t e r (plus p e r h a p s a s t a c k b a s e ) . It allows an u n l i m i t e d n u m b e r of r e t u r n a d d r e s s n e s t i n g s , but is s l o w e r than the i n t e r n a l r e g i s t e r a p p r o a c h . The gain in flexibility t e n d s to f a v o r i z e t h i s d e s i g n philosophy in the most recent microprocessors. EXISTING MICROPROCESSORS INTEL : MCS 8008 In addition to its f o u r - b i t MCS-4 m i c r o p r o c e s s o r , Intel o f f e r s an e i g h t - b i t p r o c e s s o r , the MCS-8. Its c o m p l e x i t y is equivalent to 125 TTL p a c k s . The m i c r o p r o c e s s o r chip i n c o r p o r a t e s : 1. an e i g h t - b i t p a r a l l e l a r i t h m e t i c unit 2. s e v e n e i g h t - b i t data r e g i s t e r s 3. eight f o r t e e n - b i t r e g i s t e r s (stack) for subroutine nesting. 4. i n s t r u c t i o n decoding and c o n t r o l logic (this is a h a r d w i r e d p r o c e s s o r ) . I n t e r r u p t capability. 48 i n s t r u c t i o n s . Typical m a c r o - i n s t r u c t i o n t i m e is 20 u s for the 8008, 12,5 us for the 8008-1. M e m o r y is ROM, PROM, RAM o r shift r e g i s t e r s , up to 16 K by 8 - b i t w o r d s . A d d r e s s i n g i s implicit: a, r e g i s t e r m u s t be loaded. T h i s m i c r o p r o c e s s o r u s e s an 18-pin p a c k a g e . It o f f e r s e x t e n s i v e s o f t w a r e and prototyping s u p p o r t . INTEL 8080 T h i s i s an n - c h a n n e l silicon-gate, 40-pin m i c r o p r o c e s s o r , due to be introduced s h o r t l y . Its d e s i g n is analogous to the 8008. The CPU contains: 1. 8 - b i t p a r a l l e l b i n a r y ALU 2. s e v e n 8 - b i t data r e g i s t e r s four t e s t a b l e flag b i t s 3. h a r d w i r e d c o n t r o l . E x t e r n a l l y TTL compatible 4. one 16-bit s t a c k p o i n t e r and a 16-bit program counter. Non m e m o r y r e f e r e n c i n g i n s t r u c t i o n s a r c executed in 2 m i c r o s e c o n d s (2MHz clock). In this p r o c e s s o r , the a d d r e s s is 16-bit wide, and the s t a c k is in e x t e r n a l m e m o r y (unlimited). The m i c r o -
p r o c e s s o r only c o n t a i n s a s t a c k p o i n t e r . Upon i n t e r ruption, t h e p r o g r a m - c o u n t e r plus the data r e g i s t e r s , the accumulator, and the flags, can be s t a c k e d . A n o t h e r d i f f e r e n c e l i e s in the b u s s i n g : the 8080 d o e s not t i m e - m u l t i p l e x data and a d d r e s s o v e r a single bus anym o r e . The 16 b i t - a d d r e s s p r o v i d e s a 64 K-8 bit m e m o r y a d d r e s s i n g capability without an e x t e r n a l m e m o r y register. The 74 i n s t r u c t i o n s include the 48 i n s t r u c t i o n s of the 8008 (compatibility). The packaging is 40-pin DIP. NATIONAL SEMICONDUCTOR : IMP 16 C National S e m i c o n d u c t o r (NS) u s e s a building block a p p r o a c h for its s y s t e m s , the IMP 16 'C ~(~16h i t s ) and the IMP 8 C (8 b i t s ) . They a r e built around m:icrop r o g r a m m a b l e f o u r - b i t p r o c e s s o r m o d u l e s . The IMP 16 C u s e s four R A L U ' s and a CROM to f o r m a 16-bit s y s t e m . Each RALU has: 1. s e v e n i n t e r n a l r e g i s t e r s : four g e n e r a l p u r p o s e , including one a s index plus t h r e e for the m i c r o c o d e (PC, MAR, MDR) 2. 16-word s t a c k (4 bits) 3. 4 status flags 4. 4 - b i t wide ALU (ADD, AND, OR, EOR and shift). The CROM p r o v i d e s the c o n t r o l logic for up to eight R A L U ' s . It s t o r e s the m i c r o p r o g r a m and o f f e r s a s t a n d a r d i n s t r u c t i o n set of 43 i n s t r u c t i o n s . The ROM s t o r e s i00 23-bit m i c r o i n s t r u c t i o n s . A typical m a c r o i n s t r u c t i o n r e q u i r e s 7 us. The clock c y c l e of 1.5 us is divided in four p h a s e s . The c o m m a n d s s p e c i f i e d b e t w e e n the RALU and the CROM a r e : 1. A-source register 2. B-source register 3. ALU o p e r a t i o n s e l e c t 4. R-address register. The pin count is 24 for RALU and CROM. FAIRCHILD : P P S 25 T h i s is a f o u r - b i t p r o c e s s o r intended for s c i e n t i f i c c a l c u l a t i o n s . It b e l o n g s to the family of p r o c e s s o r s d i r e c t l y d e r i v e d f r o m c a l c u l a t o r c h i p s . It u s e s a m u l t i chip approach: a 3805 a r i t h m e t i c unit, a 3806 p r o g-rammed function and timing unit, a 3810 ROM for m i c r o p r o g r a m s , a 3808 for m e m o r y . Its o r g a n i z a t i o n is 25-digit s e r i a l , 4-bit p a r a l l e l , with a 62.5 us w o r d t i m e , 2.5 us bit t i m e (addition of two 25 digit n u m b e r s in 62.5 us, multiplication in 50 m s ) . Each ROM s t o r e s 256 m i c r o i n s t r u c t i o n s . Up to 26 ROM
12 c h i p s may be u s e d in one s y s t e m . The m e m o r y chip s t o r e s d i g i t s , each 4 b i t s b i n a r y - c o d e d (BCD). T h e r e a r e 3 25-digit r e g i s t e r s p e r chip. Its c h a r a c t e r i s t i c s a r e : one 25-digit r e g i s t e r 4 b i t s p e r digit BCD s e r i a l / p a r a l l e l : 25 digit s e r i a l , 4 bit p a r a l l e l 95 i n s t r u c t i o n s bit t i m e is 2.5 us, word t i m e is 62.5 us (25 digits + 25 digits) 4 level subroutine s t a c k external interrupt 1 to 7 25-digit m e m o r y r e g i s t e r s 1 to 26 ROMS : 256 x 1 2 b i t s . TOSHIBA TLCS 12
T o s h i b a ' s m i c r o p r o c e s s o r is 12-bit wide and i n c o r p o r a t e s the c o n t r o l ROM within the m i c r o p r o c e s s o r chip.
GENERAL AUTOMATION : LSI-12/16
The f o r m e r SPC-12 p r o c e s s o r b o a r d is r e p l a c e d by a single chip. It u s e s LSI, n - c h a n n e l SOS technology. It o f f e r s h i g h - s p e e d of n - c h a n n e l SOS and high density (2000 g a t e s or 4000 to 5000 t r a n s i s t o r s ) . The b a s i c b o a r d a c c o m o d a t e s the m i c r o p r o c e s s o r sysLem with up to 2 K of m e m o r y , o p e r a t o r c o n s o l e and s y s t e m o p e r ation f e a t u r e s . It f e a t u r e s c o m p l e x m e m o r y a d d r e s s i n g of up to 4 K w o r d s (12 bit a d d r e s s ) . F o r m i c r o p r o g r a m m i n g flexibility, t h i s s y s t e m u s e s a "ROM p a t c h " technique with two ROM b o a r d s • One holds 32 p a t c h a d d r e s s e s , the o t h e r holds the 32 p a t c h e s . The s y s t e m is s t r u c t u r e d in 12 b i t - p a r a l l e l for a d d r e s s e s , 8 - b i t p a r a l l e l for data. F i f t y - t w o b a s i c i n s t r u c t i o n s a r e o f f e r e d . B a s i c i n s t r u c t i o n c y c l e is 2.6 us.
FORTHCOMING MICROPROCESSORS
Its main c h a r a c t e r i s t i c s a r e : 12 bit ALU with f a s t - c a r r y logic 5 working r e g i s t e r s • 8 12-bit g e n e r a l - p u r p o s e r e g i s t e r s (7 available to the u s e r , plus p r o g r a m s t a t u s word).
AMERICAN MICROSYSTEMS INC (AMI) : 7300
A minimum system configuration necessitates the microprocessor, three memories, and one memory control unit.
This m i c r o p r o g r a m m e d 2-chip p r o c e s s o r is p a r a l l e l , 8-bit. It u s e s a RALU plus CROM philosophy. Both c h i p s a r e p - c h a n n e l , silicon-gate, ion-implanted. The RALU c o n t a i n s : 1. ALU with A and B - s o u r c e r e g i s t e r s , status register, result register 2. t h i r t y - t w o g e n e r a l r e g i s t e r s which can be used a s e i t h e r one or two s t a c k s and or one o r two register sets 3. s e v e n - a d d r e s s stack.
M i c r o i n s t r u c t i o n s a r e 29 b i t s wide. The s y s t e m a c c o m o d a t e s up to 128 m i c r o i n s t r u c t i o n s . The packaging is 42-pin DIP, logic d e n s i t y is c l a i m e d to be equivalent to 11000 p - c h a n n e l MOS t r a n s i s t o r s ( s i l i c o n - g a t e technology). ROCKWELL MICROELECTRONICS : 10660 T h i s is a f a s t f o u r - b i t p a r a l l e l p r o c e s s o r (5 us) with 50 w i r e d i n s t r u c t i o n s . It u s e s ROMs, RAMs, and 10 c h i p s . They a r e 4 2 - l e a d flat p a c k s .
The s y s t e m is d e s c r i b e d for its a r c h i t e c t u r a l i n t e r e s t . It has b e e n announced r e c e n t l y that it will not be implemented.
The control ROM is called M i c r o i n s t r u c t i o n ROM or MIR. It is a 512-word by 22-bit m a s k p r o g r a m m a b l e ROM. The i n s t r u c t i o n c y c l e is 4 us. T h e r e is a f o u r level i n t e r r u p t s y s t e m . SIGNETICS
Subroutine n e s t i n g is p e r f o r m e d in RAM. The a d d r e s s bus is 12-bit wide. Two d e c i m a l digits a r e added in 30 us. COMPUTER AUTOMATION : NAKED MINI C o m p u t e r Automation developed a s e v e n - c h i p MOS/LSI p r o c e s s o r to build a b a s i c 16 b i t - s y s t e m . It u s e s four R A L U ' s and t h r e e c o n t r o l - c h i p s with P r o g r a m m a b l e Logic A r r a y s (PLA's) r a t h e r than ROMs. All b u s s i n g is 16-bit wide. The newly developed LSI-2 p r o c e s s o r r e p l a c e s the LSI-1, is faster, and c o m p a t i b l e .
Signetics p l a n s the introduction of an 8 - b i t fixed ins t r u c t i o n p r o c e s s o r with e x t e n s i v e a d d r e s s i n g c a p a b i l i t i e s : d i r e c t , i n d i r e c t , r e l a t i v e , absolute, i m m e d i a t e . It will be an n - c h a n n e l silicon*gate p r o c e s s o r . I n s t r u c tion t i m e is 5 to 10 us. The ALU contains 4 g e n e r a l r e g i s t e r s , an e i g h t - r e g i s t e r stack, and i m p l e m e n t s 75 i n s t r u c t i o n s . The a d d r e s s bus is 15-bit wide. ins t r u c t i o n s a r e s t r u c t u r e d in a 6 - b i t opcode and 2-bit r e g i s t e r p o i n t e r . It u s e s a 40-pin package. Introduction planned for 1974.
13 Programmed games.
OTHERS Monolithic M e m o r i e s and Raytheon have announced a b i p o l a r m i c r o p r o c e s s o r . R a y t h e o n ' s is a s e v e n - c h i p s y s t e m , with 3 CROMs and 4 R A L U s to p r o d u c e a 16 bit s y s t e m . Due to the b i p o l a r technology, the e x p e c t e d s p e e d is 200 ns. S i e m e n s h a s announced d e v e l o p m e n t p l a n s for an MOS n - c h a n n e l 8 b i t - m i c r o p r o c e s s o r analogous to the Intel 8080. T e x a s I n s t r u m e n t s , A m e r i c a n M i c r o s y s t e m s , and M i c r o s y s t e m s I n t e r n a t i o n a l a r e said to be c o n s i d e r i n g l i c e n s i n g a g r e e m e n t s for s e c o n d - s o u r c i n g the 808 0. Inselek has announced plans for a CMOS, SOS microprocessor with a 300 ns cycle time.
RCA has announced a 2 - c h i p CMOS 8 bit m i c r o p r o c e s s o r using a 16 x 16 s c r a t c h p a d for m e m o r y accesses.
W e s t e r n Digital and other m a n u f a c t u r e r s a r e a n nouncing p l a n s for new m i c r o p r o c e s s o r s . In view of the long l e a d - t i m e for d e v e l o p m e n t , it is likely that only a few m o r e will be effectively introduced this y e a r .
THE IMPACT OF MICROCOMPUTERS The impact of the m i c r o p r o c e s s o r can be e x p e c t e d to be m o r e significant than the mini revolution a few y e a r s ago. The r a n g e of m i c r o c o m p u t e r s y s t e m s extends throughout a wide s p e c t r u m of p e r f o r m a n c e and c o s t , f r o m the c a l c u l a t o r at the low end, to the m i n i c o m p u t e r at the high end. Typical execution t i m e s for m i c r o c o m p u t e r s a r e still 2 to 10 t i m e s s l o w e r than t h o s e for m i n i s , but a r e c o n s t a n t l y shrinking. M i c r o p r o c e s s o r s have evolved a s s t a n d a r d OEM p r o d u c t s , and c a t e r exc l u s i v e l y to the OEM u s e r s , while m i n i c o m p u t e r s u s u ally p r o v i d e e x t e n s i v e support g e a r e d to the e n d - u s e r . T h e i r m a j o r impact is felt on e c o n o m i c a l and " s m a r t " OEM digital p r o d u c t s . As MOS LSI c o s t s keep d e c r e a s i n g , the n u m b e r of m i c r o c o m p u t e r s should exceed by far the n u m b e r of any o t h e r type of c o m p u t e r being p r o d u c e d .
RE FERENC ES 1.
C . G . Bell and al, "The A r c h i t e c t u r e and Applic a t i o n s of C o m p u t e r Modules: A Set of C o m p o n e n t s for Digital Design", COMPCON 73, M a r c h 1973, pp. 177-180.
GENERAL RULES
2.
O r i g i n a l l y intended for d e s k - c a l c u l a t o r usage, m i c r o c o m p u t e r s y s t e m s a r e now being u s e d in an i n c r e a s i n g r a n g e of a p p l i c a t i o n s .
S. Davis, "A F r e s h View of M i n i - and M i c r o c o m p u t e r s " , C o m p u t e r Design, May 1974, pp. 67-79.
3.
C . C . F o s t e r , "A View of C o m p u t e r A r c h i t e c t u r e " , CACM J u l y 1972, Vol. 15, n u m b e r 7, pp. 557-565
4.
S. F u l l e r and D. Siewiorek, "Some O b s e r v a t i o n s on S e m i c o n d u c t o r Technology and the A r c h i t e c t u r e of L a r g e Digital Modules", C o m p u t e r , Oct 1973, pp. 15-19
5.
M . E . Hoff, J r , "Applications for M i c r o c o m p u t e r s in I n s t r u m e n t a t i o n " , 1973 IEEE I n t e r c o m
6.
R. Holt, M. L e m a s , " C u r r e n t M i c r o c o m p u t e r A r c h i t e c t u r e " , C o m p u t e r Design, F e b r u a r y 1974, pp. 65-73.
7.
G. Lapidus, "MOS/LSI L a u n c h e s the Low Cost P r o c e s s o r " , S p e c t r u m , Nov 1972, pp. 33-40.
8.
G. Reyling, J r , "LSI Building Blacks for P a r a l l e l Digital P r o c e s s o r s " , 1~,73 IEEE I n t e r c o n .
9.
T. Tarui, and al, " T w e l v e - b i t m i c r o p r o c e s s o r nears minicomputer's performance level", E l e c t r o n i c s , M a r c h 1974, pp. 111-116.
10.
J . W e i s b e c k e r , "A Simplified M i c r o c o m p u t e r A r c h i t e c t u r e " , C o m p u t e r , M a r c h 1974, pp. 41-47.
11.
W. W i c k e s , "A Compatible MOS/LSI M i c r o p r o c e s s o r Device F a m i l y " , C o m p u t e r Design, July 73, pp. 75-81.
APPLICATIONS OF MICROCOMPUTERS
The g e n e r a l r u l e s for using a m i c r o p r o c e s s o r instead of a h a r d w i r e d d e v i c e can be s u m m a r i z e d as follows: 1. sequential digital application r e q u i r i n g o v e r 50 hardwired IC's 2. n o n - t r i v i a l p r o g r a m s e q u e n c e 3. logical or a r i t h m e t i c r e q u i r e m e n t 4. no s u p e r - s p e e d , although multiple m i c r o p r o c e s s o r s m a y be used. APPLICATIONS M i c r o p r o c e s s o r s a r e u s e d in the following applications: Small b u s i n e s s m a c h i n e s , including c a l c u l a t o r s Point of Sale T e r m i n a l s (cash r e g i s t e r s , c r e d i t card verifiers) Data C o m m u n i c a t i o n ( c o m m u n i c a t i o n s p r e p r o c e s s o r , s m a r t t e r m i n a l , t e s t equipment, data c o n c e n t r a t o r , m e s s a g e switching, signal processor) P e r i p h e r a l s C o n t r o l l e r s {card r e a d e r , floppy d i s c , c a s s e t t e tape unit, line p r i n t e r s , CRT) G e n e r a l Control (machine tool, p r o c e s s c o n t r o l , e n v i r o n m e n t c o n t r o l for building, t r a f f i c c o n t r o l , e l e v a t o r c o n t r o l , a p p l i a n c e s , automobiles) Data A c q u i s i t i o n S y s t e m s I n s t r u m e n t a t i o n and device t e s t e r
SYSTEMS:
RODNAY
A SURVEY
ZAKS
UNIVERSITE DE TECHNOLOGIE DE COMPIEGNE
ABSTRACT R e c e n t p r o g r e s s in metal-oxide s e m i c o n d u c t o r (MOS) l a r g e - s c a l e i n t e g r a t i o n (LSI) technology has y i e l d e d a new type of component, the m i c r o c o m p u t e r , o r " c o m p u t e r - o n - a - c h i p " . Its impact is a l r e a d y p r o v i n g to be s p e c t a c u l a r . The term of microprocessor has been heretofore reserved for microprogrammable processors. A new m e a n i n g h a s b e e n introduced, and is now widely a c cepted: the word " m i c r o p r o c e s s o r " d e s i g n a t e s h e r e an MOS-LSI p r o c e s s o r equipped with C P U - l i k e functions. " M i c r o " is then a r e f e r e n c e to the s i z e . This d o e s not r e f e r to the control philosophy u s e d in the p r o c e s s o r design: a m i c r o p r o c e s s o r is not n e c e s s a r i l y m i c r o p r o g r a m m e d . Other LSI p r o c e s s o r s , equipped with only m i n i m a l a r i t h m e t i c functions (4 to 8 functions) a r e d e s i g n a t e d as c a l c u l a t o r s .
The main c h a r a c t e r i s t i c of an LSI MOS "chip" (silicon s e m i c o n d u c t o r die) is to a c h i e v e v e r y high i n t e r c o n n e c t and logic d e n s i t y in a minute volume. R e c e n t m e m o r i e s i m p l e m e n t a 4K bit RAM in a single chip. The r e s u l t i n g advantages a r e e c o n o m y and p e r f o r m a n c e : low c o s t , s i z e , weight,and p o w e r c o n s u m p t i o n , high r e l i a b i l i t y , logic complexity, and speed. The p r i n c i p a l l i m i t a t i o n is in speed which is c u r r e n t l y l o w e r than b i p o l a r . M i c r o p r o c e s s o r s r e p r e s e n t a natural evolution f r o m c a l c u l a t o r c h i p s , and w e r e f i r s t introduced by Intel in 1971. Most m a j o r c o m p a n i e s a r e now in the p r o c e s s of producing m i c r o p r o c e s s o r s y s t e m s . A f t e r an o v e r v i e w of MOS LSI technology, p o s s i b l e m i c r o p r o c e s s o r o r g a n i z a t i o n s a r e analyzed. The main m i c r o p r o c e s s o r s c u r r e n t l y available, or due to be introduced, a r e p r e s e n t e d . Finally, a p p l i c a t i o n s of m i c r o c o m p u t e r s y s t e m s a r e s u r v e y e d , and t h e i r impact is evaluated.
MOS LSI TECHNOLOGY HISTORICAL EVOLUTION The concept of the MOS field-effect t r a n s i s t o r (FET) can be t r a c e d a s e a r l y a s the 1930's, p r i o r to the bipolar t r a n s i s t o r . The difficulties of the m a n u f a c t u r i n g p r o c e s s h a m p e r e d d e v e l o p m e n t e f f o r t s . Development of the silicon p l a n a r p r o c e s s in the e a r l y 1960's made it p o s s i ble to s t a r t developing MOS F E T ' s . The f i r s t s i m p l e i n t e g r a t e d c i r c u i t s (IC's) w e r e only p r o d u c e d in 1964, ten y e a r s a f t e r production of the conventional silicon t r a n s i s t o r s . It was until 1967 when MOS I C ' s s t a r t e d being p r o d u c e d by a sufficiently well c o n t r o l l e d p r o c e s s to p r o d u c e r e a s o n a b l e y i e l d s . SEVERAL TECHNOLOGIES MOS m a n u f a c t u r i n g t e c h n o l o g i e s can be b r i e f l y s u m m a r i z e d as follows: i. p - c h a n n e l : h o l e s a r e the v e h i c l e of c u r r e n t flow. It is inexpensive, e a s y to m a n u f a c t u r e . ttigh yield, high t h r e s h o l d voltage, r e l a tively slow, r e l i a b l e , l i m i t e d LSI packing d e n s i t y . Typical a c c e s s t i m e for a p channel m e m o r y is 300 ns. 2. n - c h a n n e l : e l e c t r o n s p r o v i d e the v e h i c l e for c u r r e n t flow. C o m p l e x c o n t r o l of m a n u f a c t u r i n g p r o c e s s m a k e s this v e r y r e c e n t technology a difficult one. Low t h r e s h o l d and o p e r a t i n g voltage. Due to higher e l e c t r o n mobility, n - c h a n n e l is typically two to t h r e e t i m e s f a s t e r than p - c h a n n e l , t t i g h e r packing d e n s i t i e s have led to the r e c e n t introduction of 4K RAMs and to s e v e r a l a n n o u n c e m e n t s of m i c r o p r o c e s s o r s , to be introduced soon. 3. CMOS : f r o m a m a n u f a c t u r i n g standpoint, it c o m b i n e s the n - and p - c h a n n e l p r o c e s s e s : e x p e n s i v e , low c a p a c i t y But f a s t e r than
10
4. SOS
5. Special
p - c h a n n e l and c h e a p e r t h a n b i p o l a r . V e r y high n o i s e i m m u n i t y and i n s e n s i t i v i t y to p o w e r supply voltage. However, l e s s d e n s e t h a n n-MOS and difficult m a n u f a c t u r i n g . S i l i c o n - o n - S a p p h i r e (SOS): t h i s new t e c h n o logy p r o v i d e s b e s t s p e e d p r o s p e c t s with r e l a t i v e l y high packing density. Special P r o c e s s F a c t o r s : Ion I m p l a n t a t i o n p r o v i d e s p r e c i s e i m p u r i t y and doping c o n t r o l . R e l a t i v e l y e x p e n s i v e , but r e d u c e s t h r e s h o l d and e l i m i n a t e s o v e r l a p c a p a c i tance. M e t a l - G a t e (Aluminum): i n t r o d u c e s o v e r l a p c a p a c i t a n c e , r e s u l t i n g in l o w e r speed. S i l i c o n - G a t e : r e d u c e s t h r e s h o l d and c a p a c i tance.
THE ADVANTAGES OF LSI LSI d e v i c e s offer two b a s i c a d v a n t a g e s : economy and s y s t e m p e r f o r m a n c e . In p a r t i c u l a r , LSI r e q u i r e s fewer p a c k a g e s , l o w e r p o w e r supply, l o w e r cooling r e q u i r e m e n t s . A s a r e s u l t , fewer PC c a r d s and conn e c t o r s a r e needed, h i g h e r p e r f o r m a n c e is obtained at the s a m e c o s t , b e t t e r r e l i a b i l i t y and m a i n t a i n a b i l i t y a r e achieved. T h e m a j o r l i m i t a t i o n s of LSI a r e e s s e n t i a l l y t h r e e : 1. e c o n o m i c : d e v e l o p m e n t cost, and cost of modifying a chip. 2. t e c h n o l o g i c a l : s l o w e r speed t h a n b i p o l a r . 3. m a n a g e m e n t : long l e a d - t i m e and s t a n d a r d v e r s u s c u s t o m logic. T h e m a j o r i m p a c t of MOS LSI is in r e d u c i n g t h e c o s t p e r - l o g i c - f u n c t i o n so d r a s t i c a l l y t h a t it is no l o n g e r a s i g n i f i c a n t p a r a m e t e r . Computing and logic functions b e c o m e e s s e n t i a l l y f r e e c o m p a r e d to o t h e r c o s t s . T h e c o s t of the whole m i c r o p r o c e s s o r i t s e l f is t y p i c a l l y a s m a l l f r a c t i o n of the total s y s t e m c o s t . THE LSI MICROPROCESSOR MOS b e c a m e a r e a l i t y in 1967/1968. T h e gate count p e r chip s t a r t e d to i n c r e a s e steadily: s m a l l - s c a l e i n t e g r a t i o n (SSI), m e d i u m - s c a l e i n t e g r a t i o n (MSI) (over 2000 t r a n s i s t o r s p e r chip), LSI {over 5000). T h e b a s i c p r o b l e m in LSI technology was to d e s i g n s t a n d a r d p r o d u c t s . In fact, s t a n d a r d i z a t i o n s t a r t e d only two y e a r s ago. F i r s t with r e c e i v e r - t r a n s m i t t e r s (UART's), t h e n c a l c u l a t o r c h i p s (in mid*72), l a r g e a r r a y s , and now m i c r o p r o c e s s o r s . At the s a m e t i m e , a l a r g e n u m b e r of g e n e r a l i z e d a r r a y s a r e b e i n g i n t r o duced: m e m o r i e s , sync g e n e r a t o r s , digital v o l t m e t e r s . T h e m a j o r i t y of such m i c r o p r o c e s s o r s is p r o b a b l y s t i l l c u s t o m - d e s i g n e d . The i n c r e a s i n g a v a i l a b i l i t y of s t a n d a r d m i c r o p r o c e s s o r s m a y r e v e r s e t h i s t r e n d in t h e d o m a i n of p r o c e s s o r c h i p s .
MICROCOMPUTER ARCHITECTURES MICROPROGRAMMED OR HARDWIRED It h a s b e e n explained above that a m i c r o p r o c e s s o r need not b e m i e r o p r o g r a m m e d . T h e c o n t r o l s e c t i o n of a m i c r o p r o c e s s o r m a y b e e i t h e r h a r d w i r e d (low cost) or m i c r o p r o g r a m m e d (flexibility). Both o r g a n i z a t i o n s have m e r i t s which m a k e t h e m v a l u a b l e for specific applications. H i s t o r i c a l l y , m i c r o p r o c e s s o r s w e r e introduced a s m o d ified c a l c u l a t o r d e s i g n s , i . e . , w e r e 4 bit wide and had a h a r d w i r e d i n s t r u c t i o n set. A c o m p e t i n g philosophy a p p e a r e d with 2 - c h i p p r o c e s s o r s : they u s e a RALU and a CROM. The RALU is a r e g i s t e r equipped a r i t h m e t i c logical unit (ALU). The CROM is a r e a d only m e m o r y (ROM) for RALU c o n t r o l . The chip count m a y be i n c r e a s e d a s one CROM c o n t r o l s s e v e r a l R A L U ' s o r s e v e r a l CROM's c o n t r o l one RALU. The flexibility gained with a p r o g r a m m a b l e c o n t r o l chip is b e n e f i c i a l for expanded o r v a r y i n g i n s t r u c t i o n s e t s a s well a s m i c r o c o d e d c o n t r o l a l g o r i t h m s . T h i s m i e r o p r o g r a m m i n g facility m a y p r e s e n t d i s a d v a n t a g e s : i n c r e a s e d e n g i n e e r i n g , d e v e l o p m e n t t i m e for i n s t r u c t i o n set, cost penalty. THE BIT WIDTH T h e f i r s t m i c r o p r o c e s s o r s , d e r i v e d f r o m the c a l c u l a t o r s , w e r e 4 - b i t wide. With i m p r o v i n g technology, 4, 8 and 1 2 - b i t m i c r o p r o c e s s o r s h a v e b e e n r e a l i z e d . The q u a s i - u n i v e r s a l width is now 8 bits, a n o p t i m u m in view of c u r r e n t pin count l i m i t a t i o n s (40 pins) and of c o m p o nent s t a n d a r d i z a t i o n . Often, ALU chips m a y b e used in p a r a l l e l , like m e m o r y chips, r e s u l t i n g in m o d u l a r 12, 16 or 2 4 - b i t s y s t e m s b a s e d on 4 b i t or 8 bit chips. THE CHIP COUNT Although a m i c r o p r o c e s s o r r e s i d e s on a s m a l l n u m b e r of c h i p s (one to t h r e e ) , the c o m p l e t e m i c r o c o m p u t e r s y s t e m r e q u i r e s m a n y m o r e . Typically, a c o m p l e t e s y s t e m will r e q u i r e 14 to 50 I C ' s , with c l o c k s and t i m i n g , c o n t r o l logic, plus p e r i p h e r a l i n t e r f a c e I C ' s (5 to 30 I C ' s ) . T h e total n u m b e r of I C ' s is 19 to 80. New a r c h i t e c t u r e s s e e k to m i n i m i z e the chip count by i n c o r p o r a t i n g m o r e functions within a chip: c o n t r o l , timing, buffering. THE INTERNAL REGISTERS A s p a c k i n g d e n s i t i e s h a v e i n c r e a s e d , it h a s b e c o m e p o s s i b l e to supply an i n c r e a s i n g n u m b e r of i n t e r n a l r e g i s t e r s . F r o m the u s e r ' s standpoint the two e s s e n t i a l functions a r e working r e g i s t e r s and s u b r o u t i n e a d d r e s s s t a c k . Typically, a m i c r o p r o c e s s o r will now include 8 to 16 i n t e r n a l working r e g i s t e r s (8 bit). T h e cost of p r o v i d i n g m o r e r e g i s t e r s is not so m u c h a h a r d w a r e
11 c o s t a s a l o s s of a d d r e s s b i t s i n t e r n a l l y , for r e g i s t e r selection. It will a l s o include a facility for subroutine n e s t i n g , the stack. Two p h i l o s o p h i e s c o m p e t e : an i n t e r n a l s e t of h a r d w a r e r e g i s t e r s , o r a p o i n t e r to m e m o r y . An i n t e r n a l set of 8 to 16 r e g i s t e r s o f f e r s a s p e e d advantage in stacking o p e r a t i o n s (fast i n t e r r u p t r e s p o n s e ) . The d i s a d v a n t a g e s a r e a l o s s of flexibility (the n u m b e r of l e v e l s i s l i m i t e d to t h e n u m b e r of r e g i s t e r s ) and a significant i n c r e a s e in c o m p l e x i t y . The s e c o n d a p p r o a c h u s e s a p r o g r a m c o u n t e r and a s t a c k p o i n t e r (plus p e r h a p s a s t a c k b a s e ) . It allows an u n l i m i t e d n u m b e r of r e t u r n a d d r e s s n e s t i n g s , but is s l o w e r than the i n t e r n a l r e g i s t e r a p p r o a c h . The gain in flexibility t e n d s to f a v o r i z e t h i s d e s i g n philosophy in the most recent microprocessors. EXISTING MICROPROCESSORS INTEL : MCS 8008 In addition to its f o u r - b i t MCS-4 m i c r o p r o c e s s o r , Intel o f f e r s an e i g h t - b i t p r o c e s s o r , the MCS-8. Its c o m p l e x i t y is equivalent to 125 TTL p a c k s . The m i c r o p r o c e s s o r chip i n c o r p o r a t e s : 1. an e i g h t - b i t p a r a l l e l a r i t h m e t i c unit 2. s e v e n e i g h t - b i t data r e g i s t e r s 3. eight f o r t e e n - b i t r e g i s t e r s (stack) for subroutine nesting. 4. i n s t r u c t i o n decoding and c o n t r o l logic (this is a h a r d w i r e d p r o c e s s o r ) . I n t e r r u p t capability. 48 i n s t r u c t i o n s . Typical m a c r o - i n s t r u c t i o n t i m e is 20 u s for the 8008, 12,5 us for the 8008-1. M e m o r y is ROM, PROM, RAM o r shift r e g i s t e r s , up to 16 K by 8 - b i t w o r d s . A d d r e s s i n g i s implicit: a, r e g i s t e r m u s t be loaded. T h i s m i c r o p r o c e s s o r u s e s an 18-pin p a c k a g e . It o f f e r s e x t e n s i v e s o f t w a r e and prototyping s u p p o r t . INTEL 8080 T h i s i s an n - c h a n n e l silicon-gate, 40-pin m i c r o p r o c e s s o r , due to be introduced s h o r t l y . Its d e s i g n is analogous to the 8008. The CPU contains: 1. 8 - b i t p a r a l l e l b i n a r y ALU 2. s e v e n 8 - b i t data r e g i s t e r s four t e s t a b l e flag b i t s 3. h a r d w i r e d c o n t r o l . E x t e r n a l l y TTL compatible 4. one 16-bit s t a c k p o i n t e r and a 16-bit program counter. Non m e m o r y r e f e r e n c i n g i n s t r u c t i o n s a r c executed in 2 m i c r o s e c o n d s (2MHz clock). In this p r o c e s s o r , the a d d r e s s is 16-bit wide, and the s t a c k is in e x t e r n a l m e m o r y (unlimited). The m i c r o -
p r o c e s s o r only c o n t a i n s a s t a c k p o i n t e r . Upon i n t e r ruption, t h e p r o g r a m - c o u n t e r plus the data r e g i s t e r s , the accumulator, and the flags, can be s t a c k e d . A n o t h e r d i f f e r e n c e l i e s in the b u s s i n g : the 8080 d o e s not t i m e - m u l t i p l e x data and a d d r e s s o v e r a single bus anym o r e . The 16 b i t - a d d r e s s p r o v i d e s a 64 K-8 bit m e m o r y a d d r e s s i n g capability without an e x t e r n a l m e m o r y register. The 74 i n s t r u c t i o n s include the 48 i n s t r u c t i o n s of the 8008 (compatibility). The packaging is 40-pin DIP. NATIONAL SEMICONDUCTOR : IMP 16 C National S e m i c o n d u c t o r (NS) u s e s a building block a p p r o a c h for its s y s t e m s , the IMP 16 'C ~(~16h i t s ) and the IMP 8 C (8 b i t s ) . They a r e built around m:icrop r o g r a m m a b l e f o u r - b i t p r o c e s s o r m o d u l e s . The IMP 16 C u s e s four R A L U ' s and a CROM to f o r m a 16-bit s y s t e m . Each RALU has: 1. s e v e n i n t e r n a l r e g i s t e r s : four g e n e r a l p u r p o s e , including one a s index plus t h r e e for the m i c r o c o d e (PC, MAR, MDR) 2. 16-word s t a c k (4 bits) 3. 4 status flags 4. 4 - b i t wide ALU (ADD, AND, OR, EOR and shift). The CROM p r o v i d e s the c o n t r o l logic for up to eight R A L U ' s . It s t o r e s the m i c r o p r o g r a m and o f f e r s a s t a n d a r d i n s t r u c t i o n set of 43 i n s t r u c t i o n s . The ROM s t o r e s i00 23-bit m i c r o i n s t r u c t i o n s . A typical m a c r o i n s t r u c t i o n r e q u i r e s 7 us. The clock c y c l e of 1.5 us is divided in four p h a s e s . The c o m m a n d s s p e c i f i e d b e t w e e n the RALU and the CROM a r e : 1. A-source register 2. B-source register 3. ALU o p e r a t i o n s e l e c t 4. R-address register. The pin count is 24 for RALU and CROM. FAIRCHILD : P P S 25 T h i s is a f o u r - b i t p r o c e s s o r intended for s c i e n t i f i c c a l c u l a t i o n s . It b e l o n g s to the family of p r o c e s s o r s d i r e c t l y d e r i v e d f r o m c a l c u l a t o r c h i p s . It u s e s a m u l t i chip approach: a 3805 a r i t h m e t i c unit, a 3806 p r o g-rammed function and timing unit, a 3810 ROM for m i c r o p r o g r a m s , a 3808 for m e m o r y . Its o r g a n i z a t i o n is 25-digit s e r i a l , 4-bit p a r a l l e l , with a 62.5 us w o r d t i m e , 2.5 us bit t i m e (addition of two 25 digit n u m b e r s in 62.5 us, multiplication in 50 m s ) . Each ROM s t o r e s 256 m i c r o i n s t r u c t i o n s . Up to 26 ROM
12 c h i p s may be u s e d in one s y s t e m . The m e m o r y chip s t o r e s d i g i t s , each 4 b i t s b i n a r y - c o d e d (BCD). T h e r e a r e 3 25-digit r e g i s t e r s p e r chip. Its c h a r a c t e r i s t i c s a r e : one 25-digit r e g i s t e r 4 b i t s p e r digit BCD s e r i a l / p a r a l l e l : 25 digit s e r i a l , 4 bit p a r a l l e l 95 i n s t r u c t i o n s bit t i m e is 2.5 us, word t i m e is 62.5 us (25 digits + 25 digits) 4 level subroutine s t a c k external interrupt 1 to 7 25-digit m e m o r y r e g i s t e r s 1 to 26 ROMS : 256 x 1 2 b i t s . TOSHIBA TLCS 12
T o s h i b a ' s m i c r o p r o c e s s o r is 12-bit wide and i n c o r p o r a t e s the c o n t r o l ROM within the m i c r o p r o c e s s o r chip.
GENERAL AUTOMATION : LSI-12/16
The f o r m e r SPC-12 p r o c e s s o r b o a r d is r e p l a c e d by a single chip. It u s e s LSI, n - c h a n n e l SOS technology. It o f f e r s h i g h - s p e e d of n - c h a n n e l SOS and high density (2000 g a t e s or 4000 to 5000 t r a n s i s t o r s ) . The b a s i c b o a r d a c c o m o d a t e s the m i c r o p r o c e s s o r sysLem with up to 2 K of m e m o r y , o p e r a t o r c o n s o l e and s y s t e m o p e r ation f e a t u r e s . It f e a t u r e s c o m p l e x m e m o r y a d d r e s s i n g of up to 4 K w o r d s (12 bit a d d r e s s ) . F o r m i c r o p r o g r a m m i n g flexibility, t h i s s y s t e m u s e s a "ROM p a t c h " technique with two ROM b o a r d s • One holds 32 p a t c h a d d r e s s e s , the o t h e r holds the 32 p a t c h e s . The s y s t e m is s t r u c t u r e d in 12 b i t - p a r a l l e l for a d d r e s s e s , 8 - b i t p a r a l l e l for data. F i f t y - t w o b a s i c i n s t r u c t i o n s a r e o f f e r e d . B a s i c i n s t r u c t i o n c y c l e is 2.6 us.
FORTHCOMING MICROPROCESSORS
Its main c h a r a c t e r i s t i c s a r e : 12 bit ALU with f a s t - c a r r y logic 5 working r e g i s t e r s • 8 12-bit g e n e r a l - p u r p o s e r e g i s t e r s (7 available to the u s e r , plus p r o g r a m s t a t u s word).
AMERICAN MICROSYSTEMS INC (AMI) : 7300
A minimum system configuration necessitates the microprocessor, three memories, and one memory control unit.
This m i c r o p r o g r a m m e d 2-chip p r o c e s s o r is p a r a l l e l , 8-bit. It u s e s a RALU plus CROM philosophy. Both c h i p s a r e p - c h a n n e l , silicon-gate, ion-implanted. The RALU c o n t a i n s : 1. ALU with A and B - s o u r c e r e g i s t e r s , status register, result register 2. t h i r t y - t w o g e n e r a l r e g i s t e r s which can be used a s e i t h e r one or two s t a c k s and or one o r two register sets 3. s e v e n - a d d r e s s stack.
M i c r o i n s t r u c t i o n s a r e 29 b i t s wide. The s y s t e m a c c o m o d a t e s up to 128 m i c r o i n s t r u c t i o n s . The packaging is 42-pin DIP, logic d e n s i t y is c l a i m e d to be equivalent to 11000 p - c h a n n e l MOS t r a n s i s t o r s ( s i l i c o n - g a t e technology). ROCKWELL MICROELECTRONICS : 10660 T h i s is a f a s t f o u r - b i t p a r a l l e l p r o c e s s o r (5 us) with 50 w i r e d i n s t r u c t i o n s . It u s e s ROMs, RAMs, and 10 c h i p s . They a r e 4 2 - l e a d flat p a c k s .
The s y s t e m is d e s c r i b e d for its a r c h i t e c t u r a l i n t e r e s t . It has b e e n announced r e c e n t l y that it will not be implemented.
The control ROM is called M i c r o i n s t r u c t i o n ROM or MIR. It is a 512-word by 22-bit m a s k p r o g r a m m a b l e ROM. The i n s t r u c t i o n c y c l e is 4 us. T h e r e is a f o u r level i n t e r r u p t s y s t e m . SIGNETICS
Subroutine n e s t i n g is p e r f o r m e d in RAM. The a d d r e s s bus is 12-bit wide. Two d e c i m a l digits a r e added in 30 us. COMPUTER AUTOMATION : NAKED MINI C o m p u t e r Automation developed a s e v e n - c h i p MOS/LSI p r o c e s s o r to build a b a s i c 16 b i t - s y s t e m . It u s e s four R A L U ' s and t h r e e c o n t r o l - c h i p s with P r o g r a m m a b l e Logic A r r a y s (PLA's) r a t h e r than ROMs. All b u s s i n g is 16-bit wide. The newly developed LSI-2 p r o c e s s o r r e p l a c e s the LSI-1, is faster, and c o m p a t i b l e .
Signetics p l a n s the introduction of an 8 - b i t fixed ins t r u c t i o n p r o c e s s o r with e x t e n s i v e a d d r e s s i n g c a p a b i l i t i e s : d i r e c t , i n d i r e c t , r e l a t i v e , absolute, i m m e d i a t e . It will be an n - c h a n n e l silicon*gate p r o c e s s o r . I n s t r u c tion t i m e is 5 to 10 us. The ALU contains 4 g e n e r a l r e g i s t e r s , an e i g h t - r e g i s t e r stack, and i m p l e m e n t s 75 i n s t r u c t i o n s . The a d d r e s s bus is 15-bit wide. ins t r u c t i o n s a r e s t r u c t u r e d in a 6 - b i t opcode and 2-bit r e g i s t e r p o i n t e r . It u s e s a 40-pin package. Introduction planned for 1974.
13 Programmed games.
OTHERS Monolithic M e m o r i e s and Raytheon have announced a b i p o l a r m i c r o p r o c e s s o r . R a y t h e o n ' s is a s e v e n - c h i p s y s t e m , with 3 CROMs and 4 R A L U s to p r o d u c e a 16 bit s y s t e m . Due to the b i p o l a r technology, the e x p e c t e d s p e e d is 200 ns. S i e m e n s h a s announced d e v e l o p m e n t p l a n s for an MOS n - c h a n n e l 8 b i t - m i c r o p r o c e s s o r analogous to the Intel 8080. T e x a s I n s t r u m e n t s , A m e r i c a n M i c r o s y s t e m s , and M i c r o s y s t e m s I n t e r n a t i o n a l a r e said to be c o n s i d e r i n g l i c e n s i n g a g r e e m e n t s for s e c o n d - s o u r c i n g the 808 0. Inselek has announced plans for a CMOS, SOS microprocessor with a 300 ns cycle time.
RCA has announced a 2 - c h i p CMOS 8 bit m i c r o p r o c e s s o r using a 16 x 16 s c r a t c h p a d for m e m o r y accesses.
W e s t e r n Digital and other m a n u f a c t u r e r s a r e a n nouncing p l a n s for new m i c r o p r o c e s s o r s . In view of the long l e a d - t i m e for d e v e l o p m e n t , it is likely that only a few m o r e will be effectively introduced this y e a r .
THE IMPACT OF MICROCOMPUTERS The impact of the m i c r o p r o c e s s o r can be e x p e c t e d to be m o r e significant than the mini revolution a few y e a r s ago. The r a n g e of m i c r o c o m p u t e r s y s t e m s extends throughout a wide s p e c t r u m of p e r f o r m a n c e and c o s t , f r o m the c a l c u l a t o r at the low end, to the m i n i c o m p u t e r at the high end. Typical execution t i m e s for m i c r o c o m p u t e r s a r e still 2 to 10 t i m e s s l o w e r than t h o s e for m i n i s , but a r e c o n s t a n t l y shrinking. M i c r o p r o c e s s o r s have evolved a s s t a n d a r d OEM p r o d u c t s , and c a t e r exc l u s i v e l y to the OEM u s e r s , while m i n i c o m p u t e r s u s u ally p r o v i d e e x t e n s i v e support g e a r e d to the e n d - u s e r . T h e i r m a j o r impact is felt on e c o n o m i c a l and " s m a r t " OEM digital p r o d u c t s . As MOS LSI c o s t s keep d e c r e a s i n g , the n u m b e r of m i c r o c o m p u t e r s should exceed by far the n u m b e r of any o t h e r type of c o m p u t e r being p r o d u c e d .
RE FERENC ES 1.
C . G . Bell and al, "The A r c h i t e c t u r e and Applic a t i o n s of C o m p u t e r Modules: A Set of C o m p o n e n t s for Digital Design", COMPCON 73, M a r c h 1973, pp. 177-180.
GENERAL RULES
2.
O r i g i n a l l y intended for d e s k - c a l c u l a t o r usage, m i c r o c o m p u t e r s y s t e m s a r e now being u s e d in an i n c r e a s i n g r a n g e of a p p l i c a t i o n s .
S. Davis, "A F r e s h View of M i n i - and M i c r o c o m p u t e r s " , C o m p u t e r Design, May 1974, pp. 67-79.
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C . C . F o s t e r , "A View of C o m p u t e r A r c h i t e c t u r e " , CACM J u l y 1972, Vol. 15, n u m b e r 7, pp. 557-565
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S. F u l l e r and D. Siewiorek, "Some O b s e r v a t i o n s on S e m i c o n d u c t o r Technology and the A r c h i t e c t u r e of L a r g e Digital Modules", C o m p u t e r , Oct 1973, pp. 15-19
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M . E . Hoff, J r , "Applications for M i c r o c o m p u t e r s in I n s t r u m e n t a t i o n " , 1973 IEEE I n t e r c o m
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R. Holt, M. L e m a s , " C u r r e n t M i c r o c o m p u t e r A r c h i t e c t u r e " , C o m p u t e r Design, F e b r u a r y 1974, pp. 65-73.
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G. Lapidus, "MOS/LSI L a u n c h e s the Low Cost P r o c e s s o r " , S p e c t r u m , Nov 1972, pp. 33-40.
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G. Reyling, J r , "LSI Building Blacks for P a r a l l e l Digital P r o c e s s o r s " , 1~,73 IEEE I n t e r c o n .
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T. Tarui, and al, " T w e l v e - b i t m i c r o p r o c e s s o r nears minicomputer's performance level", E l e c t r o n i c s , M a r c h 1974, pp. 111-116.
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J . W e i s b e c k e r , "A Simplified M i c r o c o m p u t e r A r c h i t e c t u r e " , C o m p u t e r , M a r c h 1974, pp. 41-47.
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W. W i c k e s , "A Compatible MOS/LSI M i c r o p r o c e s s o r Device F a m i l y " , C o m p u t e r Design, July 73, pp. 75-81.
APPLICATIONS OF MICROCOMPUTERS
The g e n e r a l r u l e s for using a m i c r o p r o c e s s o r instead of a h a r d w i r e d d e v i c e can be s u m m a r i z e d as follows: 1. sequential digital application r e q u i r i n g o v e r 50 hardwired IC's 2. n o n - t r i v i a l p r o g r a m s e q u e n c e 3. logical or a r i t h m e t i c r e q u i r e m e n t 4. no s u p e r - s p e e d , although multiple m i c r o p r o c e s s o r s m a y be used. APPLICATIONS M i c r o p r o c e s s o r s a r e u s e d in the following applications: Small b u s i n e s s m a c h i n e s , including c a l c u l a t o r s Point of Sale T e r m i n a l s (cash r e g i s t e r s , c r e d i t card verifiers) Data C o m m u n i c a t i o n ( c o m m u n i c a t i o n s p r e p r o c e s s o r , s m a r t t e r m i n a l , t e s t equipment, data c o n c e n t r a t o r , m e s s a g e switching, signal processor) P e r i p h e r a l s C o n t r o l l e r s {card r e a d e r , floppy d i s c , c a s s e t t e tape unit, line p r i n t e r s , CRT) G e n e r a l Control (machine tool, p r o c e s s c o n t r o l , e n v i r o n m e n t c o n t r o l for building, t r a f f i c c o n t r o l , e l e v a t o r c o n t r o l , a p p l i a n c e s , automobiles) Data A c q u i s i t i o n S y s t e m s I n s t r u m e n t a t i o n and device t e s t e r