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Microprocessor-based signal filters
Microprocessor-based signal filters General-purpose microprocessors and associated peripheral chips can provide simple and cost-effective digital filters, but they are being superseded by a new generation of specialized digital signal processors. Trevor J Terrell reviews notable developments in both areas of micro-based DSP
The concepts of microprocessor-based signal filters are presented via a case study of a simple low-pass filter designed using the bilinear z-transform method. The paper provides a general introduction to signal filtering using microprocessor-based forms of implementation, and discusses several alternative system configurations based on commercially available microprocessors or specialpurpose integrated circuits. microprocessors digital signal processors switched capacitor filters
signal filters
Over the past decade digital signal processing (DSP) has played an increasingly important role in a number of branches of science and engineering. For example, DSP has found application in geophysical exploration for oil 1, electronic speech synthesis2, telecommunication systems3, digital control,4 network testing,5 medical electronics 6 and military systems7. The realization of these applications was made possible by the increased availability and falling cost of sophisticated large-scale integrated (LSI) chips. In particular, the ubiquitous microprocessor and associated peripheral chips provide the means of implementing relatively simple and cost-effective digital filters. However, in some applications the programmable general-purpose architecture inherent in the microprocessor imposes a significant computational speed restriction on DSP operations, and the baseband frequency range of analogue input signals is implicitly limited. Nevertheless, for voiceband signals (e.g. in telephony circuits) the processing rate of a microprocessor-based system is adequate when the quality of the processed or synthesized speech is acceptable in practice. Some success in improving processing speed has been achieved using integrated-circuit multipliers. This improvement may be appreciated by comparing the multiply time of the Advanced Micro Devices Am29517 16 bit x 16 bit School of Electrical and Electronic Engineering, Lancashire Polytechnic, Preston PR1 2TQ, UK
parallel multiplier (40 ns) with the time taken by the Motorola MC68000 microprocessor to form the same product (7 ~s); the IC multiplier achieves a remarkable increase in computational speed. Furthermore, some gain in processing speed has been accomplished using bit-slice system architectures for specific processing requirements. For example, the Texas Instruments 20 MHz bipolar 8-bit slice (SN54/74AS888) has been used to implement a pipelined bit-slice fast Fourier transform (FFT) processor, capable of performing a 1024-point realtime complex FFT analysis of analogue signals in 1.024 ms 7. Unfortunately, in some instances, experience has shown that the successful implementation of DSP bitslice systems is not always easily accomplished, and special attention to circuit board layout and constructional details may be necessary to avoid problems arising from the high-speed logic signal paths. Fortunately, however, in the last few years the development of selfcontained programmable digital filter modules and programmable DSP chips 8-13 has provided a practical means of implementing many realtime signal processing operations. Indeed, in response to the recognition of the market potential for DSP devices, many IC manufacturers have undertaken intensive development of DSP chips, and their design and fabrication is continuing at a rapid pace. Some notable developments are reviewed in this paper. PROCESSING ALGORITHMS Realization of a DSP function requires an algorithm (linear difference equation) for calculating the discrete time values used in implementing the processing operation. A number of established design methods exist for deriving the required linear difference equation via the corresponding z-plane representation of the digital processor transfer function 14- 1 9. One approach involves the selection or derivation of a suitable transfer function, G(s), corresponding to a prototype analogue circuit or system which meets the appropriate frequency domain specification. The digital transfer function, G(z), is then derived from knowledge of G(s) using an s-plane to z-plane mapping.
0141-9331/87/03131-10 $03.00 © 1987 Butterworth & Co. (Publishers) Ltd Vol 11 No 3 April 1987
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It is this ability to accomodate a required change in the frequency response characteristic that makes DSP processors advantageous when adaptive processing is required. For example, adaptive digital filters ~'2f have been used to implement equalization technique~ m communication networks, and they form the basis of lowbit-rate vocoders used in speech synthesis systems. However, it should be appreciated that for adaptive digital filters the IIR form of structure (Figure 1) may introduce problems of instability for certain b, coefficient values, and consequently a finite-impulse-response (FIR) digital filter (transversal filter) is used. Figure 2 shows the structure of the computational process of an FIR digital filter, and equations (5) and (6) define the corresponding transfer function and linear difference equation respectively.
The bilinear z-transform 2°, which is characteristically band limiting in its action, is a straightforward s-plane-toz-plane mapping, which is easy to apply by simply substituting a function of z for each Laplace operator s appearing in G(s). The resulting transfer function G(z) may be expressed in the direct form as M E G(z)
Y(z)
-
X(z)
-
i=
ai z-i o
(1)
;','
E
biz i
i=0
where b0 = 1 and N > M . The corresponding linear difference equation may be written in the form M
y(n) = E
N
aix(n - i ) - ~
biy(n - i)
(2) G(z)
i
i=0
M
y(z)
i=1
.-~
X(z) -/~J
-
a~z
'
(5)
i
M
In performing the computation defined by equation (2), three basic processing operations are involved: addition/ subtraction, multiplication, and a unit delay z -1 equal to a sampling period T. Figure 1 shows the structure of the computational process defined by equation (2). This type of structure yields an infinite impulse response (IIR) digital filter, and its frequency response is governed by the value of the ai and bi coefficients. For example
y(n) = ~
• an A/D converter which will provide the input sample value x(n) • a D/A converter which will transform the output sample value, y(n), into an equivalent analogue voltage value • a programmable digital processor capable of handling the sampled data and executing the filter's arithmetic operations defined by the linear difference equation • ROM and RAM for storage of coefficients, program instructions and scratch-pad data
is the linear difference equation of a second-order lowpass digital filter with a cut-off frequency of 100 Hz, the design being based on a second-order Butterworth lowpass prototype filter and derived via the bilinear ztransform using a sampling period of 1.6 ms. A change of the three a i coefficients in equation (3) transforms the low-pass digital filter to a corresponding second-order high-pass digital filter with the same value of cut-off frequency (100 Hz). To achieve the transformation the linear difference equation is changed to
Additionally, practical considerations dictate that for realtime signal processing the highest frequency component in the baseband frequency range of the analogue
y(n) = 0.48Ix(n) - 0.962x(n - 1) + 0.481x(n - 2)
x(n -
t)
(4) _
x(n - M)
Unit delay
(6)
Irrespective of the filter structure, the DSP system must be capable of accepting the input sample value x(n), in a serial or parallel data form; it must then process the samples according to the linear equation and provide the output sample value, y(n). This process imposes basic system hardware requirements on a digital signal processing system, viz.
(3)
+ 0.671 y(n - 1) - 0.253y(n - 2)
aix(n - i)
q
i=0
y(n) = 0.145x(n) + 0.291x(n - 1) + 0.145x(n - 2) + 0.671y(n - 1) - 0.235y(n - 2)
i=O
[
[
aMliv
~---.~~]
. .
J
I
y(n)
y(n --
Figure I.
732
11
IIR digital filter structure
Microprocessors and Microsystems
and inexperienced engineers. A valuable introduction to the concept of a microprocessor-based digital filter may be achieved through the study of a simple DSP system based on a common and inexpensive microprocessor, and in this context an illustrative example is presented below.
x(n - M)
aM~l~~ y(rl)
Example system The transfer function of the denormalized second-order Butterworth low-pass filter is
ao
Figure 2.
FIR digital filter structure
2
°)ca
input signal must be less than half of the sampling frequency value, fs = lIT. This is necessary to prevent aliasing errors, which result when the sampling theorem is violated. For example, it would be futile to sample a voice signal at a rate of 4 kHz because the quality of the processed speech would be unacceptable. The sampling frequency would have to be increased considerably to improve the intelligibility of the s p e e c h - - a n 8 kHz sampling rate is typically used in telephone networks. In practice, the analogue input signal may pass through an antialiasing filter (analogue low-pass filter) before it is sampled, thereby ensuring that the sampling theorem is satisfied. Also, for some applications it is common practice to connect the DSP system D/A output to the input of a reconstruction filter to smooth the stepped form of the output waveform. Figure 3 shows a simplified block diagram of a typical DSP system.
G(S) = 52 + 21/2O)cas + COca2
(7)
taking the specification for a low-pass digital filter to be: cut-off frequency fed = 100 HZ; sampling frequency fs = 625 Hz (T = 1.6 ms); design to be based on the prototype second-order Butterworth low-pass filter in equation (7). The transfer function given by equation (7) may now be mapped from the s-plane to the z-plane using the bilinear z-transformation. However, a nonlinear frequency distortion (warping)is produced by the bilinear z-transform and must be taken into account in the design process by prewarping the s-plane frequency scale. To achieve this the cut-off frequency is calculated using equation (8). Oca = ~ tan
(8)
where oca is the radian prewarped cut-off frequency of the denormalized analogue filter, mcd is the specified radian cut-off frequency of the digital filter and T is the sampling period. Substituting the specific parameters in equation (8) yields
MICROPROCESSOR-BASED DSP SYSTEMS Microprocessors offer an attractive low-cost form of implementation for some DSP applications, and in recent years they have grown in popularity as design engineers have become more experienced in microprocessor system design. They are worthy of consideration because the sophistication of the microprocessor chip has advanced considerably, and because improved support chip functions have enhanced the processing capability of microprocessor systems. Furthermore, reliable support facilities for hardware and software development are readily available, and the amount of time required to gain familiarity with and proficiency in system design and implementation is not too large. Many reference sources exist for most microprocessors, a fact that is particularly reassuring to anyone engaged in DSP system design for the first time, especially students
O~ca= i.6 x2.10_ 3tan
200n X
= 687.2 rad s -1 The next step in the design is to substitute this value of 0)ca in equation (7), thereby producing the prewarped transformed transfer function G(s)pwt. Thus G(s)pwt
472243.84 s 2 + 971.85s + 472243.84
(9)
For the bilinear z-transform we use the substitution s
2 z-1 T
RAM/ROM]
~ Antialiasing filter
I,
A/D
Programmable x(n) digital ~--
Analogueinput signal,x(t) Figure 3.
nrn~mr
y(n)
D/A
y*(t)
~-
Reconstruction filter O ~
Analogueoutput signal,y(t)
Block diagram of a typical DSP system
Vol 11 No 3 April 1987
133
and for the specified value of T this gives (10)
s = 1 2 5 0 \ , z + 1, Substituting equation (10) in equation (9) gives z 2 + 2z + 1
Y(z)
(11)
CU
I +2z-1+z-2
= 6.88 - 4.62z -1 + 1.74z -2
x(n)
Since z -d implies a time delay of d sampling periods it follows that
,(n)
~ . ~ A/D converter~ ~ P I A /] D/A(ZN435) c°nverterO upt~ut 0uTI ,zN.8 I - I ,6.2t, '-D"/ I signal, signal,~ ~ CA2
X(z) + 2X(z)z -1 + X(z)z -2 transforms to
x(t) ~
x(n) + 2x(n - 1) + x(n - 2)
y*(t)
~
and 6.88Y(z) - 4.62Y(z)z -1 + 1.74Y(z)z -2 transforms to
oZ-LF
6.88y(n) - 4.62y(n - 1) + 1.74y(n - 2) Therefore the linear difference equation corresponding to equation (11)is equation (3). In this example the poles of G(z) and the roots of the denominator polynomial in equation (11) are a complex conjugate pair at z = 0.336 +_j0.374 which lie within the unit circle in the z-plane, thereby yielding a stable filter. The processor word length required to maintain stability, assuming truncation rather than rounding of the bi filter coefficients, may be determined using the method reported by Kuo and Kaiser22, i.e. for a pth-order filter having distinct poles at (cos ¢OkT- j sin 0~kT), where k is an integer in the range p ~>k ~> 1, the number of processor bits w must be w = smallest integer exeeding
r 5pV2 k=l P
(12)
Evaluating equation (12) for the complex conjugate poles obtained from equation (11) yields w = 2. This is not a surprising result considering that the poles are located well away from the circumference (stability boundary) of the unit circle. Note that there is no guarantee that with this value of w the filter will produce its specified frequency response characteristic. A rule of thumb is generally employed whereby four or five bits are added to w to take account of quantization and computational errors. Consequently, for this example it is appropriate to consider implementation using an 8-bit word length. An appropriate 8-bit microprocessor-based digital filter configuration is shown schematically in Figure 4. The flowchart for the filter implementation is shown in Figure 5. In computing y(n), the product terms in the equation involve evaluating the multiplication of two 8-bit binary numbers, thereby producing a 16-bit result which would normally be rounded or truncated and represented by the most significant eight bits. This obviously introduces computational errors which may degrade filter performance. In this example, with 8-bit representation, the rounding or truncation effect is insignificant because the poles of the filter are located well away from the circumference of the unit circle, and a considerable
134
Figure4. system
Convert command signal Status ignal
Block diagram of 6802-based digital filter
change in the representation of the product terms would be required to cause a significant degradation of the filter frequency characteristics. The performance of the digital low-pass filter may be demonstrated by using a square wave input test signal having a period Tp and defined by the following Fourier series:
x(t)=A0+-
n
cosmlt--cos3~lt+-cos5mlt-... 3 5
where c0~ = 2n/Tp. The considerable attenuation of the high-frequency nth odd harmonic components (of the form 1/n cos naht) in the input signal, resulting from the filtering process, produces an output signal y(t) which is a reasonable approximation to a sinusoidal signal having a predominant fundamental component equal to the fundamental frequency of the input signal, that is 2
y(t) ~ A o + - cos (01t n
Figure 6 shows the output waveform y(t) resulting from the implementation of the digital low-pass filter linear difference equation, equation (3), using the test signal x(t) defined above.
Switched capacitor filters Programmable low-pass and high-pass switched capacitor filters (SCFs) are compatible with microprocessors, and are increasingl)[, being used to implement signal filtering operations23, 2.. The basic principle of operation of an SCF relies on small capacitors switched between circuit nodes at high rates to create corresponding equivalent circuit resistances.
Microprocessors and Microsystems
Consider the CMOS circuit shown in Figure 7 with switch $1 closed at time t = 0 and switch $2 open; the charge on the capacitor is then CV1. If switch $1 is opened and switch $2 closed after time T, then the charge changes to CV2. Since the average current i transferred between nodes V~ and V2 is equal to the rate of change of charge, we may write i - C(Vl - V2) T
Initialize stack pointer
Clear:
x(n - 1) x(n - 2) y(n-2) y(n-2)
Initialize PIA
convert command signal
Generate
for interrupt
t Yes Input x(n) Compute y(n) Outputto D/A y(n y(nx(n x(n -
Figure 5.
interrupt routine
2) = y(n - 1) 1)=y(n)
2) =x(n - 1) 1) =x(n)
Flowchart for 2 n d - o r d e r digital filter
but resistance R = (Vl - V2)/i = TIC = 1/(Cfs), where fs is the clock frequency. Therefore, since capacitors and transistor switches are readily implemented with CMOS technology, and because variable digital clock circuits may be easily fabricated, the SCF circuit provides an effective means of achieving a corresponding variable RC network performance. All circuit nodes must settle between the switched samples, and the maximum useful frequency is therefore limited by the settling time of the associated operational amplifier integrators. Settling to 0.1% is achievable within 1 ~s, but in practice filters have a maximum internal clock of about 400 kHz, thereby allowing 2.5 gs for the nodes to settle. For a typical low-pass filter the maximum cut-off frequency is about fs/20, i.e. approximately 20 kHz, and it is normal practice to use an antialiasing filter with an SCF to ensure that the sampling theorem is obeyed. Also it is appropriate to connect a reconstruction filter to the SCF output to smooth the stepped output arising from the switching action. Figure 8 shows a Gould AMI Semiconductors $3528 CMOS programmable switched-capacitor low-pass filter 24, which provides an accurate and flat frequency response in the passband (ripple less than _+ 0.1 dB) and stopband rejection greater than 51 dB for f > 1.3 fc, where fc is the cut-off frequency of the filter. In dynamic applications (adaptive filtering) a microprocessor may be used to select and change any one of a set of 64 different cut-off frequencies. The 6-bit data input word determines the selected filter cut-off frequency, and the application of an active-low chip enable pulse (minimum width 200 ns) latches in the data word. For example, an input code equal to 10 (hex.) sets the cut-off frequency to 1005 Hz, and if this is changed to 11 (hex.) the cut-off frequency correspondingly increases to 1105 Hz. A selection of loss curves for four different control codes is shown in Figure 9. Compared with the common form of microprocessorbased digital filter, the SCF form is much simpler to design (no s-plane to z-plane transformation needed) and can deal with a wider range of baseband signal frequencies. Node voltage
Figure 6. Waveforms for illustrative example: top, i n p u t signal, x(t); middle, o u t p u t signal from D / A converter, y*(t); b o t t o m , o u t p u t from reconstruction filter, y(t)
Vol 11 N o 3 April 1987
Node voltage Figure 7.
C M O S switched-capacitor circuit
135
Antialiasing filter
I
!
I
J 10
Input signal,x(t)
~
pCe'ter
Seventh-order elliptical low-passfilter
3.58 MHz 11-stage programmable divider
Smoothing filter
-12 1
18 17 16
Microprocessor (6802) Data bus
6-bit latch Output signal, y(k)
D5 (S3528)
4
E
I Addressdecode l logic
Addressbus
Figure 8.
Programmable 53528 switched-capacitor low-pass filter
However, for continuously variable dynamic control of the frequency response characteristic, the common form of linear difference equation implementation using a microprocessor-based system is more precise than the stepped change achievable with the SCF device.
DSP
CHIPS
The first DSP chip was the Intel 29208 , which was launched in 1979. It possessed on-chip data converters, but it lacked an on-chip multiplier and its instruction set was limited. The anticipated market for the 2920 was never achieved, but fortunately this did not deter other companies from developing their own DSP chips. In 1980 NEC introduced the pPD77208,11 DSP chip. This incorporated a 16 bit x 16 bit multiplier and a 16-bit twos complement ALU; this combination permitted the implementation of a sum-of-products operation (see equation (6)) in a single instruction cycle (250 ns). At about the same time as the development of the NEC DSP chip, the implementation of an MOS integrated circuit for digital filtering was achieved at British Telecom Research Laboratories. This chip, known as FAD (filter and detect)12, 2s, requires a single-phase clock and very little external circuitry to implement a digital filter (see Figure 10). The FAD chip is now manufactured and marketed by Plessey Semiconductors as the MS2014FAD device. It is interesting to note that Plessey has recently launched other DSP products designed using its Megacell semicustom design methodology and manufactured in 2 pm CMOS. The first two members of the chip family are
136
the two-dimensional edge detector (PDSP16401) and the 16 X 12 bit complex number multiplier (PDSP16112). Texas Instruments has had remarkable success with its TMS320 family of DSP chips, the first member of which (TMS32010) was launched in 1983. The TMS32010 is a microcomputer with a 32-bit internal Harvard architecture and a 16-bit external interface capable of executing 5M instructions per second. The next significant development was the production of the TMS32020 DSP chip. This had a
0 10 20
~ 3o 0
~
40
50 60 70 0
I
I
1
1
2
3
Frequency(kHz) Figure 9. Selection of loss curves produced by the switched-capacitor low-pass filter
Microprocessors and Microsystems
FUTURE TRENDS (MS20141
Filte CLK
C
2.048MHz
clock
NR
R
t' ICLK
IQA Binary I counter IQE Figure 10.
r in
SYNC
I
J
-~-
DO
D1
A0 I[32RoMX 2 bit
-_1
I A41
Block diagram of a typical FAD filter
number of improvements over the 32010 to make it more suitable for multiprocessing DSP implementations; in particular the 32020 permits synchronization of the multiprocessing task and includes a serial port, DMA capability and a global data memory interface. A further addition to the TMS320 range was the TMS302C2526, a pin-compatible CMOS version of the 32020 chip with a faster instruction cycle (100 ns) and more on-chip memory. The 320C25 instruction set supports adaptive filtering, extended-precision arithmetic, bit-reversed addressing and faster I/O for data-intensive signal processing. Following the successful introduction of the early DSP chips many manufacturers have been active in developing and marketing their own devices; those known to the author are listed in Appendix I. A recent novel DSP device development has been introduced by Inmos in the form of the IMS AI00 cascadable signal processor. In designing this chip Inmos looked at the most widely used signal processing algorithms and concentrated on the associated structured evaluation tasks, such as the common repeated multiplication and accumulation operations involved in the linear difference equation. It was evident that the speed of the multipliers and the memory bandwidth were the main factors limiting the rate of data throughput. Consequently Inmos reappraised the classical processor architectural structures to see whether such limiting factors could be minimized by innovative architectures and by exploiting the high packing densities of today's chip fabrication processes. The result was a transversal architecture implemented as a dataflow machine, with each node comprising a multiplier-accumulator unit and local store. The resulting IMSA100 device is cascadable to produce transversal filters of several thousand stages with high numerical accuracy and no degradation in throughput (see Figure 111. The use of a medium-speed microprocessor and one or more A100 devices (Figure 11) results in a very highperformance system. For example, two A100s controlled by a host microprocessor can perform a 1024-point complex discrete Fourier transform in less than 10 ms. Performance increases almost in proportion to the number of A100s used, and therefore this form of DSP system is capable of realizing throughputs previously only possible with bit-slice systems.
Vol 11 No 3 April 1987
The emergence of VLSI microelectronics technology and computer-aided design methodologies have given rise to significant developments in DSP and VLSI signal processing. However, it would be foolish to expect all further advances to emerge solely from improvements in device fabrication techniques. In fact it has been predicted that before 1990 we should expect little more than a 20-fold improvement in the functional throughput rate of VLSI chips. Consequently it is expected that the major significant advances will be achieved from the development of novel architectural structures and the efficient implementation of parallelism in the computational processes. Designers have had to produce improved processor architectures. Notably, the classical sequential processing strategy (von Neumann architecture) has been replaced by the more efficient parallel processing form (Harvard architecture), thereby increasing the speed of data handling and computations. The Motorola DSP56000 device architecture, for example, has been designed to maximize throughput in data-intensive DSP applications. This objective has been realized by the provision of two independent expandable data memory spaces, two address arithmetic units and a data ALU which has two accumulators and two shifter-limiters. This duality of the device architecture facilitates efficient writing and execution of software for DSP applications. Research has shown that parallel processing architectures with highly attractive and promising characteristics for utilizing VLSI technology may arise from a combination of systolic and wavefront architectures27, 28 A systolic system may be configured using an array of processors operating in a rhythmical manner to perform the computations and transmission of data for the desired signal processing operation. All of the processing elements use common control (timing) signals and simultaneously perform the same function on different sampled-data values. The systolic array therefore exhibits modularity, regularity and local interconnection synchronized pipelined multiprocessing, and offers remarkable potential for improved architectures for future DSP chips and VLSI signal processing 29-31.
CONCLUDING REMARKS This paper has attempted to illustrate some of the main concepts of microprocessor-based signal filters, and several forms of implementation have been reviewed. In Go
Clock
Data-~ IMSAIO0 I
IMSAIO01-- *SA,OO a
I
I
Microprocessor [ Figure 11.
Cascaded/MS A l O0-based DSP system
137
particular, the intention has been to make the reader more aware of the availability of microprocessor-based signal filters, and of the range of devices now commercially available for DSP applications. Readers requiring further information should consult the manufacturers and suppliers listed in Appendix 1.
REFERENCES 1 Mesko, A Digital filtering applications in geophysical exploration for oil Pitman, London, UK (1984) 2 Brislow, G Electronic speech synthesis Granada, London, UK (1984) 3 Bellanger, M Digital processing of signals: theory and practice John Wiley, New York, USA (1984) 4 Katz, P Digital control using microprocessors PrenticeHall, Englewood Cliffs, NJ, USA (1981) 5 Willey, T 'Network testing using DSP' New Electron. (1 October 1985) pp 33-34 and 38 6 Fair, D and Windsor, B 'CMOS DSP components target new military applications' Defense Electron. (April 1986) pp 105-106, 109, 112, 114 and 116 7 Duval, I and Niehaus, I 'Pipelined bit-slice architecture eases FFT implementation' EDN (27 October 1983) pp 215-224 8 Quarmby, D Signalprocessor chips Granada, London, UK (1984) 9 Dettmer, R'Digital signal processors' Electron. Power (February 1986) pp 124-128 10 Terrell, T J and Simpson, R J 'Digital filtering using the Intel 2920 signal processor' Int. J. Elec. Engng, Educ. Vol 18 (1981) pp 211-224 11 Simpson, R J and Terrell, T I 'Digital filtering using the N EC PD7720 signal processor' Microproc. Microprog. Vol 14 (1984) pp 67-78 12 'Digital signal processing with the MS2014 FAD' Electron. Product Des. (May 1986) pp 49-56 13 Marven, C 'Second generation DSP expands into new domains' New Electron. (3 September 1985) pp 30, 33-34, 37 14 Rabiner, L R and Gold, B Theory and application of digital signal processing Prentice-Hall, Englewood Cliffs, N J, USA (1975) 15 Oppenheim, A V and Schafer, R W Digital signal processing Prentice-Hall, Englewood Cliffs, N], USA (1975) 16 Antonious, A Digital filter analysis and design McGrawHill, New York, USA (1979) 17 Terrell, T l Introduction to digital filters Macmillan, London, UK (1980) 18 Taylor, F I Digital filter design handbook Marcel Dekker, New York, USA (1983) 19 Williams, C S Designing digital filters Prentice-Hall, Englewood Cliffs, NJ, USA (1986) 20 Tustin, A 'A method of analysing the behaviour of linear systems in terms of time series' J. lEE Vo194 Part IIA (1947) pp 130-142 21 Grant, P M and Cowan, C F N 'Design and application of adaptive filters' Electron. Power (February 1985) pp 157-163 22 Kuo, F F and Kaiser, J F Systems analysis by digital computer John Wiley, New York, USA (1966) 23 Connor, J 'Filters mate with microprocessors' Electron. Product Des. (January 1985) pp 39-42 24 Gould AM I Semiconductors Programmable Iowpass
138
lrevor Terrell is a professor in the School of Electrical anc] Electronic Engineering, Lancashire Polytechnic, UK. From 1969 to 1972 he attended the University of Manchester Institute of Science and Technology, obtaining an MSc in 1970 and a PhD in 1972. In 1972 he was appointed as a lecturer in the Electrical Engineering Department of Preston Polytechnic (now Lancashire Polytechnic). His research interests include digital signal and image processing, and the application of microprocessors in digital control systems. Since 1974 he has been a chartered engineer and he is a fellow of the Institution of Electrical Engineers.
25
26 27 28 29 30 31
filter product description: $3528 (April 1984) and Programmable highpass filter product description: $3528 (June 1984) Adams, P F, Harbridge, J R and Macmillan, R H 'An MOS integrated circuit for digital filtering and level detection' IEEE J. Solid-State Circuits Vol SC-16 No 3 (June 1981) pp 183-190 TMS320C25 digital signal processor product description Texas Instruments, Bedford, UK (1986) Kung, H T 'Systolic arrays for VLSI' in Duff, I S and Stewart, G W (Eds) Sparse matrix proceedings SIAM, Philadelphia, PA, USA (1979) Kung, S Y etal. 'Wavefront array processor: language architecture and application' IEEE Trans. Comput. (November 1982) pp 1054-1066 Kung, S Y, Whitehouse, H l and KaUath, T VLSI and modern signal processing Prentice-Hall, Englewood Cliffs, NJ, USA (1985) Swartzlander, E E Jr VLSI signal processing systems Kluwer, Hingham, MA, USA (1986) Denyer, P and Renshaw, D VLSI signal processing: a bit-serial approach Addison-Wesley, Wokingham, U K (1985)
APPENDIX 1: MANUFACTURERS A N D SUPPLIERS OF DSP DEVICES Advanced Micro Devices (UK) Ltd AMD House, Goldsworth Road, Woking, Surrey GU21 1JJ, UK. Tel: (04862) 22121 29500 signal processor family (1982): a bit-slice architecture for DSP and array processing operations; benchmark: 1024-point complex FFT in approximately 2 ms
American Microsystems Inc. 3800 Homestead Road, Santa Clara, CA 95051, USA. Tel: (408) 246-0330 528211 signal processor family (1982): architecture pipelined to perform a read, multiply and accumulate with each 300 ns instruction cycle
Analog Devices Ltd Central Avenue, East Molesey, Surrey KT8 OSN, UK. Tel: 01-941 0466
Microprocessors and Microsystems
ADSP-2100 (1986): a programmable single-chip microprocessor for DSP and high-speed numeric processing applications; benchmark: 1024-point complex FFT in 7.2 ms
Burr-Brown PO Box 11400, Tucson, AZ 85734, USA. Tel: (602) 746-1111
point and floating-point arithmetic when data word values exceed 16 bit
Inmos Ltd 1000 Aztec West, Almondsbury, Bristol BS12 4SQ, UK. Tel: (0454) 616616
MPV960 (1985): configured around the Burr-Brown ADC84 12-bit A/D converter and the TMS320 DSP chip; provides high-speed analogue input with DSP on a VMEbus board
IMS A100 cascadable CMOS signal processor (1986): contains an array of 32 high-speed, high-accuracy, 16 x 16 bit multiplier-accumulators, plus registers and control logic, in a dataflow architecture to implement a digital transversal filter; benchmark: two A100s can achieve a 1024-point complex DFT in less than 2 ms
Calmos Systems 20 Edgewater Street, Kanata, Ontario, Canada K2L lV8. Tel: (6•3) 836-1014
Intel Corp. 5000 W Williams Fields Road, Chandler, AZ 85224, USA. Tek (602) 961-2000
CA128X16 FIR filter DMCU (1985): a building block for implementing FIR filters of orders from 1 to 128 ponts; when used in conjunction with an external filter coefficient memory and a multiplier-accumulator the data memory and control unit (DMCU) provides an FIR filter implementation with four ICs
2920 NMOS signal processor (1979): the first DSP chip, not now widely available
Euroka Oy Hameenite 155 C52a, 00560 Helsinki, Finland. Tek (358-0) 799522 SPU292 signal processing module: based on the Intel 2929 and designed to provide a microcomputer system with analogue signal processing capability, i.e. for DSP applications
I'I-IF Semiconductors Intermetall, 145-147 Ewell Road, Surbiton, Surrey KT6 6AW, UK. Tel: 01-390 6577 UDP101 CMOS digital signal processor (1984): a maskprogrammable device which has a multibus structure; uses pipelined program execution and the basic multiply and add instruction is implemented in 200 ms
Logic Devices Inc. Abacus Electronics Ltd, Abacus House, Bone Lane, Newbury, Berks RG14 5SF, UK. Tel: (0635) 33311
Fujitsu Amber Components Lid, Rabans Close, Aylesbury, Bucks HP19 3RS, UK. Tel: (0296) 34141
LSH32 32-bit cascadable barrel shifter-normalizer (1986): a high-speed shifter for use in floating-point normalization, word pack/unpack, field extraction and similar DSP applications
MB8764 general-purpose CMOS digital signal processor (1985): features a high-speed pipelined multiplier, supports concurrent operations with compound instructions and multiple data paths, and offers flexible and expandable memory options and an on-chip DMA channel; benchmark: 512-point FFT in 16 ms
Loughborough Sound Images Lid The Technology Centre, Epinal Way, Loughborough, Leics LE11 OQE, UK. Tel: (0509) 231843
General Instrument Microelectronics Lid Times House, Ruislip, Middx HA4 8LE, UK. (08956) 36141 DSP320C10-25 CMOS digital signal processor (1986): a 25 MHz device based on a pipelined architecture, and capable of executing 6.25 MIPS
Gould AMI Semiconductors AMI House, 56-58 Prospect Place, Swindon SN1 3JZ, UK. Tel: (0793) 37852 $7720 digital signal processor (1984): an advancedarchitecture microcomputer optimized for signal processing algorithms; benchmark: 64-point complex FFT in 1.6 ms
Hitachi Electronic Components (UK) Ltd 21 Upton Road, Watford, Herts WD1 7TP, UK. TeE (0923) 46488 HD61810B digital signal processor (1985): has a floatingpoint multiplier and a fixed-point/floating-point ALU, and can process signals over a dynamic range up to 32 bit, achieved via the automatic switching between fixed-
Vol 11 No 3 April 1987
TMS320 board (1986): IBM PC plug-in for the development of DSP applications using the TMS32020 device
Motorola Ltd Semiconductor Products Group, Colvilles Road, Kelvin Estate, East Kilbride, Glasgow G75 OTG, UK. Tel: (0734) 787848 DSP56000 family of DSP chips (1986): includes generalpurpose, algorithm-specific, application-specific and building-block parts; the DSP56000 device is capable of executing 10.25 MIPS and is suitable for general-purpose use; the DSP56200 device is a cascadable adaptive FIR filter, suitable for echo cancelling, telephone line equalization and other DSP applications
Mullard Lid Mullard House, Torrington Place, London WC I E 7HD, UK. Tel: 01-580 6633 SP50 family of CMOS DSP devices (1986): the PCB5011 is a ROMless version of the PCBS010 DSP device with a highly parallel Harvard architecture; it has a 16 x 16 bit hardware multiplier aided by a barrel shifter and format adjuster; benchmark: 16-point complex FFT in under 30 lus (excluding initialization procedures)
139
National Semiconductor (UK) Ltd The Maple, Kembrey, Park, Swindon, Wilts SN2 6UT, UK. Tel: (0793) 614141 LM32900 digital signal processor (1986): CMOS microprocessor optimized for DSP operations; it uses a pipelined Harvard architecture and a multiply and add/ substract operation can be executed in 200 ns
NEC Electronics (UK) Ltd Block 3, Carfin Industrial Estate, Motherwell ML1 4UL, UK. Tel: (0698) 732221 PD7720 digital signal processor (1980): uses a Harvard architecture and a multiply operation (16 × 16 bit) can be implemented in 250 ns; benchmark: FFT radix-2 butterfly in 91as
SDF family of digital filter building blocks (1981 ): a range of modules for various digital filter applications; for example, a single-pole high-pass filter with four selectable cut-off frequencies is provided by the SDF5208S module, and it may be operated with a sampling rate up to 15 MHz
STC Components Ltd Semiconductors Division, Maidstone Road, Sidcup, Kent DA14 5HT, UK. Tel: 01-300 3333 DSP128 digital signal processor (1984): a cascadable integrated signal processor (CRISP) which may be connected on a common bus for efficient implementation of multiprocessing tasks; it may also be used as a standalone processor or be interfaced to a generalpurpose microprocessor; benchmark: 64-point complex radix-2 FFT in 1.5 ms
Plessey Semiconductors Ltd Cheney Manor, Swindon, Wilts SN2 2QW, UK. Tel: (0793) 36251
Texas Instruments Manton Lane, Bedford MK41 7PA,UK. Tek (0234) 223000
MS2014FAD (1985), PDSP16401 (1986) and PDSP16112 (1986) digital signal processing chips: the MS2014FAD is a building block for implementing digital filters; the PDSP16401 is a two-dimensional edge detector; and the PDSP16112 is a 16 x 12 bit complex number multiplier
TMS320 family of digital signal processors (1983): a combination of a general-purpose single-chip microprocessor architecture with an ALU and multiplier, resulting in a 32-bit internal Harvard architecture capable of 5 MIPS; benchmark for the TMS320C25: 256-point complex FFT (radix-2 loop-coded) in 3.44 ms
Pye TMC Ltd Commercial Division, Martell Road, West Dulwich, London SE21 8EF, UK. Tel: 01-670 2211
Thomson Semiconducteurs Ringway House, Bell Road, Daneshill, Basingstoke, Hants RG24 OQG, UK. Tel: (0256) 29155
TMC539A PMOS dual second-order digital filter (ca. 1980): the filter sections are independent and may be used separately as a complete biquadratic, or they may be cascaded to form higher-order filters; sampling frequencies up to 16 kHz are practical
TS68930 programmable signal processing integrated VLSI (1986): a high-speed general-purpose signal and arithmetic processor with a parallel/pipeline architecture to simultaneously execute one ALU function, multiplication, two reads and one write operation and associated address calculation every 160 ns; benchmark: 256-point complex FFT in 2 ms
Reticon Corp. 910 Benicia Avenue, Sunnyvale, CA 94086, USA. Tel: (408) 738-4266 TAD32 tapped analogue delay (1977): a charge transfer device with 32 taps for implementing transversal filters; sampling rates up to 5 MHz are possible
Spectrum Devices Ltd Central Avenue, East Molesey, Surrey KT8 0SN, UK. Tel: 01~941 2708
140
TRW Electronic Components Group 75-17 High Street, Bedford MK40 1RU, UK. Tel: (0234) 217711 TDC1028 and TMC2243 FIR Filters (1985): the TDC1028 can be clocked at a rate up to 10 MHz and it implements an eight-tap FIR filter, whereas the TMC2243 can be clocked at a faster rate of 20 MHz and it implements a three-tap FIR filter
Microprocessors and Microsystems
The concepts of microprocessor-based signal filters are presented via a case study of a simple low-pass filter designed using the bilinear z-transform method. The paper provides a general introduction to signal filtering using microprocessor-based forms of implementation, and discusses several alternative system configurations based on commercially available microprocessors or specialpurpose integrated circuits. microprocessors digital signal processors switched capacitor filters
signal filters
Over the past decade digital signal processing (DSP) has played an increasingly important role in a number of branches of science and engineering. For example, DSP has found application in geophysical exploration for oil 1, electronic speech synthesis2, telecommunication systems3, digital control,4 network testing,5 medical electronics 6 and military systems7. The realization of these applications was made possible by the increased availability and falling cost of sophisticated large-scale integrated (LSI) chips. In particular, the ubiquitous microprocessor and associated peripheral chips provide the means of implementing relatively simple and cost-effective digital filters. However, in some applications the programmable general-purpose architecture inherent in the microprocessor imposes a significant computational speed restriction on DSP operations, and the baseband frequency range of analogue input signals is implicitly limited. Nevertheless, for voiceband signals (e.g. in telephony circuits) the processing rate of a microprocessor-based system is adequate when the quality of the processed or synthesized speech is acceptable in practice. Some success in improving processing speed has been achieved using integrated-circuit multipliers. This improvement may be appreciated by comparing the multiply time of the Advanced Micro Devices Am29517 16 bit x 16 bit School of Electrical and Electronic Engineering, Lancashire Polytechnic, Preston PR1 2TQ, UK
parallel multiplier (40 ns) with the time taken by the Motorola MC68000 microprocessor to form the same product (7 ~s); the IC multiplier achieves a remarkable increase in computational speed. Furthermore, some gain in processing speed has been accomplished using bit-slice system architectures for specific processing requirements. For example, the Texas Instruments 20 MHz bipolar 8-bit slice (SN54/74AS888) has been used to implement a pipelined bit-slice fast Fourier transform (FFT) processor, capable of performing a 1024-point realtime complex FFT analysis of analogue signals in 1.024 ms 7. Unfortunately, in some instances, experience has shown that the successful implementation of DSP bitslice systems is not always easily accomplished, and special attention to circuit board layout and constructional details may be necessary to avoid problems arising from the high-speed logic signal paths. Fortunately, however, in the last few years the development of selfcontained programmable digital filter modules and programmable DSP chips 8-13 has provided a practical means of implementing many realtime signal processing operations. Indeed, in response to the recognition of the market potential for DSP devices, many IC manufacturers have undertaken intensive development of DSP chips, and their design and fabrication is continuing at a rapid pace. Some notable developments are reviewed in this paper. PROCESSING ALGORITHMS Realization of a DSP function requires an algorithm (linear difference equation) for calculating the discrete time values used in implementing the processing operation. A number of established design methods exist for deriving the required linear difference equation via the corresponding z-plane representation of the digital processor transfer function 14- 1 9. One approach involves the selection or derivation of a suitable transfer function, G(s), corresponding to a prototype analogue circuit or system which meets the appropriate frequency domain specification. The digital transfer function, G(z), is then derived from knowledge of G(s) using an s-plane to z-plane mapping.
0141-9331/87/03131-10 $03.00 © 1987 Butterworth & Co. (Publishers) Ltd Vol 11 No 3 April 1987
131
It is this ability to accomodate a required change in the frequency response characteristic that makes DSP processors advantageous when adaptive processing is required. For example, adaptive digital filters ~'2f have been used to implement equalization technique~ m communication networks, and they form the basis of lowbit-rate vocoders used in speech synthesis systems. However, it should be appreciated that for adaptive digital filters the IIR form of structure (Figure 1) may introduce problems of instability for certain b, coefficient values, and consequently a finite-impulse-response (FIR) digital filter (transversal filter) is used. Figure 2 shows the structure of the computational process of an FIR digital filter, and equations (5) and (6) define the corresponding transfer function and linear difference equation respectively.
The bilinear z-transform 2°, which is characteristically band limiting in its action, is a straightforward s-plane-toz-plane mapping, which is easy to apply by simply substituting a function of z for each Laplace operator s appearing in G(s). The resulting transfer function G(z) may be expressed in the direct form as M E G(z)
Y(z)
-
X(z)
-
i=
ai z-i o
(1)
;','
E
biz i
i=0
where b0 = 1 and N > M . The corresponding linear difference equation may be written in the form M
y(n) = E
N
aix(n - i ) - ~
biy(n - i)
(2) G(z)
i
i=0
M
y(z)
i=1
.-~
X(z) -/~J
-
a~z
'
(5)
i
M
In performing the computation defined by equation (2), three basic processing operations are involved: addition/ subtraction, multiplication, and a unit delay z -1 equal to a sampling period T. Figure 1 shows the structure of the computational process defined by equation (2). This type of structure yields an infinite impulse response (IIR) digital filter, and its frequency response is governed by the value of the ai and bi coefficients. For example
y(n) = ~
• an A/D converter which will provide the input sample value x(n) • a D/A converter which will transform the output sample value, y(n), into an equivalent analogue voltage value • a programmable digital processor capable of handling the sampled data and executing the filter's arithmetic operations defined by the linear difference equation • ROM and RAM for storage of coefficients, program instructions and scratch-pad data
is the linear difference equation of a second-order lowpass digital filter with a cut-off frequency of 100 Hz, the design being based on a second-order Butterworth lowpass prototype filter and derived via the bilinear ztransform using a sampling period of 1.6 ms. A change of the three a i coefficients in equation (3) transforms the low-pass digital filter to a corresponding second-order high-pass digital filter with the same value of cut-off frequency (100 Hz). To achieve the transformation the linear difference equation is changed to
Additionally, practical considerations dictate that for realtime signal processing the highest frequency component in the baseband frequency range of the analogue
y(n) = 0.48Ix(n) - 0.962x(n - 1) + 0.481x(n - 2)
x(n -
t)
(4) _
x(n - M)
Unit delay
(6)
Irrespective of the filter structure, the DSP system must be capable of accepting the input sample value x(n), in a serial or parallel data form; it must then process the samples according to the linear equation and provide the output sample value, y(n). This process imposes basic system hardware requirements on a digital signal processing system, viz.
(3)
+ 0.671 y(n - 1) - 0.253y(n - 2)
aix(n - i)
q
i=0
y(n) = 0.145x(n) + 0.291x(n - 1) + 0.145x(n - 2) + 0.671y(n - 1) - 0.235y(n - 2)
i=O
[
[
aMliv
~---.~~]
. .
J
I
y(n)
y(n --
Figure I.
732
11
IIR digital filter structure
Microprocessors and Microsystems
and inexperienced engineers. A valuable introduction to the concept of a microprocessor-based digital filter may be achieved through the study of a simple DSP system based on a common and inexpensive microprocessor, and in this context an illustrative example is presented below.
x(n - M)
aM~l~~ y(rl)
Example system The transfer function of the denormalized second-order Butterworth low-pass filter is
ao
Figure 2.
FIR digital filter structure
2
°)ca
input signal must be less than half of the sampling frequency value, fs = lIT. This is necessary to prevent aliasing errors, which result when the sampling theorem is violated. For example, it would be futile to sample a voice signal at a rate of 4 kHz because the quality of the processed speech would be unacceptable. The sampling frequency would have to be increased considerably to improve the intelligibility of the s p e e c h - - a n 8 kHz sampling rate is typically used in telephone networks. In practice, the analogue input signal may pass through an antialiasing filter (analogue low-pass filter) before it is sampled, thereby ensuring that the sampling theorem is satisfied. Also, for some applications it is common practice to connect the DSP system D/A output to the input of a reconstruction filter to smooth the stepped form of the output waveform. Figure 3 shows a simplified block diagram of a typical DSP system.
G(S) = 52 + 21/2O)cas + COca2
(7)
taking the specification for a low-pass digital filter to be: cut-off frequency fed = 100 HZ; sampling frequency fs = 625 Hz (T = 1.6 ms); design to be based on the prototype second-order Butterworth low-pass filter in equation (7). The transfer function given by equation (7) may now be mapped from the s-plane to the z-plane using the bilinear z-transformation. However, a nonlinear frequency distortion (warping)is produced by the bilinear z-transform and must be taken into account in the design process by prewarping the s-plane frequency scale. To achieve this the cut-off frequency is calculated using equation (8). Oca = ~ tan
(8)
where oca is the radian prewarped cut-off frequency of the denormalized analogue filter, mcd is the specified radian cut-off frequency of the digital filter and T is the sampling period. Substituting the specific parameters in equation (8) yields
MICROPROCESSOR-BASED DSP SYSTEMS Microprocessors offer an attractive low-cost form of implementation for some DSP applications, and in recent years they have grown in popularity as design engineers have become more experienced in microprocessor system design. They are worthy of consideration because the sophistication of the microprocessor chip has advanced considerably, and because improved support chip functions have enhanced the processing capability of microprocessor systems. Furthermore, reliable support facilities for hardware and software development are readily available, and the amount of time required to gain familiarity with and proficiency in system design and implementation is not too large. Many reference sources exist for most microprocessors, a fact that is particularly reassuring to anyone engaged in DSP system design for the first time, especially students
O~ca= i.6 x2.10_ 3tan
200n X
= 687.2 rad s -1 The next step in the design is to substitute this value of 0)ca in equation (7), thereby producing the prewarped transformed transfer function G(s)pwt. Thus G(s)pwt
472243.84 s 2 + 971.85s + 472243.84
(9)
For the bilinear z-transform we use the substitution s
2 z-1 T
RAM/ROM]
~ Antialiasing filter
I,
A/D
Programmable x(n) digital ~--
Analogueinput signal,x(t) Figure 3.
nrn~mr
y(n)
D/A
y*(t)
~-
Reconstruction filter O ~
Analogueoutput signal,y(t)
Block diagram of a typical DSP system
Vol 11 No 3 April 1987
133
and for the specified value of T this gives (10)
s = 1 2 5 0 \ , z + 1, Substituting equation (10) in equation (9) gives z 2 + 2z + 1
Y(z)
(11)
CU
I +2z-1+z-2
= 6.88 - 4.62z -1 + 1.74z -2
x(n)
Since z -d implies a time delay of d sampling periods it follows that
,(n)
~ . ~ A/D converter~ ~ P I A /] D/A(ZN435) c°nverterO upt~ut 0uTI ,zN.8 I - I ,6.2t, '-D"/ I signal, signal,~ ~ CA2
X(z) + 2X(z)z -1 + X(z)z -2 transforms to
x(t) ~
x(n) + 2x(n - 1) + x(n - 2)
y*(t)
~
and 6.88Y(z) - 4.62Y(z)z -1 + 1.74Y(z)z -2 transforms to
oZ-LF
6.88y(n) - 4.62y(n - 1) + 1.74y(n - 2) Therefore the linear difference equation corresponding to equation (11)is equation (3). In this example the poles of G(z) and the roots of the denominator polynomial in equation (11) are a complex conjugate pair at z = 0.336 +_j0.374 which lie within the unit circle in the z-plane, thereby yielding a stable filter. The processor word length required to maintain stability, assuming truncation rather than rounding of the bi filter coefficients, may be determined using the method reported by Kuo and Kaiser22, i.e. for a pth-order filter having distinct poles at (cos ¢OkT- j sin 0~kT), where k is an integer in the range p ~>k ~> 1, the number of processor bits w must be w = smallest integer exeeding
r 5pV2 k=l P
(12)
Evaluating equation (12) for the complex conjugate poles obtained from equation (11) yields w = 2. This is not a surprising result considering that the poles are located well away from the circumference (stability boundary) of the unit circle. Note that there is no guarantee that with this value of w the filter will produce its specified frequency response characteristic. A rule of thumb is generally employed whereby four or five bits are added to w to take account of quantization and computational errors. Consequently, for this example it is appropriate to consider implementation using an 8-bit word length. An appropriate 8-bit microprocessor-based digital filter configuration is shown schematically in Figure 4. The flowchart for the filter implementation is shown in Figure 5. In computing y(n), the product terms in the equation involve evaluating the multiplication of two 8-bit binary numbers, thereby producing a 16-bit result which would normally be rounded or truncated and represented by the most significant eight bits. This obviously introduces computational errors which may degrade filter performance. In this example, with 8-bit representation, the rounding or truncation effect is insignificant because the poles of the filter are located well away from the circumference of the unit circle, and a considerable
134
Figure4. system
Convert command signal Status ignal
Block diagram of 6802-based digital filter
change in the representation of the product terms would be required to cause a significant degradation of the filter frequency characteristics. The performance of the digital low-pass filter may be demonstrated by using a square wave input test signal having a period Tp and defined by the following Fourier series:
x(t)=A0+-
n
cosmlt--cos3~lt+-cos5mlt-... 3 5
where c0~ = 2n/Tp. The considerable attenuation of the high-frequency nth odd harmonic components (of the form 1/n cos naht) in the input signal, resulting from the filtering process, produces an output signal y(t) which is a reasonable approximation to a sinusoidal signal having a predominant fundamental component equal to the fundamental frequency of the input signal, that is 2
y(t) ~ A o + - cos (01t n
Figure 6 shows the output waveform y(t) resulting from the implementation of the digital low-pass filter linear difference equation, equation (3), using the test signal x(t) defined above.
Switched capacitor filters Programmable low-pass and high-pass switched capacitor filters (SCFs) are compatible with microprocessors, and are increasingl)[, being used to implement signal filtering operations23, 2.. The basic principle of operation of an SCF relies on small capacitors switched between circuit nodes at high rates to create corresponding equivalent circuit resistances.
Microprocessors and Microsystems
Consider the CMOS circuit shown in Figure 7 with switch $1 closed at time t = 0 and switch $2 open; the charge on the capacitor is then CV1. If switch $1 is opened and switch $2 closed after time T, then the charge changes to CV2. Since the average current i transferred between nodes V~ and V2 is equal to the rate of change of charge, we may write i - C(Vl - V2) T
Initialize stack pointer
Clear:
x(n - 1) x(n - 2) y(n-2) y(n-2)
Initialize PIA
convert command signal
Generate
for interrupt
t Yes Input x(n) Compute y(n) Outputto D/A y(n y(nx(n x(n -
Figure 5.
interrupt routine
2) = y(n - 1) 1)=y(n)
2) =x(n - 1) 1) =x(n)
Flowchart for 2 n d - o r d e r digital filter
but resistance R = (Vl - V2)/i = TIC = 1/(Cfs), where fs is the clock frequency. Therefore, since capacitors and transistor switches are readily implemented with CMOS technology, and because variable digital clock circuits may be easily fabricated, the SCF circuit provides an effective means of achieving a corresponding variable RC network performance. All circuit nodes must settle between the switched samples, and the maximum useful frequency is therefore limited by the settling time of the associated operational amplifier integrators. Settling to 0.1% is achievable within 1 ~s, but in practice filters have a maximum internal clock of about 400 kHz, thereby allowing 2.5 gs for the nodes to settle. For a typical low-pass filter the maximum cut-off frequency is about fs/20, i.e. approximately 20 kHz, and it is normal practice to use an antialiasing filter with an SCF to ensure that the sampling theorem is obeyed. Also it is appropriate to connect a reconstruction filter to the SCF output to smooth the stepped output arising from the switching action. Figure 8 shows a Gould AMI Semiconductors $3528 CMOS programmable switched-capacitor low-pass filter 24, which provides an accurate and flat frequency response in the passband (ripple less than _+ 0.1 dB) and stopband rejection greater than 51 dB for f > 1.3 fc, where fc is the cut-off frequency of the filter. In dynamic applications (adaptive filtering) a microprocessor may be used to select and change any one of a set of 64 different cut-off frequencies. The 6-bit data input word determines the selected filter cut-off frequency, and the application of an active-low chip enable pulse (minimum width 200 ns) latches in the data word. For example, an input code equal to 10 (hex.) sets the cut-off frequency to 1005 Hz, and if this is changed to 11 (hex.) the cut-off frequency correspondingly increases to 1105 Hz. A selection of loss curves for four different control codes is shown in Figure 9. Compared with the common form of microprocessorbased digital filter, the SCF form is much simpler to design (no s-plane to z-plane transformation needed) and can deal with a wider range of baseband signal frequencies. Node voltage
Figure 6. Waveforms for illustrative example: top, i n p u t signal, x(t); middle, o u t p u t signal from D / A converter, y*(t); b o t t o m , o u t p u t from reconstruction filter, y(t)
Vol 11 N o 3 April 1987
Node voltage Figure 7.
C M O S switched-capacitor circuit
135
Antialiasing filter
I
!
I
J 10
Input signal,x(t)
~
pCe'ter
Seventh-order elliptical low-passfilter
3.58 MHz 11-stage programmable divider
Smoothing filter
-12 1
18 17 16
Microprocessor (6802) Data bus
6-bit latch Output signal, y(k)
D5 (S3528)
4
E
I Addressdecode l logic
Addressbus
Figure 8.
Programmable 53528 switched-capacitor low-pass filter
However, for continuously variable dynamic control of the frequency response characteristic, the common form of linear difference equation implementation using a microprocessor-based system is more precise than the stepped change achievable with the SCF device.
DSP
CHIPS
The first DSP chip was the Intel 29208 , which was launched in 1979. It possessed on-chip data converters, but it lacked an on-chip multiplier and its instruction set was limited. The anticipated market for the 2920 was never achieved, but fortunately this did not deter other companies from developing their own DSP chips. In 1980 NEC introduced the pPD77208,11 DSP chip. This incorporated a 16 bit x 16 bit multiplier and a 16-bit twos complement ALU; this combination permitted the implementation of a sum-of-products operation (see equation (6)) in a single instruction cycle (250 ns). At about the same time as the development of the NEC DSP chip, the implementation of an MOS integrated circuit for digital filtering was achieved at British Telecom Research Laboratories. This chip, known as FAD (filter and detect)12, 2s, requires a single-phase clock and very little external circuitry to implement a digital filter (see Figure 10). The FAD chip is now manufactured and marketed by Plessey Semiconductors as the MS2014FAD device. It is interesting to note that Plessey has recently launched other DSP products designed using its Megacell semicustom design methodology and manufactured in 2 pm CMOS. The first two members of the chip family are
136
the two-dimensional edge detector (PDSP16401) and the 16 X 12 bit complex number multiplier (PDSP16112). Texas Instruments has had remarkable success with its TMS320 family of DSP chips, the first member of which (TMS32010) was launched in 1983. The TMS32010 is a microcomputer with a 32-bit internal Harvard architecture and a 16-bit external interface capable of executing 5M instructions per second. The next significant development was the production of the TMS32020 DSP chip. This had a
0 10 20
~ 3o 0
~
40
50 60 70 0
I
I
1
1
2
3
Frequency(kHz) Figure 9. Selection of loss curves produced by the switched-capacitor low-pass filter
Microprocessors and Microsystems
FUTURE TRENDS (MS20141
Filte CLK
C
2.048MHz
clock
NR
R
t' ICLK
IQA Binary I counter IQE Figure 10.
r in
SYNC
I
J
-~-
DO
D1
A0 I[32RoMX 2 bit
-_1
I A41
Block diagram of a typical FAD filter
number of improvements over the 32010 to make it more suitable for multiprocessing DSP implementations; in particular the 32020 permits synchronization of the multiprocessing task and includes a serial port, DMA capability and a global data memory interface. A further addition to the TMS320 range was the TMS302C2526, a pin-compatible CMOS version of the 32020 chip with a faster instruction cycle (100 ns) and more on-chip memory. The 320C25 instruction set supports adaptive filtering, extended-precision arithmetic, bit-reversed addressing and faster I/O for data-intensive signal processing. Following the successful introduction of the early DSP chips many manufacturers have been active in developing and marketing their own devices; those known to the author are listed in Appendix I. A recent novel DSP device development has been introduced by Inmos in the form of the IMS AI00 cascadable signal processor. In designing this chip Inmos looked at the most widely used signal processing algorithms and concentrated on the associated structured evaluation tasks, such as the common repeated multiplication and accumulation operations involved in the linear difference equation. It was evident that the speed of the multipliers and the memory bandwidth were the main factors limiting the rate of data throughput. Consequently Inmos reappraised the classical processor architectural structures to see whether such limiting factors could be minimized by innovative architectures and by exploiting the high packing densities of today's chip fabrication processes. The result was a transversal architecture implemented as a dataflow machine, with each node comprising a multiplier-accumulator unit and local store. The resulting IMSA100 device is cascadable to produce transversal filters of several thousand stages with high numerical accuracy and no degradation in throughput (see Figure 111. The use of a medium-speed microprocessor and one or more A100 devices (Figure 11) results in a very highperformance system. For example, two A100s controlled by a host microprocessor can perform a 1024-point complex discrete Fourier transform in less than 10 ms. Performance increases almost in proportion to the number of A100s used, and therefore this form of DSP system is capable of realizing throughputs previously only possible with bit-slice systems.
Vol 11 No 3 April 1987
The emergence of VLSI microelectronics technology and computer-aided design methodologies have given rise to significant developments in DSP and VLSI signal processing. However, it would be foolish to expect all further advances to emerge solely from improvements in device fabrication techniques. In fact it has been predicted that before 1990 we should expect little more than a 20-fold improvement in the functional throughput rate of VLSI chips. Consequently it is expected that the major significant advances will be achieved from the development of novel architectural structures and the efficient implementation of parallelism in the computational processes. Designers have had to produce improved processor architectures. Notably, the classical sequential processing strategy (von Neumann architecture) has been replaced by the more efficient parallel processing form (Harvard architecture), thereby increasing the speed of data handling and computations. The Motorola DSP56000 device architecture, for example, has been designed to maximize throughput in data-intensive DSP applications. This objective has been realized by the provision of two independent expandable data memory spaces, two address arithmetic units and a data ALU which has two accumulators and two shifter-limiters. This duality of the device architecture facilitates efficient writing and execution of software for DSP applications. Research has shown that parallel processing architectures with highly attractive and promising characteristics for utilizing VLSI technology may arise from a combination of systolic and wavefront architectures27, 28 A systolic system may be configured using an array of processors operating in a rhythmical manner to perform the computations and transmission of data for the desired signal processing operation. All of the processing elements use common control (timing) signals and simultaneously perform the same function on different sampled-data values. The systolic array therefore exhibits modularity, regularity and local interconnection synchronized pipelined multiprocessing, and offers remarkable potential for improved architectures for future DSP chips and VLSI signal processing 29-31.
CONCLUDING REMARKS This paper has attempted to illustrate some of the main concepts of microprocessor-based signal filters, and several forms of implementation have been reviewed. In Go
Clock
Data-~ IMSAIO0 I
IMSAIO01-- *SA,OO a
I
I
Microprocessor [ Figure 11.
Cascaded/MS A l O0-based DSP system
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particular, the intention has been to make the reader more aware of the availability of microprocessor-based signal filters, and of the range of devices now commercially available for DSP applications. Readers requiring further information should consult the manufacturers and suppliers listed in Appendix 1.
REFERENCES 1 Mesko, A Digital filtering applications in geophysical exploration for oil Pitman, London, UK (1984) 2 Brislow, G Electronic speech synthesis Granada, London, UK (1984) 3 Bellanger, M Digital processing of signals: theory and practice John Wiley, New York, USA (1984) 4 Katz, P Digital control using microprocessors PrenticeHall, Englewood Cliffs, NJ, USA (1981) 5 Willey, T 'Network testing using DSP' New Electron. (1 October 1985) pp 33-34 and 38 6 Fair, D and Windsor, B 'CMOS DSP components target new military applications' Defense Electron. (April 1986) pp 105-106, 109, 112, 114 and 116 7 Duval, I and Niehaus, I 'Pipelined bit-slice architecture eases FFT implementation' EDN (27 October 1983) pp 215-224 8 Quarmby, D Signalprocessor chips Granada, London, UK (1984) 9 Dettmer, R'Digital signal processors' Electron. Power (February 1986) pp 124-128 10 Terrell, T J and Simpson, R J 'Digital filtering using the Intel 2920 signal processor' Int. J. Elec. Engng, Educ. Vol 18 (1981) pp 211-224 11 Simpson, R J and Terrell, T I 'Digital filtering using the N EC PD7720 signal processor' Microproc. Microprog. Vol 14 (1984) pp 67-78 12 'Digital signal processing with the MS2014 FAD' Electron. Product Des. (May 1986) pp 49-56 13 Marven, C 'Second generation DSP expands into new domains' New Electron. (3 September 1985) pp 30, 33-34, 37 14 Rabiner, L R and Gold, B Theory and application of digital signal processing Prentice-Hall, Englewood Cliffs, N J, USA (1975) 15 Oppenheim, A V and Schafer, R W Digital signal processing Prentice-Hall, Englewood Cliffs, N], USA (1975) 16 Antonious, A Digital filter analysis and design McGrawHill, New York, USA (1979) 17 Terrell, T l Introduction to digital filters Macmillan, London, UK (1980) 18 Taylor, F I Digital filter design handbook Marcel Dekker, New York, USA (1983) 19 Williams, C S Designing digital filters Prentice-Hall, Englewood Cliffs, NJ, USA (1986) 20 Tustin, A 'A method of analysing the behaviour of linear systems in terms of time series' J. lEE Vo194 Part IIA (1947) pp 130-142 21 Grant, P M and Cowan, C F N 'Design and application of adaptive filters' Electron. Power (February 1985) pp 157-163 22 Kuo, F F and Kaiser, J F Systems analysis by digital computer John Wiley, New York, USA (1966) 23 Connor, J 'Filters mate with microprocessors' Electron. Product Des. (January 1985) pp 39-42 24 Gould AM I Semiconductors Programmable Iowpass
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lrevor Terrell is a professor in the School of Electrical anc] Electronic Engineering, Lancashire Polytechnic, UK. From 1969 to 1972 he attended the University of Manchester Institute of Science and Technology, obtaining an MSc in 1970 and a PhD in 1972. In 1972 he was appointed as a lecturer in the Electrical Engineering Department of Preston Polytechnic (now Lancashire Polytechnic). His research interests include digital signal and image processing, and the application of microprocessors in digital control systems. Since 1974 he has been a chartered engineer and he is a fellow of the Institution of Electrical Engineers.
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26 27 28 29 30 31
filter product description: $3528 (April 1984) and Programmable highpass filter product description: $3528 (June 1984) Adams, P F, Harbridge, J R and Macmillan, R H 'An MOS integrated circuit for digital filtering and level detection' IEEE J. Solid-State Circuits Vol SC-16 No 3 (June 1981) pp 183-190 TMS320C25 digital signal processor product description Texas Instruments, Bedford, UK (1986) Kung, H T 'Systolic arrays for VLSI' in Duff, I S and Stewart, G W (Eds) Sparse matrix proceedings SIAM, Philadelphia, PA, USA (1979) Kung, S Y etal. 'Wavefront array processor: language architecture and application' IEEE Trans. Comput. (November 1982) pp 1054-1066 Kung, S Y, Whitehouse, H l and KaUath, T VLSI and modern signal processing Prentice-Hall, Englewood Cliffs, NJ, USA (1985) Swartzlander, E E Jr VLSI signal processing systems Kluwer, Hingham, MA, USA (1986) Denyer, P and Renshaw, D VLSI signal processing: a bit-serial approach Addison-Wesley, Wokingham, U K (1985)
APPENDIX 1: MANUFACTURERS A N D SUPPLIERS OF DSP DEVICES Advanced Micro Devices (UK) Ltd AMD House, Goldsworth Road, Woking, Surrey GU21 1JJ, UK. Tel: (04862) 22121 29500 signal processor family (1982): a bit-slice architecture for DSP and array processing operations; benchmark: 1024-point complex FFT in approximately 2 ms
American Microsystems Inc. 3800 Homestead Road, Santa Clara, CA 95051, USA. Tel: (408) 246-0330 528211 signal processor family (1982): architecture pipelined to perform a read, multiply and accumulate with each 300 ns instruction cycle
Analog Devices Ltd Central Avenue, East Molesey, Surrey KT8 OSN, UK. Tel: 01-941 0466
Microprocessors and Microsystems
ADSP-2100 (1986): a programmable single-chip microprocessor for DSP and high-speed numeric processing applications; benchmark: 1024-point complex FFT in 7.2 ms
Burr-Brown PO Box 11400, Tucson, AZ 85734, USA. Tel: (602) 746-1111
point and floating-point arithmetic when data word values exceed 16 bit
Inmos Ltd 1000 Aztec West, Almondsbury, Bristol BS12 4SQ, UK. Tel: (0454) 616616
MPV960 (1985): configured around the Burr-Brown ADC84 12-bit A/D converter and the TMS320 DSP chip; provides high-speed analogue input with DSP on a VMEbus board
IMS A100 cascadable CMOS signal processor (1986): contains an array of 32 high-speed, high-accuracy, 16 x 16 bit multiplier-accumulators, plus registers and control logic, in a dataflow architecture to implement a digital transversal filter; benchmark: two A100s can achieve a 1024-point complex DFT in less than 2 ms
Calmos Systems 20 Edgewater Street, Kanata, Ontario, Canada K2L lV8. Tel: (6•3) 836-1014
Intel Corp. 5000 W Williams Fields Road, Chandler, AZ 85224, USA. Tek (602) 961-2000
CA128X16 FIR filter DMCU (1985): a building block for implementing FIR filters of orders from 1 to 128 ponts; when used in conjunction with an external filter coefficient memory and a multiplier-accumulator the data memory and control unit (DMCU) provides an FIR filter implementation with four ICs
2920 NMOS signal processor (1979): the first DSP chip, not now widely available
Euroka Oy Hameenite 155 C52a, 00560 Helsinki, Finland. Tek (358-0) 799522 SPU292 signal processing module: based on the Intel 2929 and designed to provide a microcomputer system with analogue signal processing capability, i.e. for DSP applications
I'I-IF Semiconductors Intermetall, 145-147 Ewell Road, Surbiton, Surrey KT6 6AW, UK. Tel: 01-390 6577 UDP101 CMOS digital signal processor (1984): a maskprogrammable device which has a multibus structure; uses pipelined program execution and the basic multiply and add instruction is implemented in 200 ms
Logic Devices Inc. Abacus Electronics Ltd, Abacus House, Bone Lane, Newbury, Berks RG14 5SF, UK. Tel: (0635) 33311
Fujitsu Amber Components Lid, Rabans Close, Aylesbury, Bucks HP19 3RS, UK. Tel: (0296) 34141
LSH32 32-bit cascadable barrel shifter-normalizer (1986): a high-speed shifter for use in floating-point normalization, word pack/unpack, field extraction and similar DSP applications
MB8764 general-purpose CMOS digital signal processor (1985): features a high-speed pipelined multiplier, supports concurrent operations with compound instructions and multiple data paths, and offers flexible and expandable memory options and an on-chip DMA channel; benchmark: 512-point FFT in 16 ms
Loughborough Sound Images Lid The Technology Centre, Epinal Way, Loughborough, Leics LE11 OQE, UK. Tel: (0509) 231843
General Instrument Microelectronics Lid Times House, Ruislip, Middx HA4 8LE, UK. (08956) 36141 DSP320C10-25 CMOS digital signal processor (1986): a 25 MHz device based on a pipelined architecture, and capable of executing 6.25 MIPS
Gould AMI Semiconductors AMI House, 56-58 Prospect Place, Swindon SN1 3JZ, UK. Tel: (0793) 37852 $7720 digital signal processor (1984): an advancedarchitecture microcomputer optimized for signal processing algorithms; benchmark: 64-point complex FFT in 1.6 ms
Hitachi Electronic Components (UK) Ltd 21 Upton Road, Watford, Herts WD1 7TP, UK. TeE (0923) 46488 HD61810B digital signal processor (1985): has a floatingpoint multiplier and a fixed-point/floating-point ALU, and can process signals over a dynamic range up to 32 bit, achieved via the automatic switching between fixed-
Vol 11 No 3 April 1987
TMS320 board (1986): IBM PC plug-in for the development of DSP applications using the TMS32020 device
Motorola Ltd Semiconductor Products Group, Colvilles Road, Kelvin Estate, East Kilbride, Glasgow G75 OTG, UK. Tel: (0734) 787848 DSP56000 family of DSP chips (1986): includes generalpurpose, algorithm-specific, application-specific and building-block parts; the DSP56000 device is capable of executing 10.25 MIPS and is suitable for general-purpose use; the DSP56200 device is a cascadable adaptive FIR filter, suitable for echo cancelling, telephone line equalization and other DSP applications
Mullard Lid Mullard House, Torrington Place, London WC I E 7HD, UK. Tel: 01-580 6633 SP50 family of CMOS DSP devices (1986): the PCB5011 is a ROMless version of the PCBS010 DSP device with a highly parallel Harvard architecture; it has a 16 x 16 bit hardware multiplier aided by a barrel shifter and format adjuster; benchmark: 16-point complex FFT in under 30 lus (excluding initialization procedures)
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National Semiconductor (UK) Ltd The Maple, Kembrey, Park, Swindon, Wilts SN2 6UT, UK. Tel: (0793) 614141 LM32900 digital signal processor (1986): CMOS microprocessor optimized for DSP operations; it uses a pipelined Harvard architecture and a multiply and add/ substract operation can be executed in 200 ns
NEC Electronics (UK) Ltd Block 3, Carfin Industrial Estate, Motherwell ML1 4UL, UK. Tel: (0698) 732221 PD7720 digital signal processor (1980): uses a Harvard architecture and a multiply operation (16 × 16 bit) can be implemented in 250 ns; benchmark: FFT radix-2 butterfly in 91as
SDF family of digital filter building blocks (1981 ): a range of modules for various digital filter applications; for example, a single-pole high-pass filter with four selectable cut-off frequencies is provided by the SDF5208S module, and it may be operated with a sampling rate up to 15 MHz
STC Components Ltd Semiconductors Division, Maidstone Road, Sidcup, Kent DA14 5HT, UK. Tel: 01-300 3333 DSP128 digital signal processor (1984): a cascadable integrated signal processor (CRISP) which may be connected on a common bus for efficient implementation of multiprocessing tasks; it may also be used as a standalone processor or be interfaced to a generalpurpose microprocessor; benchmark: 64-point complex radix-2 FFT in 1.5 ms
Plessey Semiconductors Ltd Cheney Manor, Swindon, Wilts SN2 2QW, UK. Tel: (0793) 36251
Texas Instruments Manton Lane, Bedford MK41 7PA,UK. Tek (0234) 223000
MS2014FAD (1985), PDSP16401 (1986) and PDSP16112 (1986) digital signal processing chips: the MS2014FAD is a building block for implementing digital filters; the PDSP16401 is a two-dimensional edge detector; and the PDSP16112 is a 16 x 12 bit complex number multiplier
TMS320 family of digital signal processors (1983): a combination of a general-purpose single-chip microprocessor architecture with an ALU and multiplier, resulting in a 32-bit internal Harvard architecture capable of 5 MIPS; benchmark for the TMS320C25: 256-point complex FFT (radix-2 loop-coded) in 3.44 ms
Pye TMC Ltd Commercial Division, Martell Road, West Dulwich, London SE21 8EF, UK. Tel: 01-670 2211
Thomson Semiconducteurs Ringway House, Bell Road, Daneshill, Basingstoke, Hants RG24 OQG, UK. Tel: (0256) 29155
TMC539A PMOS dual second-order digital filter (ca. 1980): the filter sections are independent and may be used separately as a complete biquadratic, or they may be cascaded to form higher-order filters; sampling frequencies up to 16 kHz are practical
TS68930 programmable signal processing integrated VLSI (1986): a high-speed general-purpose signal and arithmetic processor with a parallel/pipeline architecture to simultaneously execute one ALU function, multiplication, two reads and one write operation and associated address calculation every 160 ns; benchmark: 256-point complex FFT in 2 ms
Reticon Corp. 910 Benicia Avenue, Sunnyvale, CA 94086, USA. Tel: (408) 738-4266 TAD32 tapped analogue delay (1977): a charge transfer device with 32 taps for implementing transversal filters; sampling rates up to 5 MHz are possible
Spectrum Devices Ltd Central Avenue, East Molesey, Surrey KT8 0SN, UK. Tel: 01~941 2708
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TRW Electronic Components Group 75-17 High Street, Bedford MK40 1RU, UK. Tel: (0234) 217711 TDC1028 and TMC2243 FIR Filters (1985): the TDC1028 can be clocked at a rate up to 10 MHz and it implements an eight-tap FIR filter, whereas the TMC2243 can be clocked at a faster rate of 20 MHz and it implements a three-tap FIR filter
Microprocessors and Microsystems