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Ge ohmic contacts to n-type GaAs formed by rapid thermal annealing
__ __ B
2%
applied
surface science
ELSEVIER
Applied Surface Science 100/101
(1996) 530-533
Microstructure studies of PdGe/Ge ohmic contacts to n-type GaAs formed by rapid thermal annealing W.D. Chen *. X.L. Xie, Y.D. Cui, C.H. Chen, C.C. Hsu Insrirure of Semiconductors and State Key Laboratory for Surface Physics. Chinese Academy of Sciences. P.0. Box 912. Beijing 100083. China
Received
15 August
1995; accepted
I I December 1995
Abstract A low resistance and shallow ohmic contact to n-GaAs is performed by using Ge/Pd/GaAs trilayer structure and rapid thermal annealing process. The dependence of specific contact resistivity on the temperature of rapid thermal annealing is investigated. A good ohmic contact is formed after annealing at 400-500°C for 60 s. The best specific contact resistivity is 1.4 X 10m6 R cm’. Auger electron spectroscopy (AES), secondary ion mass spectrometry (SIMS) and scanning electron microscopy (SEM) are used to analyze the interfacial microstructure. A strong correlation between the contact resistance and the film microstructure is observed.
1. Introduction The Au-Ge-Ni system has been extensively used as the ohmic contact to n-type GaAs. However, with device dimensions decrease the metallization system becomes inadequate for shallow junction devices and large scale integration due to the complex alloying process. This metallization often results in a nonplanar interface morphology [1.2] and formation of the low melting point P-AuGa phase that leads to poor thermal stability [3]. Recently, various materials for the preparation of low resistance and thermal stable ohmic contacts have been investigated. Among these materials, Pd/Ge can provide ohmic contacts with
’ Corresponding 2562389.
Tel.:
Copyright SO169-4332(96)00334-O
0169.4332/96/$15.00 PII
author.
+ 86-10-1558131;
fax: 86-10.
low specific contact resistivity similar to that obtained in a AuGeNi contact system, and with uniform and planar interface. Due to the improved features the Pd/Ge contact is suitable for submicrometer device or integrated circuit fabrication. Furnace annealing at 325°C for 30 min is usually used to form Pd/Ge ohmic contacts [4]. Recently the rapid thermal annealing (RTA) process was used for forming ohmic contacts [s]. In this work, the dependence of specific contact resistivity on rapid thermal annealing temperature is investigated. In order to search for a microstructure of the Pd/Ge ohmic contacts formed by RTA. the contact depth profile is studied by Auger electron spectroscopy (AES) and secondary ion mass spectrometry (SIMS). The surface and interface morphology of Pd/Ge contacts before and after annealing are observed by scanning electron microscopy (SEMI.
0 1996 Elsevier Science B.V. All rights reserved.
531
W.D. Chen er al. /Applied Surface Science lOO/ IO1 (19%) 530-533
2. Experimental A semi-insulating GaAs substrate with (100) orientation was used as the starting wafer. A 2 pm n+ GaAs epitaxial layer was grown on top of the wafer by vapor phase epitaxy (VPE). The epitaxial layer was doped with Si (3 X 10” cm-j). Specific contact resistivity (p,) was measured by transmission line model (TLM) analysis. The wafer was coated with SiO, layer of 0.2 pm thickness and a photoresist stencil was applied TLM test structure that was patterned by mesa etch using H,S0,:H,02:H,0 solution. Prior to metal deposition, the wafers were chemically cleaned by using buffered HCI. Pd (50 nm) and Ge (125 nm) were deposited sequentially by electron beam evaporation in high vacuum system (lop7 Pa). Then a Pd/Ge/GaAs structure was formed. The contact region was defined by a lift-off process. Separate ohmic contact samples on bulk n+ GaAs (100) substrate (Si doped. - 3 X lOI cm- ‘) were used for AES, SIMS and SEM analysis. All samples were annealed by rapid thermal annealing in N2 ambient in the temperature range of 350-700°C for 30 and 60 s. The contact depth profile was measured by AES (@610) and SIMS. SIMS was performed in a MIQI.56 system at a base pressure of I X IO-’ Pa. The projectile beam was Cs+ with an energy of 10 keV and beam current of 20 nA. The beam was rastered over an area of 900 x 500 km. The diatomic ejected ions CsXc were selected and recorded for monitoring distributions of elemental concentration with depth in materials.
60
Second
Anneal Temprature “C Fig. I. Specific contact resistivity as a function of annealing temperature. The annealing time is 60 s.
most of pc are on the order of 10m6 R cm’. It can be seen clearly that the ohmic behavior begins to be observed at 400°C and the p, value decreases with increasing the annealing temperature. The lowest value of 1.4 X 1O-6 0 cm’ is obtained at 425°C. At this temperature the average value is 3.4 X lop6 R cm’. With increasing temperature, an increase of the pc values and typical U-shape dependence of pc on T is observed. The dependence of pc on T is also measured for 30 s annealing at various temperatures. In the region between 425-500°C though good ohmic behavior can be obtained, the lowest value of p, is 4.7 x lop6 fl cm’ at 425°C there are higher values of p, compared with that at the same temperature for 60 s. 3.2. Auger depth profiles
3. Results 3.1. Contact resistirlit?, measurement Fig. 1 shows the specific contact resistivity (p,) of samples that are annealed for 60 s at various temperatures. The top and bottom of each vertical line correspond to the maximum and minimum values of five datum-points. The solid line shows the average values. Ohmic contact behavior is not observed when the samples were annealed below 400°C. Only a few datapoints show ohmic behavior between 525-650°C. In the region between 425 and 500°C.
From the depth profile of the as-deposited Pd/Ge contact measured by AES (not shown), it is clear that the raw data give a good representation of the actual compositional profile of Ge/Pd/GaAs trilayer structure. It should be noted that the Pd/Ge interface is abrupt, but the Pd/GaAs interface is much broader than the Pd/Ge interface, which implies that interdiffusion or interaction took place at the Pd/GaAs interface during deposition. This is consistent with cross-sectional transmission electron microscopy (TEM) observations [4]. The depth profile after the RTA process at 400°C for 30 s indicates that all Pd has reacted with Ge and that a PdGe compound is
532
W.D. Chen et al/Applied
Surface Science lOO/ 101 (19%) 530-533
formed. The excess Ge still remains at the surface layer. Electrical measurement shows that the contact of Ge/PdGe/GaAs structure is not ohmic. The Auger depth profiles annealed at 425-500°C for 30 s or 400%500°C for 60 s are nearly the same. The typical depth profile is shown in Fig. 2 which indicates that the Ge originally existed on the upmost layer has been all transported to the PdGe/GaAs interface and a PdGe/Ge/GaAs structure is formed. The structure corresponds to ohmic contact. It is noted that there is almost no change of Pd/Ge contact depth compared with that of as-deposited Pd/Ge contact. This demonstrates that the ohmic contact is very shallow and there is nearly no observable penetration.
10’ 0.0
7.5 Sputter Time (min.)
15
Fig. 3. SIMS depth profile of the sample that is annealed at 425°C for 60 s.
3.3. SIMS depth profiles SIMS analysis is carried out for the as-deposited sample and a number of annealed samples. In the SIMS analysis, CsX’ signals were recorded because CsX+ would give a more reliable indication of X density and ‘artifacts’ associated with the matrix will be reduced [6]. SIMS depth profile of as-deposited Pd/Ge contact recorded by diatomic ejected ions CsX+ is clearly display a Ge/Pd/GaAs trilayer structure. The typical SIMS depth profile that corresponds to the structure with ohmic behavior is shown in Fig. 3. The result is nearly the same as the one measured by AES that is shown in Fig. 2, but it is important to notice from Fig. 3 that the Ga signal piles up in the contact layer. The Ga signal intensity in PdGe contact layer is increased by about two orders of magnitude compared to the as-deposited
sample. It is found that there is a correlation between the appearance of Ga signal pile-up and good ohmic behavior. This observation was also reported by Lai and Lee [5]. 3.4. Sur$ace and inte$ace
morpholog)
The surface and interface morphology of Pd/Ge contact before and after annealing are observed by scanning electron microscopy (SEMI. The surface of the as-deposited sample is very smooth. The interface morphology of Pd/Ge contact annealed at 425°C for 60 s is also observed by SEM. The interface between the contact layer and GaAs substrate is more planar than that of AuGeNi contact. The limited solid phase reaction is believed to be the primary reason for the observed planar interface.
4. Discussion
0
0
2
4
6
8
IO
12
14
16
Sputter Time (min) Fig. 2. AES depth profile of the sample that is annealed at 425°C for 60 s.
For as-deposited Ge/Pd/GaAs sample, it is found that the interface of Pd/GaAs is broader than that of Ge/Pd from AES and SIMS depth profiles. This implies that interaction or interdiffusion at Pd/GaAs occurs. TEM observation showed an intermediate Pd,GaAs phase that was produced at the Pd/GaAs interface for an as-deposited sample [7,8]. It is most likely the ternary phase Pd,Ga,. As (x * 4, _vu I> which is usually found to be Ga rich (y > 1). The Ga-rich compound would cause an excess of Ga
W.D. Chen et al/Applied
Surface Science 100/101
vacancies in the GaAs. AES depth profile of the sample annealed at 400°C for 30 s shows that all of the Pd has reacted to form PdGe compound. The excess Ge is still at the sample surface. The Ge/PdGe/GaAs does not correspond to ohmic contact. But for all samples annealed between 425500°C for 30 s or 400-500°C for 60 s, AES depth profiles show that the excess Ge has been all transported across the PdGe to the PdGe/GaAs interface. The PdGe/Ge/GaAs is formed. The structure corresponds with ohmic contact as shown by I-V measurement. Having been mentioned above, an intermediate Pd,GaAs phase was found at Pd/GaAs interface for as-deposited sample. It will cause an excess of Ga vacancies in the GaAs. SIMS analysis found that the Ga signal pile-up in the contact layer after annealing between 400-500°C for 60 s. This implies that GaAs dissociates and more Ga atoms outdiffuse into the contact layer. Hence more Ga vacancies in GaAs are produced. Ge deposited on the GaAs substrate may diffuse in and occupy Ga vacancies at doping levels, then the GaAs is doped. The appearance of the Ga pile-up means that a sufficient number of Ga vacancies are generated in GaAs and GaAs is heavily doped. Therefore. the contact layer exhibits good ohmic behavior. When the samples were annealed at 550-650°C for 60 s, most datum points show rectifying but a few are still ohmic. Though PdGe/Ge/GaAs trilayer structure is observed by AES depth profiles it is important to notice that the Ge/GaAs interface has been moved in about 2 min Ar+ sputtering distance. This means that not only Ga and As outdiffuse but also Ge and Pd indiffuse. The contact layer is completely destroyed during annealing at 700°C. In this case, the Ga and As atoms outdiffuse to the surface of the sample.
(1996) 530-533
533
5. Summary A low resistance and shallow ohmic contact to n-GaAs is formed by using Ge/Pd/GaAs structure and the rapid thermal annealing process. The specific contact resistivity of ohmic contact is N 10e6 fi cm’ after annealing at 425-475°C for 60 s, the best one is 1.4 X 10e6 0 cm’. AES and SIMS analysis shows that the ohmic contact is very shallow. SEM observation shows the excellent surface morphology and the planar interface for the PdGe/Ge contact. There is a correlation between the good ohmic contact and PdGe/Ge/GaAs trilayer structure as well as Ga pile-up in the contact layer.
Acknowledgements The research is supported by National Natural Sciences Foundation of China (NSF0 under contract No. 6939177003.
References [ll N. Braslau, J. Vat. Sci. Technol. 19 (1981) 803. [2] T.S. Kuan. P.E. Batson, T.N. Jackson. H. Rupprecht and EL. Wikie, J. Appl. Phys. 54 (1983) 6952. [3] M. Murakami, K.O. Childs. J.M. Baker and A. Callegari, J. Vat. Sci. Technol. B 4 (1986) 903. [4] E.D. Marshall. B. Zhang. L.C. Wang, P.F. Jiao, W.X. Xhen, T. Sawada, S.S. Law, K.L. Kavanagh and T.F. Kuech, J. Appl. Phys. 62 (1987) 942. 151 J.T. Lai and J.Y.M. Lee, Appl. Phys. Left. 64 (1994) 229. 161 E.W. Thomas and A. Toradi, Nucl. Instr. Meth. B 73 (1993) 214. 171 T. Sand, V.G. Keramidas, A.J. Yu, K.M. Yu, R. Gronsky and J. Washburn, Mater. Res. Sot. Symp. Proc. 54 (1986) 367. 181 A. Kobayashi. T. Sakurai, T. Hashizume and T. Sakata. J. Appl. Phys. 59 (1986) 3448.
2%
applied
surface science
ELSEVIER
Applied Surface Science 100/101
(1996) 530-533
Microstructure studies of PdGe/Ge ohmic contacts to n-type GaAs formed by rapid thermal annealing W.D. Chen *. X.L. Xie, Y.D. Cui, C.H. Chen, C.C. Hsu Insrirure of Semiconductors and State Key Laboratory for Surface Physics. Chinese Academy of Sciences. P.0. Box 912. Beijing 100083. China
Received
15 August
1995; accepted
I I December 1995
Abstract A low resistance and shallow ohmic contact to n-GaAs is performed by using Ge/Pd/GaAs trilayer structure and rapid thermal annealing process. The dependence of specific contact resistivity on the temperature of rapid thermal annealing is investigated. A good ohmic contact is formed after annealing at 400-500°C for 60 s. The best specific contact resistivity is 1.4 X 10m6 R cm’. Auger electron spectroscopy (AES), secondary ion mass spectrometry (SIMS) and scanning electron microscopy (SEM) are used to analyze the interfacial microstructure. A strong correlation between the contact resistance and the film microstructure is observed.
1. Introduction The Au-Ge-Ni system has been extensively used as the ohmic contact to n-type GaAs. However, with device dimensions decrease the metallization system becomes inadequate for shallow junction devices and large scale integration due to the complex alloying process. This metallization often results in a nonplanar interface morphology [1.2] and formation of the low melting point P-AuGa phase that leads to poor thermal stability [3]. Recently, various materials for the preparation of low resistance and thermal stable ohmic contacts have been investigated. Among these materials, Pd/Ge can provide ohmic contacts with
’ Corresponding 2562389.
Tel.:
Copyright SO169-4332(96)00334-O
0169.4332/96/$15.00 PII
author.
+ 86-10-1558131;
fax: 86-10.
low specific contact resistivity similar to that obtained in a AuGeNi contact system, and with uniform and planar interface. Due to the improved features the Pd/Ge contact is suitable for submicrometer device or integrated circuit fabrication. Furnace annealing at 325°C for 30 min is usually used to form Pd/Ge ohmic contacts [4]. Recently the rapid thermal annealing (RTA) process was used for forming ohmic contacts [s]. In this work, the dependence of specific contact resistivity on rapid thermal annealing temperature is investigated. In order to search for a microstructure of the Pd/Ge ohmic contacts formed by RTA. the contact depth profile is studied by Auger electron spectroscopy (AES) and secondary ion mass spectrometry (SIMS). The surface and interface morphology of Pd/Ge contacts before and after annealing are observed by scanning electron microscopy (SEMI.
0 1996 Elsevier Science B.V. All rights reserved.
531
W.D. Chen er al. /Applied Surface Science lOO/ IO1 (19%) 530-533
2. Experimental A semi-insulating GaAs substrate with (100) orientation was used as the starting wafer. A 2 pm n+ GaAs epitaxial layer was grown on top of the wafer by vapor phase epitaxy (VPE). The epitaxial layer was doped with Si (3 X 10” cm-j). Specific contact resistivity (p,) was measured by transmission line model (TLM) analysis. The wafer was coated with SiO, layer of 0.2 pm thickness and a photoresist stencil was applied TLM test structure that was patterned by mesa etch using H,S0,:H,02:H,0 solution. Prior to metal deposition, the wafers were chemically cleaned by using buffered HCI. Pd (50 nm) and Ge (125 nm) were deposited sequentially by electron beam evaporation in high vacuum system (lop7 Pa). Then a Pd/Ge/GaAs structure was formed. The contact region was defined by a lift-off process. Separate ohmic contact samples on bulk n+ GaAs (100) substrate (Si doped. - 3 X lOI cm- ‘) were used for AES, SIMS and SEM analysis. All samples were annealed by rapid thermal annealing in N2 ambient in the temperature range of 350-700°C for 30 and 60 s. The contact depth profile was measured by AES (@610) and SIMS. SIMS was performed in a MIQI.56 system at a base pressure of I X IO-’ Pa. The projectile beam was Cs+ with an energy of 10 keV and beam current of 20 nA. The beam was rastered over an area of 900 x 500 km. The diatomic ejected ions CsXc were selected and recorded for monitoring distributions of elemental concentration with depth in materials.
60
Second
Anneal Temprature “C Fig. I. Specific contact resistivity as a function of annealing temperature. The annealing time is 60 s.
most of pc are on the order of 10m6 R cm’. It can be seen clearly that the ohmic behavior begins to be observed at 400°C and the p, value decreases with increasing the annealing temperature. The lowest value of 1.4 X 1O-6 0 cm’ is obtained at 425°C. At this temperature the average value is 3.4 X lop6 R cm’. With increasing temperature, an increase of the pc values and typical U-shape dependence of pc on T is observed. The dependence of pc on T is also measured for 30 s annealing at various temperatures. In the region between 425-500°C though good ohmic behavior can be obtained, the lowest value of p, is 4.7 x lop6 fl cm’ at 425°C there are higher values of p, compared with that at the same temperature for 60 s. 3.2. Auger depth profiles
3. Results 3.1. Contact resistirlit?, measurement Fig. 1 shows the specific contact resistivity (p,) of samples that are annealed for 60 s at various temperatures. The top and bottom of each vertical line correspond to the maximum and minimum values of five datum-points. The solid line shows the average values. Ohmic contact behavior is not observed when the samples were annealed below 400°C. Only a few datapoints show ohmic behavior between 525-650°C. In the region between 425 and 500°C.
From the depth profile of the as-deposited Pd/Ge contact measured by AES (not shown), it is clear that the raw data give a good representation of the actual compositional profile of Ge/Pd/GaAs trilayer structure. It should be noted that the Pd/Ge interface is abrupt, but the Pd/GaAs interface is much broader than the Pd/Ge interface, which implies that interdiffusion or interaction took place at the Pd/GaAs interface during deposition. This is consistent with cross-sectional transmission electron microscopy (TEM) observations [4]. The depth profile after the RTA process at 400°C for 30 s indicates that all Pd has reacted with Ge and that a PdGe compound is
532
W.D. Chen et al/Applied
Surface Science lOO/ 101 (19%) 530-533
formed. The excess Ge still remains at the surface layer. Electrical measurement shows that the contact of Ge/PdGe/GaAs structure is not ohmic. The Auger depth profiles annealed at 425-500°C for 30 s or 400%500°C for 60 s are nearly the same. The typical depth profile is shown in Fig. 2 which indicates that the Ge originally existed on the upmost layer has been all transported to the PdGe/GaAs interface and a PdGe/Ge/GaAs structure is formed. The structure corresponds to ohmic contact. It is noted that there is almost no change of Pd/Ge contact depth compared with that of as-deposited Pd/Ge contact. This demonstrates that the ohmic contact is very shallow and there is nearly no observable penetration.
10’ 0.0
7.5 Sputter Time (min.)
15
Fig. 3. SIMS depth profile of the sample that is annealed at 425°C for 60 s.
3.3. SIMS depth profiles SIMS analysis is carried out for the as-deposited sample and a number of annealed samples. In the SIMS analysis, CsX’ signals were recorded because CsX+ would give a more reliable indication of X density and ‘artifacts’ associated with the matrix will be reduced [6]. SIMS depth profile of as-deposited Pd/Ge contact recorded by diatomic ejected ions CsX+ is clearly display a Ge/Pd/GaAs trilayer structure. The typical SIMS depth profile that corresponds to the structure with ohmic behavior is shown in Fig. 3. The result is nearly the same as the one measured by AES that is shown in Fig. 2, but it is important to notice from Fig. 3 that the Ga signal piles up in the contact layer. The Ga signal intensity in PdGe contact layer is increased by about two orders of magnitude compared to the as-deposited
sample. It is found that there is a correlation between the appearance of Ga signal pile-up and good ohmic behavior. This observation was also reported by Lai and Lee [5]. 3.4. Sur$ace and inte$ace
morpholog)
The surface and interface morphology of Pd/Ge contact before and after annealing are observed by scanning electron microscopy (SEMI. The surface of the as-deposited sample is very smooth. The interface morphology of Pd/Ge contact annealed at 425°C for 60 s is also observed by SEM. The interface between the contact layer and GaAs substrate is more planar than that of AuGeNi contact. The limited solid phase reaction is believed to be the primary reason for the observed planar interface.
4. Discussion
0
0
2
4
6
8
IO
12
14
16
Sputter Time (min) Fig. 2. AES depth profile of the sample that is annealed at 425°C for 60 s.
For as-deposited Ge/Pd/GaAs sample, it is found that the interface of Pd/GaAs is broader than that of Ge/Pd from AES and SIMS depth profiles. This implies that interaction or interdiffusion at Pd/GaAs occurs. TEM observation showed an intermediate Pd,GaAs phase that was produced at the Pd/GaAs interface for an as-deposited sample [7,8]. It is most likely the ternary phase Pd,Ga,. As (x * 4, _vu I> which is usually found to be Ga rich (y > 1). The Ga-rich compound would cause an excess of Ga
W.D. Chen et al/Applied
Surface Science 100/101
vacancies in the GaAs. AES depth profile of the sample annealed at 400°C for 30 s shows that all of the Pd has reacted to form PdGe compound. The excess Ge is still at the sample surface. The Ge/PdGe/GaAs does not correspond to ohmic contact. But for all samples annealed between 425500°C for 30 s or 400-500°C for 60 s, AES depth profiles show that the excess Ge has been all transported across the PdGe to the PdGe/GaAs interface. The PdGe/Ge/GaAs is formed. The structure corresponds with ohmic contact as shown by I-V measurement. Having been mentioned above, an intermediate Pd,GaAs phase was found at Pd/GaAs interface for as-deposited sample. It will cause an excess of Ga vacancies in the GaAs. SIMS analysis found that the Ga signal pile-up in the contact layer after annealing between 400-500°C for 60 s. This implies that GaAs dissociates and more Ga atoms outdiffuse into the contact layer. Hence more Ga vacancies in GaAs are produced. Ge deposited on the GaAs substrate may diffuse in and occupy Ga vacancies at doping levels, then the GaAs is doped. The appearance of the Ga pile-up means that a sufficient number of Ga vacancies are generated in GaAs and GaAs is heavily doped. Therefore. the contact layer exhibits good ohmic behavior. When the samples were annealed at 550-650°C for 60 s, most datum points show rectifying but a few are still ohmic. Though PdGe/Ge/GaAs trilayer structure is observed by AES depth profiles it is important to notice that the Ge/GaAs interface has been moved in about 2 min Ar+ sputtering distance. This means that not only Ga and As outdiffuse but also Ge and Pd indiffuse. The contact layer is completely destroyed during annealing at 700°C. In this case, the Ga and As atoms outdiffuse to the surface of the sample.
(1996) 530-533
533
5. Summary A low resistance and shallow ohmic contact to n-GaAs is formed by using Ge/Pd/GaAs structure and the rapid thermal annealing process. The specific contact resistivity of ohmic contact is N 10e6 fi cm’ after annealing at 425-475°C for 60 s, the best one is 1.4 X 10e6 0 cm’. AES and SIMS analysis shows that the ohmic contact is very shallow. SEM observation shows the excellent surface morphology and the planar interface for the PdGe/Ge contact. There is a correlation between the good ohmic contact and PdGe/Ge/GaAs trilayer structure as well as Ga pile-up in the contact layer.
Acknowledgements The research is supported by National Natural Sciences Foundation of China (NSF0 under contract No. 6939177003.
References [ll N. Braslau, J. Vat. Sci. Technol. 19 (1981) 803. [2] T.S. Kuan. P.E. Batson, T.N. Jackson. H. Rupprecht and EL. Wikie, J. Appl. Phys. 54 (1983) 6952. [3] M. Murakami, K.O. Childs. J.M. Baker and A. Callegari, J. Vat. Sci. Technol. B 4 (1986) 903. [4] E.D. Marshall. B. Zhang. L.C. Wang, P.F. Jiao, W.X. Xhen, T. Sawada, S.S. Law, K.L. Kavanagh and T.F. Kuech, J. Appl. Phys. 62 (1987) 942. 151 J.T. Lai and J.Y.M. Lee, Appl. Phys. Left. 64 (1994) 229. 161 E.W. Thomas and A. Toradi, Nucl. Instr. Meth. B 73 (1993) 214. 171 T. Sand, V.G. Keramidas, A.J. Yu, K.M. Yu, R. Gronsky and J. Washburn, Mater. Res. Sot. Symp. Proc. 54 (1986) 367. 181 A. Kobayashi. T. Sakurai, T. Hashizume and T. Sakata. J. Appl. Phys. 59 (1986) 3448.