389-405 © 1997 Elsevier Science Limited All rights reserved. Pnnted in Great Britain 0026-2692/97/$17.00 MicroelectronicsJourna128(1997)
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Microtechnologies for pH ISFET chemical sensors C. Can6, I. Gr cia and A. Merlos Centre Nacional de Microelectr3nica,IMB, CSIC, Campus UAB, E-08193 Bellaterra, Spain
A review of different microtechnologies for the fabrication ofpH ion sensitive field effect transistor (ISFET) sensors is presented. Integrated ISFETs are of interest due to the advantages of low price, fast response and small dimensions that they present compared to ISE electrodes. ISFETs can be also applied to the detection of different ions, using the proper sensitive membranes. A lot of work has been done during the last few decades to obtain commercial devices, and many technologies and structures can be found in the literature. In this paper, both front-side and back-side contacted devices are studied, in order to determine the compatibility of different processes, devices and materials with standard CMOS technologies, which seems to be a goal for present and future applications. © 1997 Elsevier Science Ltd.
Introduction he use o f small, reliable and inexpensive sensors for the determination o f p H is o f great interest in industrial processes and clinical analysis. Ion sensitive field effect transistors (ISFETs) are devices that have been developed for such purposes, using integrated circuit technologies to obtain advantageous sensors compared to standard non-integrated p H electrodes. The first ISFETs reported by Bergveld [1] consisted o f M O S transistors with the gate conductor replaced by the liquid under test. These had a channel conductance that varied with the p H o f the solution. Later, Matsuo et al.
T
[2] improved the device by using silicon nitride as the gate sensitive membrane, as shown in the cross-section o f Fig. 1. O w i n g to the contact with the liquid, that is biased, a protective material must be applied to the bonding area to cover metal pads and wires, in order to avoid leakage currents. ISFETs are not restricted to use only as H + ion sensors, as other ions can be detected if additional sensitive membranes are deposited over the inorganic membrane and in contact with the liquid. Despite the simplicity o f the structure, ISFETs present some limitations that are still not fully solved. Drifts o f the electrical parameters and difficult packaging are the main drawbacks due to the inherent contact o f the gate with the liquid. A lot o f w o r k has been carried out during the last two decades and solutions and applications have been reported. This paper reviews some interesting microtechnologies and processes that have been reported for improving ISFET features due to the importance o f these devices. Technological processes and solid state membranes for front-side and back-side contacted approaches are summarized, together with the use o f integrated pseudo-reference electrodes and devices for the monolithic fabrication o f a sensing system.
389
C. Can6 et al./pH ISFET chemical sensors
Gate (ref. electrode)
Source _
_
i ~
.
_
--
field oxide growth
- - photolithography for gate oxide definition Drain _
_
-
-
- - gate oxide growth --
sensitive inorganic membrane deposition
- - photolithography o f the sensitive membrane
SiO2
membrane
P
Bulk Fig. 1. Schematic cross-section of a front-side contacted ISFET.
Front side microtechnologies As the ISFET is, in principle, a M O S transistor with the metal gate replaced by the solution under test, the fabrication technologies for both types of devices can be very similar, the main difference being at the gate region. In ISFETS, not only is polysilicon replaced by a sensitive membrane, but also the passivation must be open over it. Also, source and drain definition is different on simple ISFET technologies as, due to the lack of polysilicon, they can not be selfaligned and they are usually implanted before field oxide. ISFETs can be n- or p-type and channel widths and lengths used are in the ranges 200-500 # m and 10-20 #m, respectively, in order to get high transconductances and to ensure good liquid contact. The main steps of a simple ISFET technology with inorganic membrane are summarized as follows: --
selection o f the proper doping level of (100) wafers
--
initial oxidation
- - photolithography for S/D definition --
390
S/D implant to obtain low resistive regions
- - photolithography of contacts --
metal deposition
- - photolithography for metal patterning - - passivation deposition - - p h o t o l i t h o g r a p h y for passivation opening over bonding pads and ISFET gates. Early w o r k on ISFETs used similar flow charts, as summarized by Matsuo et al. [3]. In simple technologies, no interlevel oxide is necessary and only the extra steps o f channel stop and threshold voltage implants need to be included, if necessary. T h e deposition o f the sensitive membrane can also be done at the end o f the process if the temperature o f deposition is not too high for the materials already deposited. An alternative technology consisting o f the fabrication o f amorphous silicon ISFETs on glass substrates was presented by Gotoh et al. [4]. Amorphous M O S devices can be made by radiofrequency plasma discharge and they can be applied to p H sensing if a sensitive material is deposited over the gate area as shown in the cross-section o f Fig. 2a. A similar structure fabricated on SOS substrates was proposed by Akiyama et al. [5]. However, the main part o f the research on planar ISFET technologies was made in the field o f the sensitive membranes, as they are the key point for obtaining sensors with good performances.
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(a) >/// / / / i /
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Ti
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n+ Si Fig. 2. Cross-sections of front-side contacted ISFETs: (a) fabricated over amorphous silicon [4], 01989; (b) obtained with a CMOS compatible technology [28], 01990; (c) with a platinum block layer [17], 01991; (d) with a floating gate and integrated together with an Ag/AgC1 electrode [36], 01989; (e) with polysilicon covering source and drain junctions [37], 01995; (f) with polysilicon gate and Pt membrane [16], ©1984. Reprinted with kind permission from Elsevier Science SA, Lausanne, Switzerland, and The Institute of Electrical and Electronic Engineers, Piscataway, USA.
(Continued overleaf)
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C. Can~ et al./pH ISFET chemical sensors
(d)
Poly/
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p-fype Si Fig. 2. Continued. T h e properties that the isolating material o f the ISFET gate must have are: m
to be sensitive and selective to the ion under test to passivate the silicon surface
--
392
to avoid hydration and ion migration to the semiconductor surface.
It is difficult to find a unique material that presents the three properties at the same time and, in practice, the gate material is usually composed o f a combination of dielectrics to get the desired behaviour. For obtaining linear, quasi-Nernstian and long-fife devices, SiO2 membranes are not adequate and many other materials have been studied, such as Si3N 4 [28], A1203 [3,8-10], Ta205 [3,11-13] and ZrO2 [5, 14], the first being the most c o m m o n and
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interesting. In all cases these materials are deposited over a thermally grown SiO2 layer for obtaining at the same time, good sensitivity and a good interface between the gate dielectric and the silicon surface. Other materials that have been studied consist of SiOxN r oxynitrides [13,15], with properties between Si3N 4 and SiO2 depending on stoichiometry. Finally, not only dielectric materials can be used as pH sensing layers; conducting materials such as Pt [16, 17], TiN [18] or [r203 [19] have also been shown to be sensitive and inert alternative materials. The above-mentioned materials are usually deposited following standard CVD or sputtering methods, but other techniques can be used to obtain sensitive gate dielectrics. For instance, it has been demonstrated that the ion implantation of some species can be used to change the sensitivity of oxide gates [20-22]. A good review of the characteristics of pH ISFETs with SiO2, Si3N 4, AI203 and Ta205 gates was also presented by Matsuo et al. [3] in the early 1980s. For comparison, they studied ion sensitivity and selectivity and chemical transient response. Despite the fact that the results can depend on the specific deposition process, they can be considered representative and are summarized here. SiO:, was the worst material in terms of pH sensitivity as the measured range was 25-48mV/pH with no linear dependence with pH. On the other hand, Si3N 4 showed sensitivities from 46 to 56 mV/pH depending on the deposition system and oxygen contents. This problem was overcome on A1203 and Ta205 gates that show quasi ideal sensitivity in the ranges 53-57 and 56-57mV/pH, respectively. Similar results were obtained when comparing the measured selectivities to other ions, the chemical transient response and the long term stability. In all cases, SiO2 was the worst material, and A1203 and Ta205 the best, with Si3N4 being an intermediate material with very acceptable results. Thus, Si3N 4 can be considered a
good alternative for ISFET gates due to the fact that it is a well-known material for IC foundries. Different methods can be used for depositing a nitride layer, but it has been shown that if there are no temperature constraints, LPCVD is the best technique for depositing stoichiometric, quasi-Nernstian sensitive and durable layers for pH detection. Only the tendency of Si3N4 to oxidize when in contact to a non-inert ambient is a drawback and an HF treatment is often required prior to use of the ISFETs. However, this effect can be reduced by varying the nitride deposition conditions [23] or by post-processing with RTP in N2 ambient in order to nitride the surface and avoid oxidation [24]. Other parameters of interest when designing the fabrication process for an ISFET of dual layer gate are the thicknesses of the SiO2 and top dielectric membranes. Most of the reported applications do not follow any rule and, in general, the thicknesses of the materials can be the standards of each laboratory. In Table 1, some reported thicknesses and deposition methods for nitride-based ISFETs are summarized, showing the variety of combinations that, according to the respective authors, give good pH sensitivity.
CMOS compatible technologies One of the main advantages of ISFETs, compared to other chemical sensors, is that they can be integrated with signal processing circuitry on the same chip. CMOS technologies are the most widely used for circuitry fabrication, and thus it is of interest to develop ISFETs with CMOS-based technologies. For this purpose, Si3N 4 membranes are quite appropriate as it is a common material in standard CMOS foundries. An early combination of Si3N 4 ISFETs and a metal gate technology was developed by Ko et al. [25]. In that case, gate insulator was deposited after the CMOS circuit processing was completed. However, metal gate technologies are not common nowadays.
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C. Can6 et al./pH ISFET chemical sensors
TABLE l Summary of representative reported membranes for Si3N4 based ISFETs. Reference
SiO2 thickness (nm)
Si3N4 thickness (nm)
Bergveld [1] Matsuo et al. [2,3] Moss et al. [6] Cohen et al. [7]
200 100 40 40 60 100 15 70 68 50 100 50 100 80 30 78 30 40
-100 50 60 40 100 42 100 37 110 200 120 200 85 100 100 70 50-80
Abe et al. [8] Wong and White [11] Vlasov et al. [14] Ko et al. [25] Smith et al. [26] Harame et al. [27] Tsukada et al. [28] Igarashi et al. [29] Cui et al. [30] Bousse et al. [31] C a n 6 et al. [32] Hein and Egger [33] Rocher et al. [34]
W h e n combining ISFETs with polysilicon gate M O S transistors, the main technological problem is the coexistence of Si3N4/SiO2 together with Poly/SiO2 gates on the same substrate. In Fig. 2b a cross-section of the devices obtained with a C M O S compatible technology proposed by Tsukada et al. [28, 35] is presented. After C M O S was completed, the process followed with special steps for the deposition o f a polyimide that covered the complete device except for the ISFET gates, where special ion selective membranes were deposited. An adaptation o f such technology was presented by the same authors with a platinum block layer, plus an ion sensitive membrane for the chemical sensing [17], as shown in Fig. 2c. Based on a similar technology, Can6 et al. [32] studied the best sequence of deposition and further etching o f Si3N4 and polysilicon over the SiO2 gate dielectric. In principle, damage could possibly be produced on a Si3N4 membrane if polysilicon were dry etched over it and the same effect could occur if the process was made
394
Deposition method Pyrolytic deposit R.f sputtering CVD CVD CVD PECVD LPCVD CVD LPCVD LPCVD LPCVD LPCVD LPCVD Photo CVD
following the inverse sequence. T h e authors obtained the best results with the first procedure as in this case M O S electrical parameters o f the on-chip circuitry remained unchanged, while ISFET performances were not visibly degraded. As a sensitive membrane was deposited at high temperature before metallization, aluminium could be used for interconnections. Another interesting technology was presented by Bouse e t al. [36] and consisted of keeping the polysilicon gate o f the M O S devices between the SiO2 and Si3Y 4 layers that form the ISFET sensitive membrane. In that case, the source and drain of the ISFETs can be self-aligned. According to the results presented, if kept as a floating conductor buried in the ISFET insulator, polysilicon did not affect the capacitance o f the gate, despite it interrupting the electric field lines. T h e authors also claimed the effect o f stopping ambient light as another advantage of leaving polysilicon over ISFET gate. T h e sensitive silicon nitride layer was deposited at the end o f the C M O S process and a special metallization
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using bulk micromachining [26, 38]. As shown in Fig. 3, the cavities were filled with proper solutions in contact with an Ag/AgC1 reference wire. A porous silicon membrane was also necessary for contacting the liquid under test and the integrated reference electrode. With this device, a stable potential independent of the concentration of the liquid under test could be applied. However, the device was not easy to integrate and other approaches have been studied by other authors.
with silicon-rich tungsten sihcide was used in order to resist the high temperatures involved in the LPCVD deposition of Si3Y4. In Fig. 2d, the cross-section of the sensor and an integrated Ag/ AgC1 electrode can be seen. Neuzil [37] also presented a technology where polysilicon was a part of the ISFET devices for eliminating the light sensitivity of such devices. However, in the technology mentioned, polysilicon was not kept on the gate area but over source and drain p-n junctions, the sensitive membrane being made of S i 3 N 4 o v e r SiO2. In Fig. 2e the cross-section can be observed. An early work of Smith et aL [16] also suggested the compatibility of a polysilicon gate with a Pt sensitive membrane. The simple cross-section is presented in Fig. 2f.
The integration of solid state pseudo-reference electrodes seems to be of more interest, despite the lack of a proper interface between the electrode and the liquid, making the reference potential unstable. However, the combination of these electrodes and differential mode circuitry can circumvent the instabilities problem. Noble metals have been studied to fabricate integrated electrodes, as they do not degrade when they are in contact with a liquid. Solid state electrodes can be made of combined layers of Pt/Ti [15,39], Au/Cr [11,13] and Ag/AgC1 [17,36,40].
To be a realistic approach, the combination of ISFETs and CMOS circuitry should be accompanied by the reduction of the size and integration of the reference electrode. The scaling down of standard macro-electrodes is an option that requires the creation of cavities on silicon
Di°,
,,i"....;i;,r..... i
Fig. 3. Cross-section of a CMOS ISFET and integrated reference electrode [26], ©1986. Reprinted with kind permission from The Institute of Electrical and Electronic Engineers, Piscataway, USA.
395
C. Can et al./pH ISFET chemical sensors
Pseudo-electrodes are deposited at the end of the process and lift-off is usually required to pattern them. The interferences produced by the instabilities of the voltage drop on the pseudo-reference electrode can be allowed if a differential measurement system is used. If two sensors are biased at the same time with the same electrode, the c o m m o n mode interferences due to the electrode can be cancelled if the signals of both sensors are subtracted. However, to have good pH sensitivity, the optimum set-up consists of the combination of a sensitive ISFET and a nonsensitive device with the same electrical properties. This second device is known as a reference FET (REFET). Thus, a new aspect had to be considered, which is the fabrication of good integrable REFETs. The idea of integrating the reference device had already been presented by Comte and Janata in 1978 [41]. The device consisted o f a pH ISFET that was connected with the sample solution by a free liquid junction. In Fig. 4 the schematic diagram of the proposed device is shown. This first approach demonstrated the feasibility of the idea of using the differential measurement technique but, on the other hand, the fabrication of the REFET was not made following IC compatible processes.
,on.sens,,,ve at.
Other attempts to fabricate insensitive ISFETs to be used as REFETs were based on the addition of blocking or non-blocking polymeric layers on the surface of the sensors in order to get a chemically inert behaviour. Poor results were obtained in most cases, as summarized by Bergveld et aL [42]. However, in the same work a couple of devices composed of an acrylate-based REFET and an A1203 sensitive ISFET combined with a pseudo-reference electrode showed very good performances for eliminating the intrinsic instabilities induced by the nonideal electrode, and also for reducing light and temperature sensitivity, compared to a measuring system based on a single ISFET. Alternatives, consisting of chemically modifying or grafting the inorganic surface on ISFETs to decrease sensitivity, have also been studied by different authors [15,43-45]. ISFETs can also insensitively operate over short periods of time if the pH response is retarded, creating what is called a pseudo-REFET. Van den Vlekkert et al. [46] controlled the nonresponse time of such a device by varying the thickness o f a polyvinylpyrolidone (PVP) layer deposited over the inorganic gate. Bergveld [47] also used the idea of combining two ISFETs, one of fast response and another of slow response, and performed dynamic measurements with the advantages of using
'°r'
Epoxy
Fig. 4. Schematic diagram of a transistor chip with an ISFET and a reference FET [41], ©1978. Reprinted with kind permissionfrom ElsevierScienceSA, Lausanne,Switzerland.
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flow-through (FIA) systems for such measurements. Another reference element was suggested by Lisdat et al. [48], based on a multilayer structure consisting of the combination of LaF3, CaF2 and a polymer membrane. Thus, it can be concluded that pseudo-REFETs have been fabricated by some authors, but none of them can be easily integrated in standard CMOS technologies. However, when performing differential measurements, it is not necessary to use a reference FET with null sensitivity. If ISFETs of different pH sensitivities can be used, a differential measurement can be performed with a pH sensitivity which is the difference of the initial sensitivities of the single ISFETs. A good example of this approach was presented by Wong and White [11], combining a gold pseudo-reference electrode, Ta205 and SiOxN r ISFETs and CMOS differential Opamps. The final pH sensitivity of the system, with the above-mentioned membranes, was of the order of 40mV/pH, which was enough for their application. An earlier example of integration was presented by Sibbald [49]. A circuit named operational transducer composed of a chemical sensitive FET and an electronic circuitry for temperature compensation, signal hnearization and output buffering, was fabricated following a compatible technology. Other examples of sensor and circuit integration have been used to combine multiple sensors with multiplexors and output signal amphfiers [17, 25, 28, 29, 50].
except on the sensitive gate area. This technique was demonstrated to be not feasible for mass production, and some alternatives based on the use of photosensitive compounds were developed later. Other interesting approaches were based on the use of glass-based packages, as they avoid degradation of device materials, make the deposition of organic membranes easy and can be fully automated when done at wafer level. However, in this case ISFET geometries should be different from the standard planar sensors, as contacts are on the back side of the wafer if the anodic bonding of glass to silicon is performed on the front side, where the sensitive membrane is deposited. A basic cross-section of a glass encapsulated back-side contacted ISFET is depicted in Fig. 5. As shown, silicon micromachining techniques must be used for contacting the front and back sides of the double-side devices. The combination of the back-side contacted ISFETs with glass packaging is of interest due to its application to flow injection analysis (FIA) systems that are of interest, as they avoid the problem of drifts of ISFETs. Some interesting technologies have been proposed during the last decade, and will be summarized here. M1 of Gate (ref. electrode)
Back-side contacted ISFETs
One of the main hmitations of ISFETs, if they are to be mass produced, is the difficulty of designing a simple packaging that usually depends on the application. Initial packaging techniques for planar ISFETs were based on the use of printed circuit board strips with the sensor chips attached. ISFETs usually have layouts adapted for facilitating the manual protection of the device with a cover of epoxy,
SiO-
Source
~ nq++ ~ Sensitive ~ n_~_+~)
Bulk
Drain
Fig. 5. Basicdiagramof a back-sidecontactedISFET.
397
C. Can et al./pH ISFET chemical sensors
them are based on a c o m m o n set of particular processes that are combined together with standard IC steps: - - silicon micromachining for etching silicon and contact junctions from the back side - - use of etch stop techniques - - deep diffusions for performing S/D junctions on both sides of the wafers --photolithographic surfaces
steps on deep etched
- - special metallization techniques
--special
packaging based on bonding.
glass/silicon
Silicon micromachining is a widely used technique in the field of mechanical sensors. Anisotropic etch of silicon uses alkaline solutions such as KOH, tetra methyl ammonium hydroxine (TMAH) or ethylene diamine pyrocatechol (EDP). Double-side polished wafers are necessary for patterning good geometries on both sides of the substrate, and etch-stop techniques must be applied to obtain membranes of controlled thicknesses. However, the main problem to be solved is the photolithography of wafers after the silicon has been etched. In this case the coverage of wafers with resist is very difficult and implies the use of special thick resist. Although some authors have succeeded with this, alternative techniques have also been studied as shown below. Early back-side contacted ISFETs, very similar to the device presented in Fig. 5, were fabricated by W o n g [51] on very thin (100) n-type substrates in order to use p + + diffusions to stop the silicon etch and to define repetitive membranes of silicon. The first attempts to obtain boron stopped membranes were not fully successful as thicknesses of only about 3/lm
398
could be defined due to the high boron dose necessary for stopping the K O H etch. Owing to the dimensions of the membranes the small thickness produced excessively weak devices and thus thicker 10/am thick membranes had to be obtained by time control of the etch. The sensitive membrane was a multilayer of SiO2 and A1203 LPCVD and the author did not comment on the photolithographic process. A new BSC-ISFET fabricated on p-type substrates was presented by Van den Vlekkert et al. [52]. The silicon etch was performed with K O H using a thick SiO2 layer as a mask. Due to the imprecision of the etching method, membranes in the range of 6 - 1 0 # m were obtained. Deep diffusions were made by deposition of a PSG layer and further drive-in up to a junction depth of 8/am. Then, an inorganic membrane composed of 9 0 n m of Si02 and 60 n m of A1203 LPCVD was deposited on the front side. Finally, aluminium contacts were defined on the back side by lift-off. The authors suggested that the main problem was the deposition of the photoresist in the vicinity of the holes, this being solved by depositing two resist layers and adjusting spinner parameters. In Fig. 6a a cross-section of the device is shown. The same sensor was combined with a pressure sensor by the authors to perform oesophageal studies [53]. Ewald et al. [54] presented two alternative technologies for BSC-ISFETs. In both cases, n-type devices were fabricated in a p-type well to obtain electrical isolation from the substrate. In the first approach, a refractory metal was used to extend the source and drain contacts beyond the p-well, where the contact to the back side was performed. In the second process, the contact to the back side was directly performed below the S/D through an n + membrane also made in the p-well. The technologies were intended to be compatible with a C M O S process. Crosssections can be seen in Figs. 6b and 6c. Photolithography was also a critical step in these tech-
Microelectronics Journal, Vol. 28, No. 4
(a) '-~
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.......................
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399
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al./pH ISFET chemical sensors
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Microelectronics Journal, Vol. 28, No. 4
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nologies as silicon etching was performed at the beginning of the process. Photolithography steps after silicon etching were improved by Sakai et al. [55] by performing round isotropic etching procedures on the edges of the back-side contacts and gate areas. This improvement was carried out on a complex technology based on the silicon direct bonding of two wafers to forrn a silicon insulator silicon (SIS) device, as obsezved in the cross-section of Fig. 6d. Mechanical polishing was also required, prior to wet etch, to obtain membranes of about 20 #m but with poor control. Back-side contact metaUization was made with a combination of Au/Cu/Ti layers. A similar interesting double-side technology was presented by Yagi and Sakai [56], also based on SIS structures as shown in Fig. 6e. However, in this case source and drain contacts were placed on the front side o£ the structure while the sensitive membrane was deposited on the back side, after anisotropic etch was performed. Also, locking structures at the edge of the back holes were constructed ~}r improving membrane adhesion, especially when using organic materials. The best procedure to define ultra-high p+ zones for constructing the locking structures was also studied by the authors. Another ISFET structure based on the silicon direct bonding technique was developed by
Poghossian [57]. It also consisted of a back-gate device with the source and drain fabricated on a top silicon layer, as shown in Fig. 6f. In this case, connection of the sensitive area to the gate of the device was made with a metal layer. The interest in back-side membranes to be applied to SIS structures for ISFETs led Pham et al. [58] to study different process techniques for fabricating the membranes for ISFETs used in micro-fluid systems. The etch stop techniques examined consisted of the use ofSIMOX substrates, buried silicon nitride and buried p-n junction made by ion implantation. Process parameters were optimized to obtain the desired results using fully compatible IC techniques. The authors concluded that the p-n junction technique was the most interesting in terms of economy and performance. Based on p-n etch stop techniques three different technologies were recently developed by Merlos et al. [59-61]. The main characteristic of these technologies is the absence of photolithographic steps after the anisotropic etching, as only thermal processes were made after the etch of silicon. Robust membranes in the range of 15-30/~m were obtained by electrochemical etch stop and combined with 15-20/~m deep n+ diffusions made with POCI3 to ensure the contact of the front and back sides of sources and drains of the ISFETs. In Figs. 6g-6i, the cross-sections of devices fabricated following the proposed technologies are shown. The first technology consisted of a very simple and low cost process that used a nickel
401
C. Cane et al./pH ISFET chemical sensors
TABLE 2 Summaryof characteristics of double side-contacted ISFETs Reference
Substrate
Wang [51]
SiO2 80 nm AI203 150 nm p, 3-5 Ftcm SiO2 90 nm A1203 60 nm n, 3-5 f~cm SiO2 1000 nm A1203 120 nm p SiO2 100 nm SiNx 150 nm p SiO2 100 nm Si3N4 150 nm p, 20 ~2cm SiO2 80 nm Si3N4 80 nm Ta205 80 nm p, 12-17 f~cm, SiO278 nm bulk or BESOI Si3N4180 nm n, 5f~cm
Van den Vlekkert et al. [52] Ewald et al. [54] Sakai et Yagi et
al. al.
[55] [56]
Poghossian et Merlos et
al.
Membrane
al.
[57]
[59-61]
electroless plating technique for the selective metallization o f back contacts without the need for lithographic patterning. The disadvantage of the device was that it was not fully C M O S compatible. A second technology from the same authors eliminated this drawback. The new device was a back-side membrane ISFET with contacts, and all other steps were made on the front side o f the substrate, where C M O S circuitry can also be integrated. A third technology, similar to the previous one, was developed to fabricate devices with the sensitive part on the back side and only one etched hole in the silicon had to be made for contacting source and drain. BESOI wafers were used in order to take advantage o f the buried oxide Bulk m e t a l l i z a J ~ S a ~ J/
Thickness
Etchant
Etch Stop
Metal
10/ira
EDP
p+, time
6--10 #m
KOH
Time
13-17#m
KOH
Time
10-30#m
Hydracine SiO2layer
Au/Cu/Ti
EDP
Au/Cu/Ti SiO2 layer
20-25 #m
TMAH
Nickel or p-n junction or buried SiO2 aluminium
for stopping the silicon etch. The weak point of the technology consists o f the fact that the dimensions o f the channel o f the ISFET are defined not directly by the layout, but by the back lateral diffusion o f source and drain, at a point where doping concentration is much lower than at the surface. A summary o f the characteristics o f the mentioned technologies for back-side contacted ISFETs is presented in Table 2. Finally, it is o f interest to cite a flow-through ISFET proposed by Sibbald and Shaw [62] for a special flow cell application, which is shown in Fig. 7. The structure also needed silicon micromachining, but in this case the substrate was
Drain metallization
,
J Bond p
/~ //IF
,on,
surfa p-substrafe
_~__/C/ha nnei _ ~ ' / SisN4/SiO2
"- n +
source /
SisN4/Si02 ~ bource
..... m e t a IZOflOn
Fig. 7. Flow-through ISFET [62], ©1987. Reprinted with kind permission from Elsevier Science SA, Lausanne, Switzerland.
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completely etched to define the source and drain diffusions, one o n each side o f the wafer, with channel dielectrics deposited on the vertical walls o f the hole.
Conclusions S o m e interesting and representative microtechnologies for the fabrication o f different types o f p H ISFET chemical sensors have been reviewed. For standard planar devices it has been s h o w n that the proper selection o f the inorganic m e m b r a n e is o f great importance for obtaining p H sensors o f g o o d electrical characteristics and long lifetime. It has also b e e n s h o w n that some ISFET technologies can be fully C M O S compatible, allowing the integration o f a complete measurement system based on sensors and signal processing circuitry on the same chip. R e f e r e n c e electrode and reference F E T implementations have been reviewed for making the integration possible. C M O S compatibility is considered a basic constraint for future technologies, due to the increasing interest o f performing application specific: integrated sensors (ASIS) based on standard technologies o f commercial foundries. Finally, back-side contacted technologies have also b e e n summarized due to their importance in c o m b i n a t i o n with glass packaging techniques, w i t h the aim o f obtaining g o o d devices for FIA m e a s u r e m e n t systems. It can be c o n c l u d e d that this approach is very interesting despite the need for extra technological steps involving silicon m i c r o m a c h i n i n g and anodic bonding.
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