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MIM-type cell selector for high-density and low-power cross-point memory application
Microelectronic Engineering 93 (2012) 81–84
Contents lists available at SciVerse ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
MIM-type cell selector for high-density and low-power cross-point memory application Jungho Shin a, Godeuni Choi a, Jiyong Woo a, Jubong Park a, Sangsu Park b, Wootae Lee a, Seonghyun Kim a, Myungwoo Son b, Hyunsang Hwang a,b,⇑ a b
School of Materials Science and Engineering, Gwangju Institute of Science and Technology, Gwangju 500-712, Republic of Korea Nanobio Materials and Electronics, Gwangju Institute of Science and Technology, Gwangju 500-712, Republic of Korea
a r t i c l e
i n f o
Article history: Received 16 July 2011 Received in revised form 16 November 2011 Accepted 20 December 2011 Available online 26 December 2011 Keywords: Resistive memory (RRAM) Cross-point array Cell selector Readout margin Power consumption
a b s t r a c t A resistive memory can be highly integrated using a cross-point architecture; however, it requires appropriate cell selectors in order to suppress sneak paths and reduce power dissipation. In this paper, we study the effect of cell selectors on the readout margin and power dissipation in the read operation. A cell selector (Pt/TiOx/Pt) and a resistive memory (Mo/SiOx/Pt) were fabricated, and the electrical I–V characteristics were examined after connecting these two devices in series. On the basis of the I–V measurements, the readout margin and power dissipation of a cross-point array were calculated depending on the existence and characteristics of the selector. Ó 2012 Elsevier B.V. All rights reserved.
1. Introduction Resistive memory (RRAM) is an alternative memory for the next generation because of its high density integration, nonvolatility, low power consumption, high-speed operation, and CMOS compatibility [1]. To realize ultradense memory systems, the application of a cross-point array architecture is the most promising candidate [2]. This type of a cross-point memory can be composed of either an active array employing transistors (1T-1R structure) [3] or a passive array using diodes (1D-1R structure) [4]. The active cross-point array contains a transistor at each memory cell, and the memory cell is selected by tuning on its transistor. However, the 1T-1R structure not only occupies an area of at least 6F2–8F2 (F is the minimum feature size) but also involves a complex process. In comparison with the 1T-1R approach, the 1D-1R approach offers the advantages of a simple process and high integration (4F2) owing to its simple two-terminal structure. Moreover, such a passive array using a 1D-1R structure can be multiple stacked to create a 3D memory, which is further integrated up to 4F2/k (k = number of stack) [5]. Several 1D-1R-type selectors have been proposed for a unipolar-type RRAM, such as a p–n junction diode [5], a threshold-type switch [6], and a Schottky diode [7]. Recently, complementary resistive switch (CRS) concept [8–10] or self-rectifying concept
[11,12] is reported for bipolar-type RRAM cross-point application. However, a study of general selectors for a bipolar-type RRAM is needed. Because the program/erase operation of the bipolar-type RRAM occurs at both (positive/negative) voltage polarities, this type of RRAM cannot be properly programmed or erased using the existing diode. The selector of a bipolar-type RRAM should have enough current to lead the program/erase process; however, it must block the current that is below half the read voltage (1/ 2Vread) to prevent unwanted current paths through unselected cells in the read operation [13]. A cross-point memory array without cell selectors has been reported using some peripheral circuits of the memory array, a new read scheme, and non-linear device characteristics [14,15]. Nevertheless, it still has the disadvantages of a small readout margin and high power dissipation. Therefore, an effective RRAM selector is absolutely required to realize a high-density, low-power memory. In this paper, we evaluate readout margin and power dissipation depending on the existence and characteristics of the selector, based on previous work [13]. In comparison with the previous work (Pt/TiO2/TiN selector), more symmetric I–V characteristics and improved selectivity was obtained by fabricating Pt/TiOx/Pt selector device.
2. Experimental details ⇑ Corresponding author at: School of Materials Science and Engineering, Gwangju Institute of Science and Technology, Gwangju 500-712, Republic of Korea. E-mail address: [email protected] (H. Hwang). 0167-9317/$ - see front matter Ó 2012 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.12.006
As a bipolar-type RRAM device, a Mo/SiOx/Pt device was fabricated as depicted in Fig. 1(a). Initially, a 50-nm-thick SiOx layer
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was deposited onto a 250-nm diameter (active device area) via hole (Pt/SiO2/Si) at 300 °C using an RF magnetron sputtering system. Then, a 100-nm-thick Mo top electrode was deposited using the RF magnetron sputtering system at room temperature. The top electrode (300 300 lm) was patterned using a shadow mask. A Pt/TiOx/Pt stack was fabricated as a selector (Fig. 1(b)). A 4-nmthick TiOx layer was deposited onto the 250-nm diameter (active device area) via hole (Pt/SiO2/Si) at 150 °C using an atomic layer deposition (ALD) system. Then, a 100-nm-thick Pt top electrode was deposited by RF magnetron sputtering at room temperature. The top electrode (300 300 lm) was patterned using a shadow mask. To evaluate the performance of the selector, we connected it to an RRAM in series. The current–voltage (I–V) characteristics were measured by a semiconductor parameter analyzer (Agilent Technology 4155C).
3. Results and discussion As shown in Fig. 1(c), the Mo/SiOx/Pt RRAM device exhibits typical bipolar/filament-type resistive switching behavior. When the positive bias is applied to the Mo top electrode, oxygen vacancies move downward. Consequently, a filament of oxygen vacancies is constructed from the Pt bottom electrode to the Mo top electrode. As a result, the RRAM device is switched from a high-resistance state (HRS) to a low-resistance state (LRS). When the negative bias is applied to the Mo top electrode, the filament at the interfaces is ruptured. Thus, the RRAM device is switched from the LRS to the HRS. The more details of the switching mechanism are discussed in Ref. [16]. Although this RRAM device has a large on/off ratio (>105), it cannot be solely applied to a cross-point array because of sneak paths. If selectors do not exist in the passive cross-point array, undesired sneak paths arise through unselected cells, as shown in Fig. 1(e). These sneak paths hinder the reading of data stored in memory cells, and this problem becomes significant as the volume of the cross-point array increases, because the number of unwanted sneak path increases when the array is expanded. To resolve this problem, we employed a simple two-terminal selector with a Pt/TiOx/Pt structure. Because Pt has a high work function (5.6 eV) and TiOx is a known n-type semiconductor, a Pt/TiOx/Pt device consists of Schottky barriers between its TiOx layer and the Pt layer at its top and bottom, respectively. As shown in Fig. 1(c), the selector blocks its current at below |0.8 V| and permits current to flow at above |0.8 V|. After connecting the RRAM device
and the selector in series, I–V measurements were performed (Fig. 1(d)). On the basis of the results, the low resistance state (LRS) current of the RRAM is controlled by the selector; however, the on/off ratio is decreased as compared with the case without the selector. Moreover, its LRS current at half the read voltage (0.8 V) becomes almost the same as its HRS current. As depicted in Fig. 1(f), the problem of sneak paths can be solved by controlling the LRS current using the selector (1D-1R structure). An equivalent circuit model has been reported for the read operation in the cross-point array (n m), as shown in Fig. 2(a) [17]. We assumed an ideal interconnect and the worst case for read operations, which means all unselected cells are LRS (Ron). The driving voltages for (non-)accessed word/bit lines are labeled VW/B(N)A. We applied a read scheme of +1/2Vread/1/2Vread to access the word/bit lines and grounded non-accessed word/bit lines (Fig. 2(b)). As the resistance of the selected cell (Ron/off) is changed by a set or reset process, a readout voltage (VOUT), which is dropped across a load resistor (RL), is also changed (VOUTon or VOUToff). By this sensing method, we can determine whether the selected memory cell is on or off. Using the equivalent circuit, we obtain an analytic solution [17], which is expressed as:
V OUT ¼
RL Ron V WA RL Ron Ron þ RS ðn 1Þ RL þ n1 Ron ðn1ÞðRL þn1 Þ þ
RL RS V WNA RL V BA RS Ron RL RS Ron R þ L ðRL þ RS Þ RL þRS þ n1 ðn1ÞðRS þRon Þ
ð1Þ
n1
where n is number of word lines, RL (load resistor) is an optimal value for readout, and Rs is the resistance value of the selected cell. Using the analytic solution, we obtain the readout margin (100 (VOUTon VOUToff)/VWL) of a cross-point array (n m) for given device parameters and voltage biases. Variable Ron in the analytic solution is determined by the existence of the selector. If the cross-point array does not contain the selector, Ron in the analytic solution is equal to the Ron of Rs. However, if the selector is present, Ron in the analytic solution is almost same as the Roff of Rs, because the value of Ron in the solution comes from unselected cells in the equivalent circuit and we use the half-read scheme (Fig. 2). Owing to this difference, the readout margin can be significantly dependent on the existence of the selector in the cross-point array. In order to estimate the readout margin, VOUT is calculated using the MATLAB program. As shown in Fig. 3, the readout margin can
Fig. 1. (a) Schematic diagram of Mo/SiOx/Pt RRAM structure. (b) Schematic diagram of Pt/TiOx/Pt selector. (c) Typical bipolar/filament-type resistive switching characteristics of Mo/SiOx/Pt RRAM, and I–V characteristics of Pt/TiOx/Pt selector. (d) I–V characteristics of RRAM with the selector. (e) Possible sneak paths in the cross-point array. (f) Rectified read operation by suppressing the sneak paths.
J. Shin et al. / Microelectronic Engineering 93 (2012) 81–84
83
Fig. 2. (a) The equivalent circuit model of n m cross-point array for read operation (worst case). (b) Data read scheme for cross-point array.
Fig. 3. Calculated readout margin depending on the existence and characteristics of the selector. 10% readout margin is assumed to be criteria for read operation (worst case).
be obtained depending on the existence and characteristics of the selector. In Fig. 1(d), the on/off ratio of the connected series is approximately 102; however, this ratio can be increased or decreased by modulating the characteristics of the selector. Let us assume that the current density of the selector at below |0.8 V| is fixed and at above |0.8 V| can be controlled. When the current density of the selector at above |0.8 V| is increased, the on/off ratio of the RRAM (with the selector) can be increased, or vice versa. After employing this assumption, we calculated the readout margin and found that memory integration can be significantly improved by increasing the current density of the selector (at Vread) at 10% readout margin. Future experiments will focus on tests with increasing the current density of the selector (at Vread). We believe that the current density can be much improved by engineering the bandgap or Fermi-level of an insulating layer between top and bottom electrode. Using the equivalent circuit model and the PSpice circuit simulator, we also obtained the power dissipation in the read operation (Fig. 4). In the case without the selector, power consumption is relatively large because of numerous leakage paths through unselected cells. In contrast, adopting the selector can remarkably reduce the power dissipation by suppressing sneak paths in the read operation. If power dissipation of 10 mW is the criterion for read operations, the memory density can be expanded by a factor of 106 (n) by using the selector.
Fig. 4. Simulated power dissipation depending on the existence and characteristics of the selector. Power dissipation of 10 mW is assumed to be the criterion for read operation (worst case).
4. Conclusion An analysis on the necessity of cell selectors was conducted using the equivalent circuit model and the analytic solution for the read operation in a cross-point array. Although, cross-point memory array without cell selectors has been suggested using some peripheral circuits of the memory array, a new read scheme, and non-linear device characteristics by some authors, cell selectors are definitely required to produce high integration memory and lower power consumption, based on the results of readout margin calculation and power dissipation simulation. Moreover, readout margin can be substantially improved, if the current density (at Vread) of the selector is increased. Acknowledgments This work was supported by R&D program of the Ministry of Knowledge Economy and the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST). References [1] International Technology Roadmap for Semiconductors, 2009. [2] I.G. Baek, D.C. Kim, M.J. Lee, H.-J. Kim, E.K. Yim, M.S. Lee, J.E. Lee, S.E. Ahn, S. Seo, J.H. Lee, J.C. Park, Y.K. Cha, S.O. Park, H.S. Kim, I.K. Yoo, U.-In. Chung, J.T. Moon, B.I. Ryu, IEDM Tech. Dig. 750 (2005).
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[3] Y. Sato, K. Tsunoda, K. Kinoshita, H. Noshiro, M. Aoki, Y. Sugiyama, IEEE Trans. Electron Dev. 55 (2008) 1185. [4] Y. Sasago, M. Kinoshita, T. Morikawa, K. Kurotsuchi, S. Hanzawa, T. Mine, A. Shima, Y. Fujisaki, H. Kume, H. Moriya, N. Takaura, K. Torii, VLSI Tech. Dig. 24 (2009). [5] M. Lee, S. Seo, D. Kim, S. Ahn, D. H. Seo, I. Yoo, I. Baek, D. Kim, I. Byun, S. Kim, I. Hwang, J. Kim, S. Jeon, B.H. Park, Adv. Mater. 19 (2007) 73. [6] M. Lee, Y. Park, D. Suh, E. Lee, S. Seo, D. Kim, R. Jung, B. Kang, S. Ahn, C.B. Lee, D.H. Seo, Y. Cha, I. Yoo, J.S. Kim, B.H. Park, Adv. Mater. 19 (2007) 3919. [7] W.Y. Park, G.H. Kim, J.Y. Seok, K.M. Kim, S.J. Song, M.H. Lee, C.S. Hwang, Nanotechnology 21 (2010) 195201. [8] E. Linn, R. Rosezin, C. Kügeler, R. Waser, Nat. Mater. 9 (2010) 403. [9] S. Yu, J. Liang, Y. Wu, H.-S.P. Wong, Nanotechnology 21 (2010) 465202. [10] J. Lee, J. Shin, D. Lee, W. Lee, S. Jung, M. Jo, J. Park, K.P. Biju, S. Kim, S. Park, H. Hwang, IEDM Tech. Dig. 452 (2010).
[11] M. Jo, D. Seong, S. Kim, J. Lee, W. Lee, J. Park, S. Park, S. Jung, J. Shin, D. Lee, H. Hwang, VLSI Tech. Dig. 53 (2010). [12] K.P. Biju, X. Liu, E.M. Bourim, I. Kim, S. Jung, M. Siddik, J. Lee, H. Hwang, J. Phys. D: Appl. Phys. 43 (2010) 495104. [13] J. Shin, I. Kim, K.P. Biju, M. Jo, J. Park, J. Lee, S. Jung, W. Lee, S. Kim, S. Park, H. Hwang, J. Appl. Phys. 109 (2011) 033712. [14] J. Liang, H.-S.P. Wong, IEEE Trans. Electron Dev. 57 (2010) 2531. [15] P.O. Vontobel, W. Robinett, P.J. Kuekes, D.R. Stewart, J. Straznicky, R.S. Williams, Nanotechnology 20 (2009) 425204. [16] J. Shin, J. Park, J. Lee, S. Park, S. Kim, W. Lee, I. Kim, D. Lee, H. Hwang, IEEE Electron Dev. Lett. 32 (2011) 958. [17] C.J. Amsinck, N.H.D. Spigna, D.P. Nackashi, P.D. Franzon, Nanotechnology 16 (2005) 2251.
Contents lists available at SciVerse ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
MIM-type cell selector for high-density and low-power cross-point memory application Jungho Shin a, Godeuni Choi a, Jiyong Woo a, Jubong Park a, Sangsu Park b, Wootae Lee a, Seonghyun Kim a, Myungwoo Son b, Hyunsang Hwang a,b,⇑ a b
School of Materials Science and Engineering, Gwangju Institute of Science and Technology, Gwangju 500-712, Republic of Korea Nanobio Materials and Electronics, Gwangju Institute of Science and Technology, Gwangju 500-712, Republic of Korea
a r t i c l e
i n f o
Article history: Received 16 July 2011 Received in revised form 16 November 2011 Accepted 20 December 2011 Available online 26 December 2011 Keywords: Resistive memory (RRAM) Cross-point array Cell selector Readout margin Power consumption
a b s t r a c t A resistive memory can be highly integrated using a cross-point architecture; however, it requires appropriate cell selectors in order to suppress sneak paths and reduce power dissipation. In this paper, we study the effect of cell selectors on the readout margin and power dissipation in the read operation. A cell selector (Pt/TiOx/Pt) and a resistive memory (Mo/SiOx/Pt) were fabricated, and the electrical I–V characteristics were examined after connecting these two devices in series. On the basis of the I–V measurements, the readout margin and power dissipation of a cross-point array were calculated depending on the existence and characteristics of the selector. Ó 2012 Elsevier B.V. All rights reserved.
1. Introduction Resistive memory (RRAM) is an alternative memory for the next generation because of its high density integration, nonvolatility, low power consumption, high-speed operation, and CMOS compatibility [1]. To realize ultradense memory systems, the application of a cross-point array architecture is the most promising candidate [2]. This type of a cross-point memory can be composed of either an active array employing transistors (1T-1R structure) [3] or a passive array using diodes (1D-1R structure) [4]. The active cross-point array contains a transistor at each memory cell, and the memory cell is selected by tuning on its transistor. However, the 1T-1R structure not only occupies an area of at least 6F2–8F2 (F is the minimum feature size) but also involves a complex process. In comparison with the 1T-1R approach, the 1D-1R approach offers the advantages of a simple process and high integration (4F2) owing to its simple two-terminal structure. Moreover, such a passive array using a 1D-1R structure can be multiple stacked to create a 3D memory, which is further integrated up to 4F2/k (k = number of stack) [5]. Several 1D-1R-type selectors have been proposed for a unipolar-type RRAM, such as a p–n junction diode [5], a threshold-type switch [6], and a Schottky diode [7]. Recently, complementary resistive switch (CRS) concept [8–10] or self-rectifying concept
[11,12] is reported for bipolar-type RRAM cross-point application. However, a study of general selectors for a bipolar-type RRAM is needed. Because the program/erase operation of the bipolar-type RRAM occurs at both (positive/negative) voltage polarities, this type of RRAM cannot be properly programmed or erased using the existing diode. The selector of a bipolar-type RRAM should have enough current to lead the program/erase process; however, it must block the current that is below half the read voltage (1/ 2Vread) to prevent unwanted current paths through unselected cells in the read operation [13]. A cross-point memory array without cell selectors has been reported using some peripheral circuits of the memory array, a new read scheme, and non-linear device characteristics [14,15]. Nevertheless, it still has the disadvantages of a small readout margin and high power dissipation. Therefore, an effective RRAM selector is absolutely required to realize a high-density, low-power memory. In this paper, we evaluate readout margin and power dissipation depending on the existence and characteristics of the selector, based on previous work [13]. In comparison with the previous work (Pt/TiO2/TiN selector), more symmetric I–V characteristics and improved selectivity was obtained by fabricating Pt/TiOx/Pt selector device.
2. Experimental details ⇑ Corresponding author at: School of Materials Science and Engineering, Gwangju Institute of Science and Technology, Gwangju 500-712, Republic of Korea. E-mail address: [email protected] (H. Hwang). 0167-9317/$ - see front matter Ó 2012 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.12.006
As a bipolar-type RRAM device, a Mo/SiOx/Pt device was fabricated as depicted in Fig. 1(a). Initially, a 50-nm-thick SiOx layer
82
J. Shin et al. / Microelectronic Engineering 93 (2012) 81–84
was deposited onto a 250-nm diameter (active device area) via hole (Pt/SiO2/Si) at 300 °C using an RF magnetron sputtering system. Then, a 100-nm-thick Mo top electrode was deposited using the RF magnetron sputtering system at room temperature. The top electrode (300 300 lm) was patterned using a shadow mask. A Pt/TiOx/Pt stack was fabricated as a selector (Fig. 1(b)). A 4-nmthick TiOx layer was deposited onto the 250-nm diameter (active device area) via hole (Pt/SiO2/Si) at 150 °C using an atomic layer deposition (ALD) system. Then, a 100-nm-thick Pt top electrode was deposited by RF magnetron sputtering at room temperature. The top electrode (300 300 lm) was patterned using a shadow mask. To evaluate the performance of the selector, we connected it to an RRAM in series. The current–voltage (I–V) characteristics were measured by a semiconductor parameter analyzer (Agilent Technology 4155C).
3. Results and discussion As shown in Fig. 1(c), the Mo/SiOx/Pt RRAM device exhibits typical bipolar/filament-type resistive switching behavior. When the positive bias is applied to the Mo top electrode, oxygen vacancies move downward. Consequently, a filament of oxygen vacancies is constructed from the Pt bottom electrode to the Mo top electrode. As a result, the RRAM device is switched from a high-resistance state (HRS) to a low-resistance state (LRS). When the negative bias is applied to the Mo top electrode, the filament at the interfaces is ruptured. Thus, the RRAM device is switched from the LRS to the HRS. The more details of the switching mechanism are discussed in Ref. [16]. Although this RRAM device has a large on/off ratio (>105), it cannot be solely applied to a cross-point array because of sneak paths. If selectors do not exist in the passive cross-point array, undesired sneak paths arise through unselected cells, as shown in Fig. 1(e). These sneak paths hinder the reading of data stored in memory cells, and this problem becomes significant as the volume of the cross-point array increases, because the number of unwanted sneak path increases when the array is expanded. To resolve this problem, we employed a simple two-terminal selector with a Pt/TiOx/Pt structure. Because Pt has a high work function (5.6 eV) and TiOx is a known n-type semiconductor, a Pt/TiOx/Pt device consists of Schottky barriers between its TiOx layer and the Pt layer at its top and bottom, respectively. As shown in Fig. 1(c), the selector blocks its current at below |0.8 V| and permits current to flow at above |0.8 V|. After connecting the RRAM device
and the selector in series, I–V measurements were performed (Fig. 1(d)). On the basis of the results, the low resistance state (LRS) current of the RRAM is controlled by the selector; however, the on/off ratio is decreased as compared with the case without the selector. Moreover, its LRS current at half the read voltage (0.8 V) becomes almost the same as its HRS current. As depicted in Fig. 1(f), the problem of sneak paths can be solved by controlling the LRS current using the selector (1D-1R structure). An equivalent circuit model has been reported for the read operation in the cross-point array (n m), as shown in Fig. 2(a) [17]. We assumed an ideal interconnect and the worst case for read operations, which means all unselected cells are LRS (Ron). The driving voltages for (non-)accessed word/bit lines are labeled VW/B(N)A. We applied a read scheme of +1/2Vread/1/2Vread to access the word/bit lines and grounded non-accessed word/bit lines (Fig. 2(b)). As the resistance of the selected cell (Ron/off) is changed by a set or reset process, a readout voltage (VOUT), which is dropped across a load resistor (RL), is also changed (VOUTon or VOUToff). By this sensing method, we can determine whether the selected memory cell is on or off. Using the equivalent circuit, we obtain an analytic solution [17], which is expressed as:
V OUT ¼
RL Ron V WA RL Ron Ron þ RS ðn 1Þ RL þ n1 Ron ðn1ÞðRL þn1 Þ þ
RL RS V WNA RL V BA RS Ron RL RS Ron R þ L ðRL þ RS Þ RL þRS þ n1 ðn1ÞðRS þRon Þ
ð1Þ
n1
where n is number of word lines, RL (load resistor) is an optimal value for readout, and Rs is the resistance value of the selected cell. Using the analytic solution, we obtain the readout margin (100 (VOUTon VOUToff)/VWL) of a cross-point array (n m) for given device parameters and voltage biases. Variable Ron in the analytic solution is determined by the existence of the selector. If the cross-point array does not contain the selector, Ron in the analytic solution is equal to the Ron of Rs. However, if the selector is present, Ron in the analytic solution is almost same as the Roff of Rs, because the value of Ron in the solution comes from unselected cells in the equivalent circuit and we use the half-read scheme (Fig. 2). Owing to this difference, the readout margin can be significantly dependent on the existence of the selector in the cross-point array. In order to estimate the readout margin, VOUT is calculated using the MATLAB program. As shown in Fig. 3, the readout margin can
Fig. 1. (a) Schematic diagram of Mo/SiOx/Pt RRAM structure. (b) Schematic diagram of Pt/TiOx/Pt selector. (c) Typical bipolar/filament-type resistive switching characteristics of Mo/SiOx/Pt RRAM, and I–V characteristics of Pt/TiOx/Pt selector. (d) I–V characteristics of RRAM with the selector. (e) Possible sneak paths in the cross-point array. (f) Rectified read operation by suppressing the sneak paths.
J. Shin et al. / Microelectronic Engineering 93 (2012) 81–84
83
Fig. 2. (a) The equivalent circuit model of n m cross-point array for read operation (worst case). (b) Data read scheme for cross-point array.
Fig. 3. Calculated readout margin depending on the existence and characteristics of the selector. 10% readout margin is assumed to be criteria for read operation (worst case).
be obtained depending on the existence and characteristics of the selector. In Fig. 1(d), the on/off ratio of the connected series is approximately 102; however, this ratio can be increased or decreased by modulating the characteristics of the selector. Let us assume that the current density of the selector at below |0.8 V| is fixed and at above |0.8 V| can be controlled. When the current density of the selector at above |0.8 V| is increased, the on/off ratio of the RRAM (with the selector) can be increased, or vice versa. After employing this assumption, we calculated the readout margin and found that memory integration can be significantly improved by increasing the current density of the selector (at Vread) at 10% readout margin. Future experiments will focus on tests with increasing the current density of the selector (at Vread). We believe that the current density can be much improved by engineering the bandgap or Fermi-level of an insulating layer between top and bottom electrode. Using the equivalent circuit model and the PSpice circuit simulator, we also obtained the power dissipation in the read operation (Fig. 4). In the case without the selector, power consumption is relatively large because of numerous leakage paths through unselected cells. In contrast, adopting the selector can remarkably reduce the power dissipation by suppressing sneak paths in the read operation. If power dissipation of 10 mW is the criterion for read operations, the memory density can be expanded by a factor of 106 (n) by using the selector.
Fig. 4. Simulated power dissipation depending on the existence and characteristics of the selector. Power dissipation of 10 mW is assumed to be the criterion for read operation (worst case).
4. Conclusion An analysis on the necessity of cell selectors was conducted using the equivalent circuit model and the analytic solution for the read operation in a cross-point array. Although, cross-point memory array without cell selectors has been suggested using some peripheral circuits of the memory array, a new read scheme, and non-linear device characteristics by some authors, cell selectors are definitely required to produce high integration memory and lower power consumption, based on the results of readout margin calculation and power dissipation simulation. Moreover, readout margin can be substantially improved, if the current density (at Vread) of the selector is increased. Acknowledgments This work was supported by R&D program of the Ministry of Knowledge Economy and the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST). References [1] International Technology Roadmap for Semiconductors, 2009. [2] I.G. Baek, D.C. Kim, M.J. Lee, H.-J. Kim, E.K. Yim, M.S. Lee, J.E. Lee, S.E. Ahn, S. Seo, J.H. Lee, J.C. Park, Y.K. Cha, S.O. Park, H.S. Kim, I.K. Yoo, U.-In. Chung, J.T. Moon, B.I. Ryu, IEDM Tech. Dig. 750 (2005).
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[3] Y. Sato, K. Tsunoda, K. Kinoshita, H. Noshiro, M. Aoki, Y. Sugiyama, IEEE Trans. Electron Dev. 55 (2008) 1185. [4] Y. Sasago, M. Kinoshita, T. Morikawa, K. Kurotsuchi, S. Hanzawa, T. Mine, A. Shima, Y. Fujisaki, H. Kume, H. Moriya, N. Takaura, K. Torii, VLSI Tech. Dig. 24 (2009). [5] M. Lee, S. Seo, D. Kim, S. Ahn, D. H. Seo, I. Yoo, I. Baek, D. Kim, I. Byun, S. Kim, I. Hwang, J. Kim, S. Jeon, B.H. Park, Adv. Mater. 19 (2007) 73. [6] M. Lee, Y. Park, D. Suh, E. Lee, S. Seo, D. Kim, R. Jung, B. Kang, S. Ahn, C.B. Lee, D.H. Seo, Y. Cha, I. Yoo, J.S. Kim, B.H. Park, Adv. Mater. 19 (2007) 3919. [7] W.Y. Park, G.H. Kim, J.Y. Seok, K.M. Kim, S.J. Song, M.H. Lee, C.S. Hwang, Nanotechnology 21 (2010) 195201. [8] E. Linn, R. Rosezin, C. Kügeler, R. Waser, Nat. Mater. 9 (2010) 403. [9] S. Yu, J. Liang, Y. Wu, H.-S.P. Wong, Nanotechnology 21 (2010) 465202. [10] J. Lee, J. Shin, D. Lee, W. Lee, S. Jung, M. Jo, J. Park, K.P. Biju, S. Kim, S. Park, H. Hwang, IEDM Tech. Dig. 452 (2010).
[11] M. Jo, D. Seong, S. Kim, J. Lee, W. Lee, J. Park, S. Park, S. Jung, J. Shin, D. Lee, H. Hwang, VLSI Tech. Dig. 53 (2010). [12] K.P. Biju, X. Liu, E.M. Bourim, I. Kim, S. Jung, M. Siddik, J. Lee, H. Hwang, J. Phys. D: Appl. Phys. 43 (2010) 495104. [13] J. Shin, I. Kim, K.P. Biju, M. Jo, J. Park, J. Lee, S. Jung, W. Lee, S. Kim, S. Park, H. Hwang, J. Appl. Phys. 109 (2011) 033712. [14] J. Liang, H.-S.P. Wong, IEEE Trans. Electron Dev. 57 (2010) 2531. [15] P.O. Vontobel, W. Robinett, P.J. Kuekes, D.R. Stewart, J. Straznicky, R.S. Williams, Nanotechnology 20 (2009) 425204. [16] J. Shin, J. Park, J. Lee, S. Park, S. Kim, W. Lee, I. Kim, D. Lee, H. Hwang, IEEE Electron Dev. Lett. 32 (2011) 958. [17] C.J. Amsinck, N.H.D. Spigna, D.P. Nackashi, P.D. Franzon, Nanotechnology 16 (2005) 2251.