- Email: [email protected]
D circuit design
Microelectronics Journal 44 (2013) 33–38
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Modelling of Carbon Nanotube Field Effect Transistors oriented to SPICE software for A/D circuit design Roberto Marani, Gennaro Gelao, Anna Gina Perri n Politecnico di Bari, Dipartimento di Elettrotecnica ed Elettronica, Laboratorio di Dispositivi Elettronici, Via E. Orabona 4, 70125 Bari, Italy
a r t i c l e i n f o
abstract
Article history: Received 22 June 2010 Received in revised form 10 May 2011 Accepted 28 July 2011 Available online 24 August 2011
We present a model of Carbon Nanotube Field Effect Transistors (CNTFETs) directly and easily implementable in simulation SPICE software for electronic circuit design. The model is based on analytical approximations and parameters extracted from quantum mechanical simulations of the device and depending on the nanotube diameter and the oxide capacitance. Comparison of the simulated output and transfer characteristics with those of a numerical model available online and with experimental data shows a relative error less than 5% in both cases. In order to determine the values of CNTFET equivalent circuit elements a new procedure, based on a best-fitting between the measured and simulated values of output device characteristics, has been proposed. To verify the versatility of the proposed model we use it in the SPICE simulator to design some A/D electronic circuits, demonstrating the importance of the quantum capacitance dependence on polarisation voltages and examining the effects of the CNT quantum resistances. & 2011 Elsevier Ltd. All rights reserved.
Keywords: Nanoelectronic devices Carbon Nanotube Field Effect Transistor (CNTFET) Modelling Analogue and Digital circuit design
1. Introduction Carbon Nanotube Field Effect Transistors (CNTFETs) are FETs using a carbon nanotube as a channel and are regarded as an important contending device to replace conventional silicon transistors [1]. The conventional CNTFETs, denoted as C-CNTFETs, with heavily doped source and drain contacts, show the best performances in terms of ‘‘on–off’’ ratio currents and subthreshold swing. About modelling issues, most of the CNTFET models available in literature are numerical and make use of self-consistency and therefore they cannot be directly implemented in circuit simulators, such as SPICE, Verilog or VHDL-AMS. In this paper we present a model of CNTFETs based on analytical approximations and parameters extracted from quantum mechanical simulations of the device and depending on the nanotube diameter and on the oxide capacitance. The structure of the model is to give it directly and easily implementable in the simulation SPICE software for the electronic circuit design. The CNTFET equivalent circuit is similar to the common MOSFET one in which we have numerically determined the flat band voltage and the resistances of the doped regions in series with the parasitic ones of the electrodes, commonly assumed equal to 25 kO (typical value of quantum resistance) by a best-fit
n
Corresponding author. Tel.: þ39 80 5963314/5963427; fax: þ 39 80 5963410. E-mail address: [email protected] (A.G. Perri).
0026-2692/$ - see front matter & 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2011.07.012
procedure between the measured and simulated values of output device characteristics, while the quantum capacitances have to be computed from the charge in the channel. In order to verify the accuracy of the model, the results have been compared with those of the numerical model FETToy [2] and of experimental data [3], with a negligible relative error in both cases (less than 5%). Moreover the good agreement between simulation and experimental results for a p-type CNTFET demonstrates the validity of the proposed model, born for an n-type CNTFET, also for this kind of devices. Finally we have used the model in the SPICE simulator to design some electronic circuits. In particular we have demonstrated the importance of the quantum capacitance dependence on polarisation voltages, while the effects of the CNT quantum resistances are absolutely relevant in the design of analogue circuits.
2. Model 2.1. I–V model The proposed model is based on the work of Raychowdhury et al. [4] and on the following improvements introduced by Pre´galdiny et al. [5,6]. The model, developed for an n-type CNTFET with semiconductor single wall carbon nanotube having diameters ranging from 1 nm to 4 nm, is based on the hypothesis of ballistic transport.
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R. Marani et al. / Microelectronics Journal 44 (2013) 33–38
In a CNTFET the conduction behaviour is similar to a common MOSFET one and the CNTFET works on the principle of barrierheight modulation by the application of a gate potential. With the hypothesis that each sub-band decreases by the same quantity along the whole channel length, the drain current for every single sub-band can be calculated using the Landauer formula [7,8] IDSp ¼
4qkT lnð1 þ expxSp Þlnð1þ exp xDp Þ h
ð1Þ
where q is the electron charge, k is the Boltzmann constant, T is the absolute temperature, h is the Planck constant and p is the number of sub-bands, while xSp and xDp have the following expressions:
xSp ¼
qVCNT ECp kT
and
xDp ¼
qVCNT ECp qVDS kT
ð2Þ
where ECp is the sub-bands conduction minimum, VCNT the surface potential and VDS the voltage applied between drain and source Therefore the total drain current can be expressed as [7] IDS ¼
4qkT X ½lnð1 þexpðxSp ÞÞlnð1þ expðxDp ÞÞ h p
2.2. C–V model To determine the quantum capacitances CGS and CGD, it is necessary to know the total channel charge QCNT, having the following expression: X QCNT ¼ q ðnSp þnDp Þ ð6Þ p
where nSp and nDp are electron concentrations by the source and the drain, respectively, in the pth sub-band. Having
ð3Þ N0 ¼
In order to evaluate the surface potential VCNT, the following approximation has been proposed [4]: 8 for VGS o EqC < VGS VCNT ¼ ð4Þ : VGS a VGS EqC for VGS Z EqC where EC is the conduction band minimum for the first sub-band. The parameter a depends on the VDS voltage and has the following expression: 2 a ¼ a0 þ a1 VDS þ a2 VDS
For VDS Z3 V we assume that IDS current has reached its saturation value, like in the MOSFET model. Moreover from Fig. 2, which shows the computed values of current IDS versus VDS determined considering one, two, three and more sub-bands, we have verified that only three sub-bands are sufficient to describe the output characteristics of the CNTFET with a relative error, referring to the IDS values of the FETToy numerical model [2], less than 5%. This good agreement demonstrates the validity of our approach.
ð5Þ
4kT 3pa0 9g9
ð7Þ
where a0 is the carbon–carbon (C–C) bonding distance (E0.142 nm) and g the C–C bonding energy (E3 eV), the number of carriers nip(i¼i or D), which increases almost linearly for xip greater or equal than zero and falls off exponentially as xip becomes negative, can be derived from the following relationship [6]: ( Ap exp xip for xip o0 nip ¼ N0 , i ¼ S,D ð8Þ Bp xip þ Ap for xip Z0 where the parameters Ap and Bp depend on ECp; for ECp o0.5 eV have the following empirical expressions [6]: ( Ap ¼ 5:3E2Cp þ10ECp þ 1 ð9Þ Bp ¼ 0:34ECp þ 1
where a0, a1 and a2, functions of both CNTFET diameter and gate oxide capacitance Cox, must be extracted from the experimental device characteristics [8]. As the a parameter cannot assume negative values, in [8] we have demonstrated that the model describes the behaviour of CNTFET, having diameter between 1 nm and 4 nm, with a maximum value of VDS equal to about 5 V. However Fig. 1, in which we have reported the IDS values versus VDS for different values of VGS, shows that to assert the model can describe the behaviour of CNTFET well with a maximum value of VDS equal to 3 V.
However VCNT (VGS) and its derivative are not continuous for VGS ¼(ECp/q).
Fig. 1. IDS versus VDS for different values of VGS.
Fig. 2. IDS versus VDS for pZ 1.
Therefore the quantum capacitances CGD and CGS are given by 8 P @nDp P @nDp @xDp @VCNT > > < CGD ¼ q p @VGS ¼ q p @xDp @VCNT @VGS ð10Þ P @nSp P @nSp @xSp @V > > : CGS ¼ q @VGS ¼ q @xSp @VCNT @VCNT GS p
p
R. Marani et al. / Microelectronics Journal 44 (2013) 33–38
This problem can be solved by replacing Eq. (4) with the following relationship: qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi aðVGS ðEC =qÞÞ þ ½aðVGS ðEC =qÞÞ2 þ 4e2 ð11Þ VCNT ¼ VGS 2 in which a smoothing parameter e, assumed equal to 0.05 V [5], has been introduced. The difference between Eqs. (4) and (11) is negligible when VGS is outside the range [(EC/q) 2e, (EC/q)þ2e]. Also nip (xip) is not continuous for VGS ¼ (ECp/q). In this case for nip (xip) an equation similar to the interpolation function of the EKV MOSFET model is convenient [9]: 0:96 xip Ap nip ¼ N0 1:2Bp ln 1 þ exp ð12Þ 1:2Bp 0:96 In the proposed algorithm we have not used the relationship (4) to calculate @VCNT/@VGS(and also @nip/@xip), because some convergence issues occur during the SPICE simulation. Therefore @VCNT/@VGS has been evaluated by the SOFTLIM block of ABM SPICE library as @VCNT EC a 1a SOFTLIM VGS a þ 0:5, ð13Þ @VGS q 4e
35
Some authors have assumed these parameters fixed to constant and typical values (i.e. VFB ¼0 V [5] and RD ¼RS ¼25 kO [10,11]), thus losing the dependence of flat band voltage on the CNT diameter. In our work we have extracted VFB, RD and RS by a best-fit procedure between the measured and simulated values of I–V characteristics of the device, while the quantum capacitances have been computed from the charge in the channel [8]. Fig. 4 compares the IDS–VDS characteristics (denoted by continuous lines) of numerical simulations according to our procedure and the experimental ones [3] (denoted by þ), in which we have assumed the same values for VFB, CNT diameter, RD and RS reported in [3]. In order to obtain a better agreement we have numerically determined the flat band voltage, the CNT diameter and the resistances of the drain and source regions by a best-fit procedure between the measured and simulated values of IDS–VDS characteristics of the device, obtaining VFB ¼1.297 V, CNT diameter¼2 nm, RD ¼87.51 kO and RS ¼67,398 kO with an optimal value of the smoothing parameter e equal to 0.167 V. The results are shown in Fig. 5.
Since the SOFTLIM block is obtained using hyperbolic tangent, which is an analytical function, numerical problems are avoided and in this way the quantum capacitances become continuous and derivable functions without any convergence problem. Moreover, since the a/4e term must be fixed in the SOFTLIM block, we have assigned a mean value to it. Further details regarding the C–V model of CNTFET can be found in [8]. 2.3. CNTFET equivalent circuit The equivalent circuit of an n-type CNTFET is shown in Fig. 3. The voltage generator describes the flat band voltage VFB, whose values depend on the CNT diameter, while RD and RS represent the resistances of the doped drain and source regions, respectively, with the parasitic ones of the electrodes. Fig. 4. Simulated IDS–VDS characteristics (denoted by continuous lines) and experimental IDS–VDS characteristics [3] (denoted by þ ).
D RD 25k 2 LD 200pH CGD
1
VFB G
IDS 2
CDS
LS 200pH 1 RS 25k S
Fig. 3. Equivalent circuit of an n-type CNTFET.
Fig. 5. Simulated IDS–VDS characteristics (denoted by continuous lines, with optimal values of VFB, CNT diameter, RD and RS) and experimental IDS–VDS characteristics [3] (denoted by þ ).
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R. Marani et al. / Microelectronics Journal 44 (2013) 33–38
This comparison shows that there is a good agreement between simulation and experimental results, particularly in the saturation region, where the percent error is practically negligible. Moreover the proposed best-fit procedure allows extraction, from the measured IDS–VDS characteristics of the device, of the optimal values of the CNTFET equivalent circuit elements. Fig. 6 compares the simulated IDS–VGS characteristics (denoted by x) by our procedure and the numerical IDS–VGS characteristics (denoted by þ) [2], in which we have assumed VFB ¼ 0 V, CNT diameter¼1.4 nm, RD ¼RS ¼0 O and Cox ¼3.8 pF/cm. Moreover it is important to highlight that the experimental curves [3] are referred to an p-type CNTFET and the good agreement demonstrates the validity of our model, born for an n-type CNTFET, also to describe this kind of devices.
3. Circuit simulations 3.1. Analogue circuit simulation In order to verify the versatility of our model, we have used it to design some electronic circuits. In all simulations we have considered CNTFETs having a diameter of 1.42 nm, length of 100 nm and quantum capacitances depending on polarisation voltages. Fig. 7 shows a CNTFET amplifier in common-source configuration, whose circuit data are reported in the figure.
Fig. 6. Modelled IDS–VGS characteristics (denoted by x) and numerical IDS–VGS characteristics [2] (denoted by þ).
Fig. 7. CNTFET amplifier in common-source configuration.
Fig. 8 shows the Bode diagrams of the simulated amplifier, in which we have considered the resistances of the doped drain and source regions equal to 25 kO. From Fig. 8 it is easy to see that the high cut-off frequency is equal to 1.9 THz and the voltage gain is about 12 dB at 100 GHz, while it becomes about 0 dB at 10 THz. It is important to underline that we have obtained Fig. 8 considering in the CNTFET model also the classical inductance of 400 pH, which we have splitted up into two inductances of 200 pH in the source and drain terminals. In order to verify the effect of the quantum resistances RS and RD, we have considered RS ¼ RD ¼0 O and source and drain inductances of both 200 pH. In this case we have only an increase of the voltage gain, which is about 18 dB at 100 GHz, while the high cut-off frequency, equal to 1.6 THz, is practically the same. Moreover, when we assume RD ¼ RS ¼0 O, the effects of source and drain inductances cannot be neglected if their values decrease. In fact, considering source and drain inductances of both 1 pH, without RS and RD, we have only an increase of the high cut-off frequency, which becomes 41.2 THz, while the voltage gain has the same value (18 dB at 100 GHz). 3.2. Digital circuit simulation To verify the possibility to employ the proposed model also in the design of digital circuits, we have studied NOT gates in a four stage chain, as shown in Fig. 9, whose circuit data are shown in the figure. Each NOT is designed with 3 identical CNTFETs, the upper two working as dynamic load while resistors represent parasitic elements. In all simulations we have considered CNTFETs of 1.42 nm diameter, 100 nm length and quantum capacitances depending on polarisation voltages. Fig. 10 shows the transfer function of each stage of NOT gates architecture, where each output is loaded by the gate input of the next. This figure also allows defining the logic level ranges for the input and output at power supply voltage equal to 0.6 V. Moreover, from Fig. 10, it is possible to evaluate the noise margins, which are 0.2 V for high level and 0.1 V for low level. Fig. 11 shows the result of a transient simulation to validate the dynamic behaviour of the CNT-based NOT gates driven by a 14 ps clock, verifying that the dynamic variation of CGD and CGS is important. In fact we have repeated the simulation with fixed values capacitance, the same for all CNTFET. We used average capacitance
Fig. 8. Bode diagrams of CS CNTFET amplifier with resistances RS and RD equal to 25 kO.
R. Marani et al. / Microelectronics Journal 44 (2013) 33–38 5
4
D
3
Ref3
VSupply
G GG001
D
G
S
GG001
0
G
G
S
GG001
B
G GG001
G GG001 R2
R1
0
S
G
D
0
GG001
G GG001 R5
0
S
D
G GG001
R7
0
R12 1e9
G
S
GG001 R8 1e9
D
G GG001
R10
C
0
D S
R11 1e9
Ref10
0
S
1e9
0
S
Ref11
0
Ref7
1e9 D
D
1e9 Ref8
S
1e9
0
0
GG001
R4
1e9
G
S R9
0
Ref4
1e9 D
D
1e9 Ref5
S
Ref1
Vin
D
D
Ref12
R6
0
D
1
Ref9
1e9 Ref2
GG001
2
Ref6
R3
C
37
D
0
S
B
1e9
0
0
0
0
A
A
5
4
3
2
1
Fig. 9. Schematic of the circuit used to simulate the behaviour of the three NOT gates.
450mV 375mV
250mV
125mV 50mV 25ps
30ps V (NOT1 : OUT)
Fig. 10. Transfer function of the circuit shown in Fig. 9.
35ps V (NOT2 : OUT) Time
40ps
45ps
V (NOT3 : OUT)
Fig. 12. Same as in Fig. 11 but with fixed capacitance values.
Fig. 11. Transient simulation of the CNT-based NOT gates. The output of the first NOT is marked with squares, the second with diamonds and the third with triangles.
The result is shown in Fig. 12, where it is easy to see that the signal is strongly degraded when it propagates in the circuit, while the simulation of Fig. 11, in which we have considered quantum capacitances depending on the polarisation voltages, shows a better behaviour. Finally, we have studied NAND gates in a five-stage chain, as shown in Fig. 13. Fig. 14 shows the result of the transient simulation, in which we have considered quantum capacitances, CGD and CGS, depending on the polarisation voltages and RD and RS equal to 25 kO. If these resistances are neglected, we have verified that both transfer function and the transient behaviour of circuits of Figs. 9 and 13 are practically unchanged.
4. Conclusions values for CNTFET in this circuit, that is to say CGD ¼1.5 pF (1 pF for quantum effects and 0.5 pF for classical effects) and CDS ¼3 pF (2 pF for quantum effects and 1 pF for classical effects).
In this paper we have presented a semi-empirical CNTFET model, whose structure is to give it directly and easily implementable in circuit simulator, such as SPICE.
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R. Marani et al. / Microelectronics Journal 44 (2013) 33–38
4
5
1
2
D
+Vcc
InB
InA InB
Out
InA InB
Out
NAND
NA4 InA InB
Out
NAND
NA5 InA InB
+Vcc -Vcc
IN
Out
NAND
NA3
+Vcc -Vcc
InA
+Vcc -Vcc
C
NAND
NA2
+Vcc -Vcc
NAND
NA1
+Vcc -Vcc
D
3
C
Out R1 1E8
B
B
0 A
A
0 5
4
3
2
1
Fig. 13. Schematic of the circuit used to simulate the behaviour of the NAND gate.
800mV
600mV
400mV
200mV
0V
-200mV 0s 50ps 100ps 150ps 200ps 250ps 300ps V (NA1 : OUT) V (NA2 : OUT) V (NA3 : OUT) V (NA4 : OUT) V (NA5 : OUT) Time Fig. 14. Transfer function of the circuit shown in Fig. 13.
To verify the accuracy of the model the results have been compared with those of a numerical model and of experimental data, with a negligible relative error in both cases. Moreover we have proposed a new procedure to determine numerically the flat band voltage, the CNT diameter and the resistances of the drain and source regions, based on a best-fitting between the measured and simulated values of output device characteristics, obtaining a better agreement between simulation and experimental results, particularly in the saturation region, where the percent error is practically negligible. The proposed best-fit procedure also allows extraction of the optimal values of CNTFET equivalent circuit elements. Finally we have employed the proposed model to design some A/D electronics circuits. In particular we have demonstrated the importance of the quantum capacitance dependence on polarisation voltages, while the effects of the CNT quantum resistances are absolutely relevant in the design of analogue circuits. References [1] Ph. Avouris, M. Radosavljevic´, S.J. Wind, Carbon nanotube electronics and optoelectronics, in: Applied Physics of Carbon Nanotubes: Fundamentals of Theory, Optics and Transport Devices, Springer–Verlag, Berlin, Germany, 2005 ISBN: 978-3-540-23110-3.
[2] A. Rahman, J. Wang , J. Guo, M.d.S. Hassan, Y. Liu, A. Matsudaira, S. Ahmed, S. Datta, M. Lundstrom, FETToy, (2006), /http://www.nanohub.orgS. [3] A. Javey, H. Kim, M. Brink, Q. Wang, A. Ural, J. Guo, P. Mcintyre, P. Mceuen, M. Lundstrom, M. Dai, High-K dielectrics for advanced carbon nanotube transistors and logic gates, Nature Materials (2002) 241–246. [4] A. Raychowdhury, S. Mukhopadhyay, K. Roy, A circuit-compatible model of ballistic carbon nanotube field-effect transistors, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23 (2004) 1411–1420. [5] F. Pre´galdiny, C. Lallement, J.B. Kammerer, Design-oriented compact models for CNTFETs, in: Proceedings of the International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006, pp. 34–39. [6] F. Pre´galdiny, C. Lallement, B. Diange, M. Sallese, M. Krummenacher, Compact modeling of emerging technologies with VHDL-AMS, in Advances in: Design and Specification Languages for Embedded Systems, Springer, Netherlands, 2007 ISBN: 978-1-4020-6147-9. [7] S. Datta, Electronic Transport in Mesoscopic Systems, in Cambridge Studies in: Semiconductor Physics and Microelectronic Engineering 3, Cambridge University Press, New York, 1995 ISBN: 978-0-521-599943-6. [8] R. Marani, A.G. Perri, A compact, semi-empirical model of carbon nanotube field effect transistors oriented to simulation software, Current Nanoscience 7 (2) (2011) 245–253. [9] P.J. Burke, AC performance of nanoelectronics: towards a ballistic THz nanotube transistor, Solid-State Electronics 48 (2004) 1981–1986. [10] I. O’Connor, J. Liu, F. Gaffiot, F. Pre´galdiny, C. Lallement, C. Maneux, J. Goguet, S. Fre´gone se, T. Zimmer, L. Anghel, T. Dang, R. Leveugle, CNTFET modeling and reconfigurable logic-circuit design, IEEE Transactions on Circuits and Systems I 54 (11) (2007) 2365–2379. [11] C. Maneux, J. Goguet, S. Fre´gone se, T. Zimmer, Analysis of CNTFET physical compact model, in: Proceedings of the International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006, pp. 40–45.
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Modelling of Carbon Nanotube Field Effect Transistors oriented to SPICE software for A/D circuit design Roberto Marani, Gennaro Gelao, Anna Gina Perri n Politecnico di Bari, Dipartimento di Elettrotecnica ed Elettronica, Laboratorio di Dispositivi Elettronici, Via E. Orabona 4, 70125 Bari, Italy
a r t i c l e i n f o
abstract
Article history: Received 22 June 2010 Received in revised form 10 May 2011 Accepted 28 July 2011 Available online 24 August 2011
We present a model of Carbon Nanotube Field Effect Transistors (CNTFETs) directly and easily implementable in simulation SPICE software for electronic circuit design. The model is based on analytical approximations and parameters extracted from quantum mechanical simulations of the device and depending on the nanotube diameter and the oxide capacitance. Comparison of the simulated output and transfer characteristics with those of a numerical model available online and with experimental data shows a relative error less than 5% in both cases. In order to determine the values of CNTFET equivalent circuit elements a new procedure, based on a best-fitting between the measured and simulated values of output device characteristics, has been proposed. To verify the versatility of the proposed model we use it in the SPICE simulator to design some A/D electronic circuits, demonstrating the importance of the quantum capacitance dependence on polarisation voltages and examining the effects of the CNT quantum resistances. & 2011 Elsevier Ltd. All rights reserved.
Keywords: Nanoelectronic devices Carbon Nanotube Field Effect Transistor (CNTFET) Modelling Analogue and Digital circuit design
1. Introduction Carbon Nanotube Field Effect Transistors (CNTFETs) are FETs using a carbon nanotube as a channel and are regarded as an important contending device to replace conventional silicon transistors [1]. The conventional CNTFETs, denoted as C-CNTFETs, with heavily doped source and drain contacts, show the best performances in terms of ‘‘on–off’’ ratio currents and subthreshold swing. About modelling issues, most of the CNTFET models available in literature are numerical and make use of self-consistency and therefore they cannot be directly implemented in circuit simulators, such as SPICE, Verilog or VHDL-AMS. In this paper we present a model of CNTFETs based on analytical approximations and parameters extracted from quantum mechanical simulations of the device and depending on the nanotube diameter and on the oxide capacitance. The structure of the model is to give it directly and easily implementable in the simulation SPICE software for the electronic circuit design. The CNTFET equivalent circuit is similar to the common MOSFET one in which we have numerically determined the flat band voltage and the resistances of the doped regions in series with the parasitic ones of the electrodes, commonly assumed equal to 25 kO (typical value of quantum resistance) by a best-fit
n
Corresponding author. Tel.: þ39 80 5963314/5963427; fax: þ 39 80 5963410. E-mail address: [email protected] (A.G. Perri).
0026-2692/$ - see front matter & 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2011.07.012
procedure between the measured and simulated values of output device characteristics, while the quantum capacitances have to be computed from the charge in the channel. In order to verify the accuracy of the model, the results have been compared with those of the numerical model FETToy [2] and of experimental data [3], with a negligible relative error in both cases (less than 5%). Moreover the good agreement between simulation and experimental results for a p-type CNTFET demonstrates the validity of the proposed model, born for an n-type CNTFET, also for this kind of devices. Finally we have used the model in the SPICE simulator to design some electronic circuits. In particular we have demonstrated the importance of the quantum capacitance dependence on polarisation voltages, while the effects of the CNT quantum resistances are absolutely relevant in the design of analogue circuits.
2. Model 2.1. I–V model The proposed model is based on the work of Raychowdhury et al. [4] and on the following improvements introduced by Pre´galdiny et al. [5,6]. The model, developed for an n-type CNTFET with semiconductor single wall carbon nanotube having diameters ranging from 1 nm to 4 nm, is based on the hypothesis of ballistic transport.
34
R. Marani et al. / Microelectronics Journal 44 (2013) 33–38
In a CNTFET the conduction behaviour is similar to a common MOSFET one and the CNTFET works on the principle of barrierheight modulation by the application of a gate potential. With the hypothesis that each sub-band decreases by the same quantity along the whole channel length, the drain current for every single sub-band can be calculated using the Landauer formula [7,8] IDSp ¼
4qkT lnð1 þ expxSp Þlnð1þ exp xDp Þ h
ð1Þ
where q is the electron charge, k is the Boltzmann constant, T is the absolute temperature, h is the Planck constant and p is the number of sub-bands, while xSp and xDp have the following expressions:
xSp ¼
qVCNT ECp kT
and
xDp ¼
qVCNT ECp qVDS kT
ð2Þ
where ECp is the sub-bands conduction minimum, VCNT the surface potential and VDS the voltage applied between drain and source Therefore the total drain current can be expressed as [7] IDS ¼
4qkT X ½lnð1 þexpðxSp ÞÞlnð1þ expðxDp ÞÞ h p
2.2. C–V model To determine the quantum capacitances CGS and CGD, it is necessary to know the total channel charge QCNT, having the following expression: X QCNT ¼ q ðnSp þnDp Þ ð6Þ p
where nSp and nDp are electron concentrations by the source and the drain, respectively, in the pth sub-band. Having
ð3Þ N0 ¼
In order to evaluate the surface potential VCNT, the following approximation has been proposed [4]: 8 for VGS o EqC < VGS VCNT ¼ ð4Þ : VGS a VGS EqC for VGS Z EqC where EC is the conduction band minimum for the first sub-band. The parameter a depends on the VDS voltage and has the following expression: 2 a ¼ a0 þ a1 VDS þ a2 VDS
For VDS Z3 V we assume that IDS current has reached its saturation value, like in the MOSFET model. Moreover from Fig. 2, which shows the computed values of current IDS versus VDS determined considering one, two, three and more sub-bands, we have verified that only three sub-bands are sufficient to describe the output characteristics of the CNTFET with a relative error, referring to the IDS values of the FETToy numerical model [2], less than 5%. This good agreement demonstrates the validity of our approach.
ð5Þ
4kT 3pa0 9g9
ð7Þ
where a0 is the carbon–carbon (C–C) bonding distance (E0.142 nm) and g the C–C bonding energy (E3 eV), the number of carriers nip(i¼i or D), which increases almost linearly for xip greater or equal than zero and falls off exponentially as xip becomes negative, can be derived from the following relationship [6]: ( Ap exp xip for xip o0 nip ¼ N0 , i ¼ S,D ð8Þ Bp xip þ Ap for xip Z0 where the parameters Ap and Bp depend on ECp; for ECp o0.5 eV have the following empirical expressions [6]: ( Ap ¼ 5:3E2Cp þ10ECp þ 1 ð9Þ Bp ¼ 0:34ECp þ 1
where a0, a1 and a2, functions of both CNTFET diameter and gate oxide capacitance Cox, must be extracted from the experimental device characteristics [8]. As the a parameter cannot assume negative values, in [8] we have demonstrated that the model describes the behaviour of CNTFET, having diameter between 1 nm and 4 nm, with a maximum value of VDS equal to about 5 V. However Fig. 1, in which we have reported the IDS values versus VDS for different values of VGS, shows that to assert the model can describe the behaviour of CNTFET well with a maximum value of VDS equal to 3 V.
However VCNT (VGS) and its derivative are not continuous for VGS ¼(ECp/q).
Fig. 1. IDS versus VDS for different values of VGS.
Fig. 2. IDS versus VDS for pZ 1.
Therefore the quantum capacitances CGD and CGS are given by 8 P @nDp P @nDp @xDp @VCNT > > < CGD ¼ q p @VGS ¼ q p @xDp @VCNT @VGS ð10Þ P @nSp P @nSp @xSp @V > > : CGS ¼ q @VGS ¼ q @xSp @VCNT @VCNT GS p
p
R. Marani et al. / Microelectronics Journal 44 (2013) 33–38
This problem can be solved by replacing Eq. (4) with the following relationship: qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi aðVGS ðEC =qÞÞ þ ½aðVGS ðEC =qÞÞ2 þ 4e2 ð11Þ VCNT ¼ VGS 2 in which a smoothing parameter e, assumed equal to 0.05 V [5], has been introduced. The difference between Eqs. (4) and (11) is negligible when VGS is outside the range [(EC/q) 2e, (EC/q)þ2e]. Also nip (xip) is not continuous for VGS ¼ (ECp/q). In this case for nip (xip) an equation similar to the interpolation function of the EKV MOSFET model is convenient [9]: 0:96 xip Ap nip ¼ N0 1:2Bp ln 1 þ exp ð12Þ 1:2Bp 0:96 In the proposed algorithm we have not used the relationship (4) to calculate @VCNT/@VGS(and also @nip/@xip), because some convergence issues occur during the SPICE simulation. Therefore @VCNT/@VGS has been evaluated by the SOFTLIM block of ABM SPICE library as @VCNT EC a 1a SOFTLIM VGS a þ 0:5, ð13Þ @VGS q 4e
35
Some authors have assumed these parameters fixed to constant and typical values (i.e. VFB ¼0 V [5] and RD ¼RS ¼25 kO [10,11]), thus losing the dependence of flat band voltage on the CNT diameter. In our work we have extracted VFB, RD and RS by a best-fit procedure between the measured and simulated values of I–V characteristics of the device, while the quantum capacitances have been computed from the charge in the channel [8]. Fig. 4 compares the IDS–VDS characteristics (denoted by continuous lines) of numerical simulations according to our procedure and the experimental ones [3] (denoted by þ), in which we have assumed the same values for VFB, CNT diameter, RD and RS reported in [3]. In order to obtain a better agreement we have numerically determined the flat band voltage, the CNT diameter and the resistances of the drain and source regions by a best-fit procedure between the measured and simulated values of IDS–VDS characteristics of the device, obtaining VFB ¼1.297 V, CNT diameter¼2 nm, RD ¼87.51 kO and RS ¼67,398 kO with an optimal value of the smoothing parameter e equal to 0.167 V. The results are shown in Fig. 5.
Since the SOFTLIM block is obtained using hyperbolic tangent, which is an analytical function, numerical problems are avoided and in this way the quantum capacitances become continuous and derivable functions without any convergence problem. Moreover, since the a/4e term must be fixed in the SOFTLIM block, we have assigned a mean value to it. Further details regarding the C–V model of CNTFET can be found in [8]. 2.3. CNTFET equivalent circuit The equivalent circuit of an n-type CNTFET is shown in Fig. 3. The voltage generator describes the flat band voltage VFB, whose values depend on the CNT diameter, while RD and RS represent the resistances of the doped drain and source regions, respectively, with the parasitic ones of the electrodes. Fig. 4. Simulated IDS–VDS characteristics (denoted by continuous lines) and experimental IDS–VDS characteristics [3] (denoted by þ ).
D RD 25k 2 LD 200pH CGD
1
VFB G
IDS 2
CDS
LS 200pH 1 RS 25k S
Fig. 3. Equivalent circuit of an n-type CNTFET.
Fig. 5. Simulated IDS–VDS characteristics (denoted by continuous lines, with optimal values of VFB, CNT diameter, RD and RS) and experimental IDS–VDS characteristics [3] (denoted by þ ).
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R. Marani et al. / Microelectronics Journal 44 (2013) 33–38
This comparison shows that there is a good agreement between simulation and experimental results, particularly in the saturation region, where the percent error is practically negligible. Moreover the proposed best-fit procedure allows extraction, from the measured IDS–VDS characteristics of the device, of the optimal values of the CNTFET equivalent circuit elements. Fig. 6 compares the simulated IDS–VGS characteristics (denoted by x) by our procedure and the numerical IDS–VGS characteristics (denoted by þ) [2], in which we have assumed VFB ¼ 0 V, CNT diameter¼1.4 nm, RD ¼RS ¼0 O and Cox ¼3.8 pF/cm. Moreover it is important to highlight that the experimental curves [3] are referred to an p-type CNTFET and the good agreement demonstrates the validity of our model, born for an n-type CNTFET, also to describe this kind of devices.
3. Circuit simulations 3.1. Analogue circuit simulation In order to verify the versatility of our model, we have used it to design some electronic circuits. In all simulations we have considered CNTFETs having a diameter of 1.42 nm, length of 100 nm and quantum capacitances depending on polarisation voltages. Fig. 7 shows a CNTFET amplifier in common-source configuration, whose circuit data are reported in the figure.
Fig. 6. Modelled IDS–VGS characteristics (denoted by x) and numerical IDS–VGS characteristics [2] (denoted by þ).
Fig. 7. CNTFET amplifier in common-source configuration.
Fig. 8 shows the Bode diagrams of the simulated amplifier, in which we have considered the resistances of the doped drain and source regions equal to 25 kO. From Fig. 8 it is easy to see that the high cut-off frequency is equal to 1.9 THz and the voltage gain is about 12 dB at 100 GHz, while it becomes about 0 dB at 10 THz. It is important to underline that we have obtained Fig. 8 considering in the CNTFET model also the classical inductance of 400 pH, which we have splitted up into two inductances of 200 pH in the source and drain terminals. In order to verify the effect of the quantum resistances RS and RD, we have considered RS ¼ RD ¼0 O and source and drain inductances of both 200 pH. In this case we have only an increase of the voltage gain, which is about 18 dB at 100 GHz, while the high cut-off frequency, equal to 1.6 THz, is practically the same. Moreover, when we assume RD ¼ RS ¼0 O, the effects of source and drain inductances cannot be neglected if their values decrease. In fact, considering source and drain inductances of both 1 pH, without RS and RD, we have only an increase of the high cut-off frequency, which becomes 41.2 THz, while the voltage gain has the same value (18 dB at 100 GHz). 3.2. Digital circuit simulation To verify the possibility to employ the proposed model also in the design of digital circuits, we have studied NOT gates in a four stage chain, as shown in Fig. 9, whose circuit data are shown in the figure. Each NOT is designed with 3 identical CNTFETs, the upper two working as dynamic load while resistors represent parasitic elements. In all simulations we have considered CNTFETs of 1.42 nm diameter, 100 nm length and quantum capacitances depending on polarisation voltages. Fig. 10 shows the transfer function of each stage of NOT gates architecture, where each output is loaded by the gate input of the next. This figure also allows defining the logic level ranges for the input and output at power supply voltage equal to 0.6 V. Moreover, from Fig. 10, it is possible to evaluate the noise margins, which are 0.2 V for high level and 0.1 V for low level. Fig. 11 shows the result of a transient simulation to validate the dynamic behaviour of the CNT-based NOT gates driven by a 14 ps clock, verifying that the dynamic variation of CGD and CGS is important. In fact we have repeated the simulation with fixed values capacitance, the same for all CNTFET. We used average capacitance
Fig. 8. Bode diagrams of CS CNTFET amplifier with resistances RS and RD equal to 25 kO.
R. Marani et al. / Microelectronics Journal 44 (2013) 33–38 5
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Fig. 9. Schematic of the circuit used to simulate the behaviour of the three NOT gates.
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Fig. 12. Same as in Fig. 11 but with fixed capacitance values.
Fig. 11. Transient simulation of the CNT-based NOT gates. The output of the first NOT is marked with squares, the second with diamonds and the third with triangles.
The result is shown in Fig. 12, where it is easy to see that the signal is strongly degraded when it propagates in the circuit, while the simulation of Fig. 11, in which we have considered quantum capacitances depending on the polarisation voltages, shows a better behaviour. Finally, we have studied NAND gates in a five-stage chain, as shown in Fig. 13. Fig. 14 shows the result of the transient simulation, in which we have considered quantum capacitances, CGD and CGS, depending on the polarisation voltages and RD and RS equal to 25 kO. If these resistances are neglected, we have verified that both transfer function and the transient behaviour of circuits of Figs. 9 and 13 are practically unchanged.
4. Conclusions values for CNTFET in this circuit, that is to say CGD ¼1.5 pF (1 pF for quantum effects and 0.5 pF for classical effects) and CDS ¼3 pF (2 pF for quantum effects and 1 pF for classical effects).
In this paper we have presented a semi-empirical CNTFET model, whose structure is to give it directly and easily implementable in circuit simulator, such as SPICE.
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R. Marani et al. / Microelectronics Journal 44 (2013) 33–38
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-200mV 0s 50ps 100ps 150ps 200ps 250ps 300ps V (NA1 : OUT) V (NA2 : OUT) V (NA3 : OUT) V (NA4 : OUT) V (NA5 : OUT) Time Fig. 14. Transfer function of the circuit shown in Fig. 13.
To verify the accuracy of the model the results have been compared with those of a numerical model and of experimental data, with a negligible relative error in both cases. Moreover we have proposed a new procedure to determine numerically the flat band voltage, the CNT diameter and the resistances of the drain and source regions, based on a best-fitting between the measured and simulated values of output device characteristics, obtaining a better agreement between simulation and experimental results, particularly in the saturation region, where the percent error is practically negligible. The proposed best-fit procedure also allows extraction of the optimal values of CNTFET equivalent circuit elements. Finally we have employed the proposed model to design some A/D electronics circuits. In particular we have demonstrated the importance of the quantum capacitance dependence on polarisation voltages, while the effects of the CNT quantum resistances are absolutely relevant in the design of analogue circuits. References [1] Ph. Avouris, M. Radosavljevic´, S.J. Wind, Carbon nanotube electronics and optoelectronics, in: Applied Physics of Carbon Nanotubes: Fundamentals of Theory, Optics and Transport Devices, Springer–Verlag, Berlin, Germany, 2005 ISBN: 978-3-540-23110-3.
[2] A. Rahman, J. Wang , J. Guo, M.d.S. Hassan, Y. Liu, A. Matsudaira, S. Ahmed, S. Datta, M. Lundstrom, FETToy, (2006), /http://www.nanohub.orgS. [3] A. Javey, H. Kim, M. Brink, Q. Wang, A. Ural, J. Guo, P. Mcintyre, P. Mceuen, M. Lundstrom, M. Dai, High-K dielectrics for advanced carbon nanotube transistors and logic gates, Nature Materials (2002) 241–246. [4] A. Raychowdhury, S. Mukhopadhyay, K. Roy, A circuit-compatible model of ballistic carbon nanotube field-effect transistors, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23 (2004) 1411–1420. [5] F. Pre´galdiny, C. Lallement, J.B. Kammerer, Design-oriented compact models for CNTFETs, in: Proceedings of the International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006, pp. 34–39. [6] F. Pre´galdiny, C. Lallement, B. Diange, M. Sallese, M. Krummenacher, Compact modeling of emerging technologies with VHDL-AMS, in Advances in: Design and Specification Languages for Embedded Systems, Springer, Netherlands, 2007 ISBN: 978-1-4020-6147-9. [7] S. Datta, Electronic Transport in Mesoscopic Systems, in Cambridge Studies in: Semiconductor Physics and Microelectronic Engineering 3, Cambridge University Press, New York, 1995 ISBN: 978-0-521-599943-6. [8] R. Marani, A.G. Perri, A compact, semi-empirical model of carbon nanotube field effect transistors oriented to simulation software, Current Nanoscience 7 (2) (2011) 245–253. [9] P.J. Burke, AC performance of nanoelectronics: towards a ballistic THz nanotube transistor, Solid-State Electronics 48 (2004) 1981–1986. [10] I. O’Connor, J. Liu, F. Gaffiot, F. Pre´galdiny, C. Lallement, C. Maneux, J. Goguet, S. Fre´gone se, T. Zimmer, L. Anghel, T. Dang, R. Leveugle, CNTFET modeling and reconfigurable logic-circuit design, IEEE Transactions on Circuits and Systems I 54 (11) (2007) 2365–2379. [11] C. Maneux, J. Goguet, S. Fre´gone se, T. Zimmer, Analysis of CNTFET physical compact model, in: Proceedings of the International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006, pp. 40–45.