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Molecular layer epitaxy
Thin Solid Films 367 (2000) 13±24 www.elsevier.com/locate/tsf
Molecular layer epitaxy Jun-ichi Nishizawa a,b,*, Toru Kurabayashi a,b a
Telecommunications Advancement Organization, Sendai Research Center, Koeji 19, Nagamachi-Aza Aoba-ku, Sendai 980-0868, Japan b Semiconductor Research Institute of Semiconductor Research Foundation, Kawauchi, Aoba-ku, Sendai 980-0862, Japan
Abstract Molecular layer epitaxy (MLE) of GaAs related compounds and Si with SiO2 deposition has been developed to realize the tera-hertz operating devices. At suf®ciently low process temperature, lower than in the conventional growth method, device quality epitaxial layers Ê scale static induction transistors are fabricated with MLE. These transistors operated in a mixed were achieved by MLE. In GaAs, 100 A ballistic-tunneling mode or in the pure tunneling mode. Basic research on MLE in the ®eld of surface science and material science is performed, from the point of view of device application of this technology. q 2000 Elsevier Science S.A. All rights reserved. Keywords: Molecular layer epitaxy of GaAs, InP and Si; Static induction transistor technology; GaAs tera-hertz devices grown by molecular layer epitaxy
1. Introduction Optical communication network systems with remarkable larger information capacity as Tera-bit/s, 1000 times larger than conventional Giga-bit/s transmission are urgently required. In such demand, high-speed devices operating in tera-hertz frequency should be developed. Static induction transistors (SIT) [1,2] or tunnel mode transit time diodes (TUNNETT) [3±5] are suitable as tera-herz devices. SIT is a kind of the ®eld effect transistor with a very short channel, or the bipolar transistor with an ultimately thin base layer. Therefore, SIT operates with the highest speed among them. In the case when the channel in SIT is made shorter than the mean free path of electrons, then injected electrons travel from source to the intrinsic gate without collision into lattice atoms. Nishizawa estiÊ mated the cut-off frequency of 718 GHz for a 1000 A GaAs SIT [6]. This transistor was called `Ideal SIT (ISIT)'. Later, Shur and Eastman estimated a similar cutoff frequency, and called the scattering free transport as `ballistic' [7]. The quasi ballistic transport at the cryogenic temperature was veri®ed in III-V compound semiconductor devices, like planar doped barrier transistors [8] and tunneling hot electron transfer ampli®ers (THETA) [9]. Dependence of a cut-off frequency on a collector-emitter voltage indicates a signi®cant overshoot of electron velocity in heterojunction bipolar transistors (HBT) [10]. For devices * Corresponding author. Tel.: 1 81-22-223-7287; fax: 1 81-22-2237289. E-mail addresses: [email protected] (J. Nishizawa); [email protected] (T. Kurabayashi)
operating at the tera-hertz frequency, the transit time should be shorter than 10 213 s. The Monte Carlo simulation of highenergy electron transport in GaAs, indicated that it might be Ê achieved in a transistor with a channel shorter than 200 A [11]. Ê are The GaAs ISITs with channels as short as 100 A achieved. An electron tunneling through the potential barrier between the source and the drain of the transistor is a dominant transport mechanism. The ISITs were fabricated with the molecular layer epitaxy (MLE) [12], developed by Nishizawa who was inspired with the Suntola's idea of atomic layer epitaxy (ALE) [13,14] for II±VI compound semiconductor polycrystals. The selective MLE regrowth was applied to de®ne the channel length. Fabrication processes for ISIT require low temperature and damage free crystallization with atomic-accuracy, what is characteristic for MLE. However, the redistribution of the doped Se of n 11 (heavily doped n-type) GaAs layer was clearly detected by secondary ion mass spectroscopy (SIMS), when the process temperature was higher than 4808C [15]. To reduce the diffused impurity in the device fabrication process, growth condition has been examined, that is, the control of stoichiometry has been applied during the MLE process [16]. As a practical matter during the fabrication process of ISIT, a controlling of carrier concentration of the doped layer and the thickness grown on the side wall are signi®cantly important for the dif®culties of monitoring. The doping characteristics shows quite different manner in each oriented GaAs surface on (001), (111)A and (111)B. Such orientation dependence of doping is quite important
0040-6090/00/$ - see front matter q 2000 Elsevier Science S.A. All rights reserved. PII: S 0040-609 0(00)00678-7
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for sidewall epitaxy in the ISIT fabrication process. The gate thickness of ISIT was controlled by monitoring the growth thickness on (001). However, a control of lateral growth has never been investigated. The size used in the quantum devices, such as ISIT, was several tens of nm order at the most. We have investigated the directional dependence of lateral growth rate on the low steps quantitatively by using the table method [17]. Additionally, as new materials for application, MLE of InP [18], and Si [19] with SiO2 [20] deposition have been also developed to realize the tera-hertz operating devices. At process temperature suf®ciently lower than in the conventional growth method, device quality epitaxial layers were achieved by MLE. For the device applications of this growth technique the required basic research on MLE of each of the mentioned materials has been performed in the ®eld of surface science and material science. 2. ISIT structure and fabrication GaAs ISITs were fabricated with MLE [21,22]. The precision of MLE suits well for a fabrication process of Ê devices, as there is only 20 crystal cells between the 100 A source and the drain. In addition, the GaAs device quality crystal is grown at temperatures not exceeding 5008C. The growth can be performed selectively on GaAs, without deposition on masked SiN layers. Epitaxial interface stoichiometry is well controlled, so that the selective epitaxial regrowth can be used as an advanced self-alignment method for fabrication of devices with channel lengths many times shorter than possible to achieve with de®nition by lithography. Vertical GaAs SITs with epitaxially regrown channel/gate structures as shown in Fig. 1 are suitable for electron transport investigation with electroluminescence experiments. The thin p 11 (9 £ 1019 cm 23) layer inserted between n 11 (5 £ 1019 cm 23) source and drain layers induces a potential barrier. The barrier height is lower than the bandgap of GaAs, so that the p 11 layer is depleted from holes. At a sidewall of the ex-situ etched groove, the homojunction GaAs channel/gate structure is selectively regrown with MLE. The ®ve crystal monolayer thick n 11 layer at the regrowth interface, induces a minimum in the potential barrier, at the interface. Although the designed metallurgical distance between the n 11 source Ê , the source-drain depleand drain layers is as short as 75 A tion layer penetrates the n 11 layers. Its thickness, measured Ê and this with the capacitance-voltage method is 160 A should be considered to be the channel length. Normallyoff and normally-on devices can be fabricated in the same process on (001) GaAs, depending on crystal orientation of the channel/gate side-wall±Fig. 2. For reducing the parasitic capacitance of transistors, double selective MLE regrowth was applied to fabricate an ISIT with source and drain arranged in a plane, on semi-insulating GaAs, so called horizontal ISIT as shown
Ê GaAs ISIT (b). Fig. 1. Structure (a) and operation principle of 160 A
in Fig. 3. The two epitaxial interfaces meet in the channel of the device. The transconductance was 90 mS/mm. Minimization of the source/drain capacitance was veri®ed by measurement of the C±V dependence in such the structure. Fitting the C to a model of double, side-wall and co-planar Ê. capacitance gave source/drain distances of 90±120 A 3. Electron transport in ISIT The weak temperature dependence of the I-V characteristics±Fig. 3±indicates, that the tunneling electron current component is larger at room temperature, than the thermioÊ scale SIT [22]. nic emission component in the 100 A The vertical SITs with the source-drain distance of 1000 Ê were also fabricated [21]. The in¯uence of temperature on A the characteristics is strong, as expected for the thermionic injection. At room and higher temperatures, the temperature dependence of the current ®ts well to the thermionic injection model [23]±Fig. 4. Taking into consideration applied drain-source voltages exceeding the G L and G X minima separation, the experimentally obtained ratio of ballistic electrons, gF 7:4%, can be considered to be high. It can Ê SITs, tunnelbe seen in Fig. 4 also, that even for the 1000 A ing becomes a dominating transport mechanism for T , 200 K. To have a deeper insight into the electron transport in the Ê SIT, the EL spectra were measured for the vertical 160 A device as shown in Fig. 5a. The observed spectra differ
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Ê vertical ISITs. Normally-off transistor with sidewall channel/gate in (011) plane and normally-on transistor with the Fig. 2. Output characteristics of 100 A plane. Transistors made in the same process. Solid-room temperature, dashed-liquid nitrogen. sidewall in 011
much from the spectra known for the other III±V ®eld effect transistors. The maximum applied VDS # 1:8 V was too small to explain the EL as an effect of holes directly generated by impact ionization and recombining with electrons [24]. An explanation is possible with the Zener tunneling of electrons from the top of the valence band at the barrier maximum to the conduction band of the drain, as presented in Fig. 5b [25]. They can recombine radiatively with the source electrons, like at Esaki diodes. It can be expected that the tunneling of electrons from the source to the drain is direct. For the VDS value of about 1 V and the barrier height about 0.5 eV, the energy gained by the electron exceeds signi®cantly the G L and G X minima separation energies.
The experiments on ionization rate and Monte Carlo (MC) simulation [11], indicate the mean free path as short as 20± Ê . Scattering rate exceeds 2 £ 1014 s 21 for that high 30 A energies. However, these values hold for electrons in the upper valleys of the conduction band. For an electron starting from the G minimum, the average time of 3 £ 10214 s Ê were estimated before the ®rst and the distance of 200 A scattering event. In our devices, planar and vertical, the drift Ê . Thus, the drift time for region length does not exceed 100 A a central valley, ballistic electron should not exceed 1 £ 10214 s. The probability of the ballistic drift should then be close to unity. There is much controversy about the tunneling time [26]. If it is shorter than 10214 s, then the sum of the tunneling time and the drift time should be
Fig. 3. Fabrication and structure of horizontal MIS ISIT.
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200 l/s, and the background pressure was about 1 £ 1029 Torr. The arsenic source was pure AsH3 (100%), and the gallium source was pure TMG or TEG (triethylgallium: Ga(C2H5)3) without carrier gas. TMG (or TEG) and AsH3 were introduced alternately after being evacuated, respectively. In the case of TMG-AsH3 MLE, GaAs ®lms are grown monolayer by monolayer [27,28]. 4.1. Temperature dependence
Ê , vertical Fig. 4. Temperature dependence of saturation current Is, of 1000 A n 1±i±p 1±i±n 1 source/drain sandwich.
shorter than 2 £ 10214 s. This value is suitable for operation of the SIT at tera-hertz frequencies. 4. Molecular layer epitaxy of GaAs The growth chamber was evacuated by a turbo-molecular pump and rotary pump. The net pumping speed was about
Ê, Fig. 5. (a) Room temperature electroluminescence spectra from 160 A vertical GaAs ISIT. Intensity corrected for detector characteristics. (b) Proposed mechanism of observed electroluminescence.
Fig. 6 shows the surface roughness of the ®lm grown by MLE, and the growth rate per cycle as a function of the growth temperature in TMG-AsH3. The surface roughness was measured by atomic force microscope (AFM). The growth sequence was 100''-4''-16''-4''; a 100 s AsH3 injection, a 4 s evacuation of AsH3, a 16 s TMG injection, and a 4 s TMG evacuation. The injected TMG pressure was constant at 5 £ 1025 Torr, and AsH3 pressure was 1 £ 1023 Torr. In the case of the temperature lower than 4458C, the growth rate per cycle was less than the value of a monolayer, i.e. 0.28 nm/cycle. The self-limiting monolayer growth occurred at the temperature range from 445 to 5348C (monolayer plateau). When the growth temperature was over 5348C, the growth rate per cycle was over monolayer. The surface roughness as a function of the growth temperature was estimated by the average of roughness, Ra. As a result, the dependence of the surface roughness on the grown temperature was not the same manner with the growth rate. When the growth temperature was lower than 4708C, the surface roughness was less than 0.2 nm, which was under monolayer order. However, in the case of the temperature range from 470 to 5408C, the roughness was about 0.2±0.4 nm, and about 4±5 nm over 5408C. The surface roughness changes in the temperature range of the monolayer plateau, i.e. over 4708C, the surface roughness tended to increase followed by saturation. In the temperature range over the monolayer growth region, the surface roughness increased drastically. Fig. 7 shows the AFM images of the surface morphology grown by 150 cycles of MLE at various growth temperatures. When the growth temperature was over 4708C, the formation of the nucleated
Fig. 6. Growth thickness per R cycle RL and the surface roughness estimated by the relation of Ra 1=LM M 0 0 jf x; yjdxdy as a function of the growth temperature.
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Fig. 7. The AFM images of the surface morphology grown by 150 cycles of MLE at various growth temperatures: PAsH3 1:3 £ 1021 Pa and PTMG 6:7 £ 1023 Pa, and the gas injection mode is 100''-2''-16''-4''.
was observed. The islands grown along the direction 110 was represented length of the island on the direction 110 . When the growth temperature region was less than by L110
4708C, as shown in (a) and (b), the formation of such islands did not occur and the smooth surface was observed in the order of monolayer accuracy. 4.2. AsH3 supply
Fig. 8. Growth rate per cycle as a function of AsH3 dosage in GaAs MLE by TMG-AsH3.
Fig. 8 shows the growth rate per cycle at 5138C vs. AsH3 dosage, which means the product of the pressure and the duration of AsH3 in each cycle. In Fig. 8, there were three different characteristics of the growth rate vs. AsH3 dosage. The growth rate per cycle in molecular layer epitaxy by using TMG and AsH3 was strongly in¯uenced by the surface stoichiometry of arsenic on the growing surface. The dominant parameter was the product of the AsH3 pressure and its duration. There are two stable state of arsenic at near 70% of arsenic coverage and 100% arsenic coverage, respectively. One is near 70% coverage which is found at a lower AsH3 dosage and the other is almost 100% coverage at the excess AsH3 dosage. Chadi predicted two different structures of (2 £ 4) As-stabilized surface [29]. One is 2 £ 4g with an arsenic coverage of 100% (monolayer), and the other is 2 £
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70% by increasing the duration of AsH3 evacuation. The arsenic re-evaporate from the arsenic monolayer covered surface. The dependence of growth rate per cycle on the TMG evacuation duration is shown in Fig. 10 as a function of growth temperature. In the case of the temperature at 5138C, the growth rate per cycle was always the value of a monolayer. On the other hand, the growth rate per cycle decreased with increasing evacuation duration of TMG and probably saturated over 40 s at the temperatures of 475 and 4458C. The adsorbate formed by TMG supply might not be Ga but Ga compounds which would be volatile and reevaporate during the TMG evacuation in the case of 475 and 4458C. 4.5. Surface reaction mechanism in MLE Fig. 9. Growth rate per cycle as a function of TMG pressure in GaAs MLE by TMG-AsH3.
4b with an As coverage of 75% (3/4 monolayer). The Ê state (70% covercoverage of 75% may ®t our result of 2 A age of arsenic). 4.3. TMG supply Fig. 9 shows the growth rate and the incorporation rate of Ga vs. TMG pressure. The growth mode was 100''-4''-16''4'', and the pressure of TMG was changed. The incorporation rate means the probability of Ga incorporated into the lattice of the GaAs from a molecule of TMG in a cycle. When the TMG pressure was from 1:5 £ 1026 to 5:0 £ 1026 Torr, the growth rate per cycle exceeded monolayer height, and the surface was rough (enhanced growth). Whereas the TMG pressure was over 1 £ 1025 Torr, monolayer growth occurred and mirror-like surface was obtained. The incorporation rate of Ga from TMG was nearly constant at the TMG pressure under 2 £ 1026 Torr, and decreased gradually with increasing TMG pressure in the range over the value. Thus, the Ga or Ga compound on the surface may not interact with TMG at pressures under 2 £ 1026 Torr, while the interaction rate may increases gradually with increasing TMG pressure.
The reaction products from the surface reaction during MLE were measured by in-situ mass spectroscopy. It appears that at least two reactions occur during TMG injection. One is the initial state reaction corresponding to the rapid increase of amu15 CH31 and the rapid decrease of amu99 Ga(CH3)21. The other is the steady state reaction which corresponds to the formation of amu84 GaCH31 as the dominant species. At 420±5108C the monolayer of GaCH3 would be formed by the introduction of TMG temporarily, from which adsorbed Ga and desorbed CH3 with a time constant of 15±36 s are formed. The time constant of formation of the Ga adsorbed layer is longer if the substrate temperature is lower. The further decomposition of TMG occurs on this Ga adsorbed layer. The products of this reaction might be such volatile molecules as GaCH3 or Ga(CH3)2. The reactions of TMG on GaAs (100) are as follows: ÿ 1 Ga CH3 3 ! GaCH3 ad 1 2CH3 initial state GaCH3 ad ! Ga ad 1 CH3 transient state
2
The reaction between AsH3 and the adsorbed species
4.4. Evacuation of AsH3 and TMG The dependence of the growth rate per cycle on the evacuation duration of AsH3 and TMG was investigated as shown in Fig. 10. On the monolayer growth condition, AsH3 was introduced for 100 s at the pressure of 1 £ 1023 Torr and TMG for 16 s at 5 £ 1025 Torr. Almost complete monolayer growth occurred when the evacuation duration of AsH3 was shorter than 4 s, but the growth rate per cycle decreased gradually with increasing the evacuation duration Ê which coincides with the of AsH3 and saturated near 2 A 70% coverage saturation of arsenic, as discussed. It is suggested that the arsenic coverage changes from 100 to
Fig. 10. The dependence of growth rate per cycle on the evacuation duration of AsH3 and of TMG in GaAs MLE by TMG-AsH3.
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Fig. 11. Schematic drawing of the surface reaction mechanism of TMG and AsH3 in GaAs MLE.
associated with the TMG injection was also measured by QMS. As a result, an amu2 H21 signal along with a weaker amu15 CH31 signal was observed. This means that CH4 and H2 are the byproducts of the reaction with a long time constant (.30 s). We concluded that the main adsorption species formed by the TMG injection would be GaCH3. From the QMS data, the possible reactions with AsH3 are: GaCH3 adsorb 1 AsH3 ! GaAs 1 CH4 1H2
3
Ga adsorb 1 AsH3 ! GaAs 1 3=2H2
4
The reaction in MLE was schematically shown in Fig. 11.
5. Doping technology in GaAs molecular layer epitaxy Fig. 12 shows the schematic diagram of MLE system and the gas injection sequence for doped layer growth. The arsenic source was pure AsH3 (100%), and the gallium source was pure Ga(C2H5)3 (triethylgallium: TEG) without carrier gas. The effect of the doping period was studied by experiments in which the dopant source supplied during AsH3 evacuation period (AA: after As), the TEG injection period (IG: in Ga), the TEG evacuation period (AG: after Ga), or AsH3 injection period (IA: in As) [30]. The growth temperatures were 350±4008C mainly. The electron concentration of the Se doped n 11 layer was controlled in the range of 4 £ 1018 to 3 £ 1019 cm 23 by
Fig. 12. Schematic diagram of the MLE system and the gas injection sequence for doped layer growth.
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changing the injection pressure and the duration of Se(C2H5)2 (diethylselenium: DESe) at the growth temperature of 4008C. In the fabrication process of ISIT, the ®rst epitaxial process is the source-drain fabrication, and the second is the regrowth for the external gate fabrication. Prior to the second epitaxial growth, the surface treatment by heating was necessary to remove the surface contaminations. However, the electrical characteristics of the source-drain was changed by the surface treatment. The dopants pro®les measured by SIMS showed that the barrier characteristics vanished mainly due to the anomalous diffusion of Se from a heavily Se-doped source region to the p 11 barrier layer with a few monolayer thickness. The dopants pro®les of the source-drain structure of the ISIT were measured by using SIMS to measure the doped or diffused dopants pro®les. SIMS measurements were carried out with low energy 2.5 keV Cs 1 beams for each dopants detection to avoid the atomic mixing at higher energy after
annealing at various temperatures [15]. Fig. 13a shows the Ê -thick source-drain structure after dopants pro®le of 1836 A Ê -thick carbon doped heat treatment. The sample has a 36 A 11 p layer to induce a potential barrier. The as-grown sample (i.e. not heat treated) showed an abrupt pro®le of Se. The heat treatment was performed at 620, 525, and 4808C under the H2 ambient at atmospheric pressure for 30 min. No Se diffusion was observed into Si doped substrate, whereas in Ê layer, a signi®cant amount of Se diffuthe undoped 1500 A sion from the source region was observed in each heat treated samples. The redistributed Se pro®les by the heat treatment seem to be the same shape with the distribution of carbon in the p 11 layer. In other words, Se from the source region diffused and gathered at the p 11 layer as `spike like'. To identify this, the structure without the p 11 layer was examined as the same procedure. In this case the `spike like' Se diffusion was not observed, but replaced by a diffused Se pro®le as shown in Fig. 13b. Additionally, the structure without the top Se doped layer (2±3 £ 1019 cm 23)
Ê -thick source-drain structure of ISIT measured by SIMS after heat treatment at each temperature for 30 min. (b) Dopants Fig. 13. (a) Dopants pro®le of 1836 A pro®le of n 11±n 1±i±n 1 structure (source-drain structure of ISIT without p 11 layer) measured by SIMS after heat treatment at each temperature for 30 min.
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showed a remarkable small amount the diffusion of Se. From these results, the Se diffusion source would be a heavily Se-doped layer of 2±3 £ 1019 cm 23 which would contain a larger amount of the interstitial Se atom in the lattice. The carbon doped layer would act as a gettering layer of diffused interstitial Se. As mentioned, for the fabrications of ISIT, the interdiffusion of Se as a donor impurity in the source-drain structure was remarkable when the process temperature was higher than 4508C. To examine the growth condition on impurity diffusion, n 11 (Se doped)-i (undoped) structure was fabricated by doping MLE in various condition of AsH3 supply. The pro®le of Se was measured after heat-treatment as shown in Fig. 14a. The higher amount of AsH3 supply during the growth of undoped layer reduces diffusion of Se from the n 11 layer as shown in Fig. 14b. The excess of AsH3 supply may reduce the arsenic vacancy of the i layer, and therefore the arsenic site of Se, even after the heat treatment [16]. On the other hand, a lower amount of AsH3 supply during the growth of n 11 layer reduces the
Ê )-i Fig. 14. (a) Typical depth pro®le of Se in n 11 (Se doped 500±600 A Ê ) structures as-grown and after the heat treatment at (undoped 500±700 A 480, 525 and 6208C for 30 min in a H2 atmosphere. (b) The diffused Se concentrations in the i layer vs. annealed temperature were examined as parameters of AsH3 injection pressure in the i layer growth. In the ®gure, 4008C annealing temperature means the value of the as-grown one at the growth temperature of 4008C.
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diffusion of Se from the n 11 layer itself, which seems to be understood by the idea of the increasing the arsenic vacancy and stabilizing the interstitial Se to become substitutional. As related processes with doping MLE, chemical vapor deposition of W on Se doped or Te doped n 11 GaAs for a low resistivity contact has been successfully achieved by using W(CO)6 precursor at temperatures lower than 4008C in MLE chamber. Contact resistance was 3 £ 1027 V cm 2 to Te doped n-type GaAs at Te 3±4 £ 1020 cm 23, and below 2 £ 1028 V cm 2 to C doped p-type GaAs at the electrically active acceptor concentration of 4 £ 1019 cm 23 [31]. This technology is effective for low resistivity ohmic contact for tera-hertz operating devices. In ISIT fabrication, at a sidewall of the chemical etched groove, the homo-junction GaAs channel/gate structure is selectively regrown with MLE. The crystallographic orientation on the sidewall may be gallium stable surface like (111)Ga, or (311)Ga. The ®ve mono-molecular layer thick n 11 layer at the regrowth interface, induces a minimum in the potential barrier, at the interface. Normally-off and normally-on devices can be fabricated in the same process on GaAs, depending on crystal orientation of the channel/ gate side-wall. In order to control the doping MLE at a sidewall, the doping characteristics on each crystallographic orientation surfaces of GaAs substrate have been studied. The AsH3 supply in a cycle was 50 s at the partial pressure of 1 £ 1023 Torr, and the TEG was 4 s at 7:2 £ 1026 Torr. As a dopant gas, Te(C2H5)2 (diethyltellurium: DETe) was introduced for 2 s in a cycle at the partial pressure of 1 £ 1027 Torr. Te doped crystallographic orientation dependence on the carrier concentration has been studied. As the substrate, (001), (111)A, and (111)B-oriented undoped semi-insulating substrate were used. The doping characteristics shows quite different manner in each oriented GaAs surface on each substrates as shown in Fig. 15. On Ga-stable (111)A surface, Te was doped at the lowest temperature in each orientation of the substrate. However, on arsenic-stable (111)B surface, Te doping was performed at the highest temperature. Doped Te should be incorporated in arsenic site, however, the arsenic stability on the growing surface should be different in each orientation of the substrate. For example on (111)A, Ga is stable but not arsenic, therefore, Te might be incorporated at a lower temperature, namely, doped Te is easy to desorb at a higher growth temperature. Additionally, the directional lateral growth on the nm step of GaAs during molecular layer epitaxy was investigated quantitatively by using the table method. MLE growth was performed on the deformation and measured by using AFM and the lateral growth was estimated. The fastest direction and is 5±10 lateral growth rate is in the 110 times greater than the vertical growth rate on GaAs (001) plane. The slowest lateral growth rate is in the [110] directions. With increasing the growth temperature, the lateral growth rate was increased in each direction. The deformation of the table pattern in each direction was proportional to
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Fig. 15. Te doped crystallographic orientation dependence on the carrier concentration. As the substrate, (001), (111)A, and (111)B-oriented undoped semi-insulating substrate were used. Fig. 16. Si and SiO2 MLE system.
sin u (u is the deviation angle from the [110] direction on the GaAs (001) plane). The deformation of lateral growth directions tends to increase followed by along the 110 saturation with increasing the growth cycle. These results show that the lateral growth rate is proportional to the density of arsenic dangling bonds on the surface. 6. Molecular layer epitaxy of other materials MLE growth and digital etching of (001) InP in the MLE chamber has also been achieved [18]. The intermittent injection of uncracked tert-butylphosphine (TBP), the injection and the evacuation of which are cyclically repeated at 3908C, has been used for the selective-area etching of an InP(001) surface in addition to the MLE growth of InP. The etch rate was almost independent of the TBP injection time, TBP injection pressure, and the evacuation time in a selflimiting fashion. These etching techniques promise to improve the device characteristics by removing the damaged and contaminated layers as atomic dimension accuracy before MLE. Si MLE has been performed by using SiH2Cl2±H2 system introducing SiH2Cl2 and H2 alternately on the Si substrate at the temperature range of 800±9008C [32]. However, the growth temperature over 8008C is too high to fabricate nm-scale devices such as ISIT structure. To reduce the growth temperature, Si2H6 was used as a source gas. The growth system is schematically shown in Fig. 16. The MLE growth was performed by using temperature synchronized method, namely, the source gas injection was synchronized with the substrate temperature. In a cycle of gas injection, Si2H6 was introduced at the pressure of 1:3 £ 1022 Pa for 10±100 s at the temperature of 4008C, and the substrate was heated up to 5508C and cooled to 4008C within 30 s. Even enough amount of Si2H6 was introduced at 4008C, no growth occurred, therefore, the heating followed by the Si2H6 supply enables the surface reaction to proceed [19].
As shown in Fig. 17, mass spectroscopic measurement proved that the adsorption of SiZH compound is dominant at 4008C after Si2H6 supply, and the hydrogen from the SiZH will release by the surface reaction of SiZHx adsorbate when the substrate was heated up to 5508C. By using the temperature modulation method [33], Si MLE was ®rst accomplished at low temperature with self-limiting process as parameters of duration and/or pressure of Si2H6 supply as shown in Fig. 18.
Fig. 17. Time dependence of (a) controlled substrate temperature, and (b) in-situ mass spectroscopic signal of amu2 H21.
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been studied. The GaAs ISITs with channels as short as 100 Ê are achieved by using MLE and related processes. The I-V A characteristics and the electroluminescence spectra (below Ê ISIT structure band gap, from 0.6±1.4 eV) from the 160 A indicate tunneling through the potential barrier between the source and the drain as room temperature electron transport mechanism. From these results, the electron transit time was estimated as 2 £ 10214 s. The superior microwave performance will be presented soon in another paper. These studies are continued at the Sendai Research Center, TAO, Japan. Recently, not only GaAs but also InP, Si with SiO2 CVD has been developed to achieve ISITs in other materials. References
Fig. 18. Temperature modulation Si MLE. Si2H6 injection duration dependence (a), and Si2H6 pressure dependence.
As related process with Si MLE, chemical vapor deposition of SiO2 in high vacuum has also been studied by introducing Si2H6 and active oxygen (radical O2) from helicon plasma source in the MLE system [20]. SiO2 CVD was intended to fabricate MOS-gate structure in Si MLE chamber. At the partial pressure of 1 £ 1022 Pa for Si2H6 and radical O2, the deposition rate was nearly constant at 0.2 nm/min at the temperature range from 300 to 7508C, while the oxidation speed was 0.04 nm/min by the same amount of radical O2 introduction. At the next stage, MOS gate structure by the CVD SiO2 in Si MLE chamber, and the doping method in Si MLE will be applied to fabricate the MOS gate ISIT structure. 7. Concluding remarks MLE of GaAs has been developed to realize the tera-hertz operating devices with a basic research in the ®eld of surface science and material science. Doping technology and the related process to control the inter-diffusion of dopant, in-situ metal CVD for low resistivity contact have
[1] Y. Watanabe, J. Nishizawa, Japanese Patent No. 205068 (Application Date: Dec. 1950). [2] J. Nishizawa, T. Terasaki, J. Shibata, Electron Devices ED-22 (1975) 185. [3] J. Nishizawa, Y. Watanabe, Sci. Rep. Res. Inst. Tohoku Univ. 10 (1958) 91. [4] T. Okabe, S. Takamiya, K. Okamoto, J. Nishizawa, IEEE Dig. IEDM (1968) 1. [5] T. Okabe, S. Takamiya, K. Okamoto, J. Nishizawa, RIEC Technical Rep., TR-31, Tohoku University, 1968, pp. 1±10. [6] J. Nishizawa, Proc. 1979 Int. Conf. Solid State Devices, 1979. [7] M. Shur, L.F. Eastman, IEEE Trans. Electron. Devices ED-26 (1979) 1677. [8] J.R. Hayes, A.F.J. Levi, W. Wiegmann, Electron. Lett. 20 (1984) 851. [9] N. Yokoyama, K. Imamura, T. Ohshima, et al., Digest IEDM (1984) 532. [10] T. Ishibashi, Y. Yamauchi, IEEE Trans. Electron. Devices ED-35 (1988) 401. [11] H. Shichijo, K. Hess, Phys. Rev. B 23 (1981) 4197. [12] J. Nishizawa, H. Abe, T. Kurabayashi, J. Electrochem. Soc. 132 (1985) 1197. [13] T. Suntola, U.S. Patent 4058430, 1977. [14] M. Ahonen, M. Pessa, T. Suntola, Thin Solid Films 65 (1980) 301. [15] J. Nishizawa, T. Kurabayashi, Adv. Mater. Opt. Electron. 7 (1997) 183. [16] J. Nishizawa, T. Kurabayashi, Jpn. J. Appl. Phys. 38 (1999) 6193. [17] J. Nishizawa, M. Shimbo, J. Cryst. Growth 24/25 (1974) 215. [18] N. Otsuka, J. Nishizawa, H. Kikuchi, Y. Oyama, Ext. Abstr. 25th Int. Symp. Compound Semiconductors, The IEICE/Electronics Society, Nara, 1998, TuP-2. [19] J. Nishizawa, A. Murai, T. Ohizumi, T. Kurabayashi, K. Ohtsuka, T. Yoshida, Int. Conf. On Chemical Beam Epitaxy and Related Growth Techniques (ICCBE-7), July 27±30, 1999. [20] K. Ohtsuka, T. Yoshida, T. Ohizumi, A. Murai, T. Kurabayashi, J. Nishizawa, Int. Conf. On Chemical Beam Epitaxy and Related Growth Techniques (ICCBE-7), July 27±30, 1999. [21] P. Plotka, T. Kurabayashi, Y. Oyama, J. Nishizawa, Appl. Surf. Sci. 82/83 (1994) 91. [22] J. Nishizawa, P. Plotka, Proc. 5th. Int. Symp. Recent Advances in Microwave Technol. (1995) 54. [23] Y.X. Liu, P. Plotka, K. Suto, Y. Oyama, J. Nishizawa, IEEE Trans. Electron Devices ED-44 (1997) 195. [24] H.P. Zappe, D.J. As, Appl. Phys. Lett. 57 (1990) 2919. [25] J. Nishizawa, P. Plotka, T. Kurabayashi, IEE Proceedings-Circuits, Devices and Systems 146 (1999) 27. [26] D.K. Ferry, in: F. Cappaso (Ed.), Physics of Quantum Electron Devices, Springer, Berlin, 1990, p. 89.
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[27] J. Nishizawa, T. Kurabayashi, J. Vacuum, Sci. Technol. B 13 (1995) 1024±1029. [28] J. Nishizawa, T. Kurabayashi, Thin Solid Films 306 (1997) 179. [29] D.J. Chadi, J. Vac. Sci. Technol. A5 (1987) 834. [30] J. Nishizawa, H. Abe, T. Kurabayashi, J. Electrochem. Soc. 136 (1989) 478.
[31] Y. Oyama, P. Plotka, F. Matsumoto, T. Kurabayashi, T. Hamano, H. Kikuchi, J. Nishizawa, J. Electrochem. Soc. 146 (1999) 131. [32] J. Nishizawa, K. Aoki, S. Suzuki, K. Kikuchi, J. Electrochem. Soc. 137 (1990) 1898. [33] T. Kurabayashi, J. Nishizawa, Appl Surf. Sci. 82/83 (1994) 97.
Molecular layer epitaxy Jun-ichi Nishizawa a,b,*, Toru Kurabayashi a,b a
Telecommunications Advancement Organization, Sendai Research Center, Koeji 19, Nagamachi-Aza Aoba-ku, Sendai 980-0868, Japan b Semiconductor Research Institute of Semiconductor Research Foundation, Kawauchi, Aoba-ku, Sendai 980-0862, Japan
Abstract Molecular layer epitaxy (MLE) of GaAs related compounds and Si with SiO2 deposition has been developed to realize the tera-hertz operating devices. At suf®ciently low process temperature, lower than in the conventional growth method, device quality epitaxial layers Ê scale static induction transistors are fabricated with MLE. These transistors operated in a mixed were achieved by MLE. In GaAs, 100 A ballistic-tunneling mode or in the pure tunneling mode. Basic research on MLE in the ®eld of surface science and material science is performed, from the point of view of device application of this technology. q 2000 Elsevier Science S.A. All rights reserved. Keywords: Molecular layer epitaxy of GaAs, InP and Si; Static induction transistor technology; GaAs tera-hertz devices grown by molecular layer epitaxy
1. Introduction Optical communication network systems with remarkable larger information capacity as Tera-bit/s, 1000 times larger than conventional Giga-bit/s transmission are urgently required. In such demand, high-speed devices operating in tera-hertz frequency should be developed. Static induction transistors (SIT) [1,2] or tunnel mode transit time diodes (TUNNETT) [3±5] are suitable as tera-herz devices. SIT is a kind of the ®eld effect transistor with a very short channel, or the bipolar transistor with an ultimately thin base layer. Therefore, SIT operates with the highest speed among them. In the case when the channel in SIT is made shorter than the mean free path of electrons, then injected electrons travel from source to the intrinsic gate without collision into lattice atoms. Nishizawa estiÊ mated the cut-off frequency of 718 GHz for a 1000 A GaAs SIT [6]. This transistor was called `Ideal SIT (ISIT)'. Later, Shur and Eastman estimated a similar cutoff frequency, and called the scattering free transport as `ballistic' [7]. The quasi ballistic transport at the cryogenic temperature was veri®ed in III-V compound semiconductor devices, like planar doped barrier transistors [8] and tunneling hot electron transfer ampli®ers (THETA) [9]. Dependence of a cut-off frequency on a collector-emitter voltage indicates a signi®cant overshoot of electron velocity in heterojunction bipolar transistors (HBT) [10]. For devices * Corresponding author. Tel.: 1 81-22-223-7287; fax: 1 81-22-2237289. E-mail addresses: [email protected] (J. Nishizawa); [email protected] (T. Kurabayashi)
operating at the tera-hertz frequency, the transit time should be shorter than 10 213 s. The Monte Carlo simulation of highenergy electron transport in GaAs, indicated that it might be Ê achieved in a transistor with a channel shorter than 200 A [11]. Ê are The GaAs ISITs with channels as short as 100 A achieved. An electron tunneling through the potential barrier between the source and the drain of the transistor is a dominant transport mechanism. The ISITs were fabricated with the molecular layer epitaxy (MLE) [12], developed by Nishizawa who was inspired with the Suntola's idea of atomic layer epitaxy (ALE) [13,14] for II±VI compound semiconductor polycrystals. The selective MLE regrowth was applied to de®ne the channel length. Fabrication processes for ISIT require low temperature and damage free crystallization with atomic-accuracy, what is characteristic for MLE. However, the redistribution of the doped Se of n 11 (heavily doped n-type) GaAs layer was clearly detected by secondary ion mass spectroscopy (SIMS), when the process temperature was higher than 4808C [15]. To reduce the diffused impurity in the device fabrication process, growth condition has been examined, that is, the control of stoichiometry has been applied during the MLE process [16]. As a practical matter during the fabrication process of ISIT, a controlling of carrier concentration of the doped layer and the thickness grown on the side wall are signi®cantly important for the dif®culties of monitoring. The doping characteristics shows quite different manner in each oriented GaAs surface on (001), (111)A and (111)B. Such orientation dependence of doping is quite important
0040-6090/00/$ - see front matter q 2000 Elsevier Science S.A. All rights reserved. PII: S 0040-609 0(00)00678-7
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for sidewall epitaxy in the ISIT fabrication process. The gate thickness of ISIT was controlled by monitoring the growth thickness on (001). However, a control of lateral growth has never been investigated. The size used in the quantum devices, such as ISIT, was several tens of nm order at the most. We have investigated the directional dependence of lateral growth rate on the low steps quantitatively by using the table method [17]. Additionally, as new materials for application, MLE of InP [18], and Si [19] with SiO2 [20] deposition have been also developed to realize the tera-hertz operating devices. At process temperature suf®ciently lower than in the conventional growth method, device quality epitaxial layers were achieved by MLE. For the device applications of this growth technique the required basic research on MLE of each of the mentioned materials has been performed in the ®eld of surface science and material science. 2. ISIT structure and fabrication GaAs ISITs were fabricated with MLE [21,22]. The precision of MLE suits well for a fabrication process of Ê devices, as there is only 20 crystal cells between the 100 A source and the drain. In addition, the GaAs device quality crystal is grown at temperatures not exceeding 5008C. The growth can be performed selectively on GaAs, without deposition on masked SiN layers. Epitaxial interface stoichiometry is well controlled, so that the selective epitaxial regrowth can be used as an advanced self-alignment method for fabrication of devices with channel lengths many times shorter than possible to achieve with de®nition by lithography. Vertical GaAs SITs with epitaxially regrown channel/gate structures as shown in Fig. 1 are suitable for electron transport investigation with electroluminescence experiments. The thin p 11 (9 £ 1019 cm 23) layer inserted between n 11 (5 £ 1019 cm 23) source and drain layers induces a potential barrier. The barrier height is lower than the bandgap of GaAs, so that the p 11 layer is depleted from holes. At a sidewall of the ex-situ etched groove, the homojunction GaAs channel/gate structure is selectively regrown with MLE. The ®ve crystal monolayer thick n 11 layer at the regrowth interface, induces a minimum in the potential barrier, at the interface. Although the designed metallurgical distance between the n 11 source Ê , the source-drain depleand drain layers is as short as 75 A tion layer penetrates the n 11 layers. Its thickness, measured Ê and this with the capacitance-voltage method is 160 A should be considered to be the channel length. Normallyoff and normally-on devices can be fabricated in the same process on (001) GaAs, depending on crystal orientation of the channel/gate side-wall±Fig. 2. For reducing the parasitic capacitance of transistors, double selective MLE regrowth was applied to fabricate an ISIT with source and drain arranged in a plane, on semi-insulating GaAs, so called horizontal ISIT as shown
Ê GaAs ISIT (b). Fig. 1. Structure (a) and operation principle of 160 A
in Fig. 3. The two epitaxial interfaces meet in the channel of the device. The transconductance was 90 mS/mm. Minimization of the source/drain capacitance was veri®ed by measurement of the C±V dependence in such the structure. Fitting the C to a model of double, side-wall and co-planar Ê. capacitance gave source/drain distances of 90±120 A 3. Electron transport in ISIT The weak temperature dependence of the I-V characteristics±Fig. 3±indicates, that the tunneling electron current component is larger at room temperature, than the thermioÊ scale SIT [22]. nic emission component in the 100 A The vertical SITs with the source-drain distance of 1000 Ê were also fabricated [21]. The in¯uence of temperature on A the characteristics is strong, as expected for the thermionic injection. At room and higher temperatures, the temperature dependence of the current ®ts well to the thermionic injection model [23]±Fig. 4. Taking into consideration applied drain-source voltages exceeding the G L and G X minima separation, the experimentally obtained ratio of ballistic electrons, gF 7:4%, can be considered to be high. It can Ê SITs, tunnelbe seen in Fig. 4 also, that even for the 1000 A ing becomes a dominating transport mechanism for T , 200 K. To have a deeper insight into the electron transport in the Ê SIT, the EL spectra were measured for the vertical 160 A device as shown in Fig. 5a. The observed spectra differ
J. Nishizawa, T. Kurabayashi / Thin Solid Films 367 (2000) 13±24
15
Ê vertical ISITs. Normally-off transistor with sidewall channel/gate in (011) plane and normally-on transistor with the Fig. 2. Output characteristics of 100 A plane. Transistors made in the same process. Solid-room temperature, dashed-liquid nitrogen. sidewall in 011
much from the spectra known for the other III±V ®eld effect transistors. The maximum applied VDS # 1:8 V was too small to explain the EL as an effect of holes directly generated by impact ionization and recombining with electrons [24]. An explanation is possible with the Zener tunneling of electrons from the top of the valence band at the barrier maximum to the conduction band of the drain, as presented in Fig. 5b [25]. They can recombine radiatively with the source electrons, like at Esaki diodes. It can be expected that the tunneling of electrons from the source to the drain is direct. For the VDS value of about 1 V and the barrier height about 0.5 eV, the energy gained by the electron exceeds signi®cantly the G L and G X minima separation energies.
The experiments on ionization rate and Monte Carlo (MC) simulation [11], indicate the mean free path as short as 20± Ê . Scattering rate exceeds 2 £ 1014 s 21 for that high 30 A energies. However, these values hold for electrons in the upper valleys of the conduction band. For an electron starting from the G minimum, the average time of 3 £ 10214 s Ê were estimated before the ®rst and the distance of 200 A scattering event. In our devices, planar and vertical, the drift Ê . Thus, the drift time for region length does not exceed 100 A a central valley, ballistic electron should not exceed 1 £ 10214 s. The probability of the ballistic drift should then be close to unity. There is much controversy about the tunneling time [26]. If it is shorter than 10214 s, then the sum of the tunneling time and the drift time should be
Fig. 3. Fabrication and structure of horizontal MIS ISIT.
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200 l/s, and the background pressure was about 1 £ 1029 Torr. The arsenic source was pure AsH3 (100%), and the gallium source was pure TMG or TEG (triethylgallium: Ga(C2H5)3) without carrier gas. TMG (or TEG) and AsH3 were introduced alternately after being evacuated, respectively. In the case of TMG-AsH3 MLE, GaAs ®lms are grown monolayer by monolayer [27,28]. 4.1. Temperature dependence
Ê , vertical Fig. 4. Temperature dependence of saturation current Is, of 1000 A n 1±i±p 1±i±n 1 source/drain sandwich.
shorter than 2 £ 10214 s. This value is suitable for operation of the SIT at tera-hertz frequencies. 4. Molecular layer epitaxy of GaAs The growth chamber was evacuated by a turbo-molecular pump and rotary pump. The net pumping speed was about
Ê, Fig. 5. (a) Room temperature electroluminescence spectra from 160 A vertical GaAs ISIT. Intensity corrected for detector characteristics. (b) Proposed mechanism of observed electroluminescence.
Fig. 6 shows the surface roughness of the ®lm grown by MLE, and the growth rate per cycle as a function of the growth temperature in TMG-AsH3. The surface roughness was measured by atomic force microscope (AFM). The growth sequence was 100''-4''-16''-4''; a 100 s AsH3 injection, a 4 s evacuation of AsH3, a 16 s TMG injection, and a 4 s TMG evacuation. The injected TMG pressure was constant at 5 £ 1025 Torr, and AsH3 pressure was 1 £ 1023 Torr. In the case of the temperature lower than 4458C, the growth rate per cycle was less than the value of a monolayer, i.e. 0.28 nm/cycle. The self-limiting monolayer growth occurred at the temperature range from 445 to 5348C (monolayer plateau). When the growth temperature was over 5348C, the growth rate per cycle was over monolayer. The surface roughness as a function of the growth temperature was estimated by the average of roughness, Ra. As a result, the dependence of the surface roughness on the grown temperature was not the same manner with the growth rate. When the growth temperature was lower than 4708C, the surface roughness was less than 0.2 nm, which was under monolayer order. However, in the case of the temperature range from 470 to 5408C, the roughness was about 0.2±0.4 nm, and about 4±5 nm over 5408C. The surface roughness changes in the temperature range of the monolayer plateau, i.e. over 4708C, the surface roughness tended to increase followed by saturation. In the temperature range over the monolayer growth region, the surface roughness increased drastically. Fig. 7 shows the AFM images of the surface morphology grown by 150 cycles of MLE at various growth temperatures. When the growth temperature was over 4708C, the formation of the nucleated
Fig. 6. Growth thickness per R cycle RL and the surface roughness estimated by the relation of Ra 1=LM M 0 0 jf x; yjdxdy as a function of the growth temperature.
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17
Fig. 7. The AFM images of the surface morphology grown by 150 cycles of MLE at various growth temperatures: PAsH3 1:3 £ 1021 Pa and PTMG 6:7 £ 1023 Pa, and the gas injection mode is 100''-2''-16''-4''.
was observed. The islands grown along the direction 110 was represented length of the island on the direction 110 . When the growth temperature region was less than by L110
4708C, as shown in (a) and (b), the formation of such islands did not occur and the smooth surface was observed in the order of monolayer accuracy. 4.2. AsH3 supply
Fig. 8. Growth rate per cycle as a function of AsH3 dosage in GaAs MLE by TMG-AsH3.
Fig. 8 shows the growth rate per cycle at 5138C vs. AsH3 dosage, which means the product of the pressure and the duration of AsH3 in each cycle. In Fig. 8, there were three different characteristics of the growth rate vs. AsH3 dosage. The growth rate per cycle in molecular layer epitaxy by using TMG and AsH3 was strongly in¯uenced by the surface stoichiometry of arsenic on the growing surface. The dominant parameter was the product of the AsH3 pressure and its duration. There are two stable state of arsenic at near 70% of arsenic coverage and 100% arsenic coverage, respectively. One is near 70% coverage which is found at a lower AsH3 dosage and the other is almost 100% coverage at the excess AsH3 dosage. Chadi predicted two different structures of (2 £ 4) As-stabilized surface [29]. One is 2 £ 4g with an arsenic coverage of 100% (monolayer), and the other is 2 £
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70% by increasing the duration of AsH3 evacuation. The arsenic re-evaporate from the arsenic monolayer covered surface. The dependence of growth rate per cycle on the TMG evacuation duration is shown in Fig. 10 as a function of growth temperature. In the case of the temperature at 5138C, the growth rate per cycle was always the value of a monolayer. On the other hand, the growth rate per cycle decreased with increasing evacuation duration of TMG and probably saturated over 40 s at the temperatures of 475 and 4458C. The adsorbate formed by TMG supply might not be Ga but Ga compounds which would be volatile and reevaporate during the TMG evacuation in the case of 475 and 4458C. 4.5. Surface reaction mechanism in MLE Fig. 9. Growth rate per cycle as a function of TMG pressure in GaAs MLE by TMG-AsH3.
4b with an As coverage of 75% (3/4 monolayer). The Ê state (70% covercoverage of 75% may ®t our result of 2 A age of arsenic). 4.3. TMG supply Fig. 9 shows the growth rate and the incorporation rate of Ga vs. TMG pressure. The growth mode was 100''-4''-16''4'', and the pressure of TMG was changed. The incorporation rate means the probability of Ga incorporated into the lattice of the GaAs from a molecule of TMG in a cycle. When the TMG pressure was from 1:5 £ 1026 to 5:0 £ 1026 Torr, the growth rate per cycle exceeded monolayer height, and the surface was rough (enhanced growth). Whereas the TMG pressure was over 1 £ 1025 Torr, monolayer growth occurred and mirror-like surface was obtained. The incorporation rate of Ga from TMG was nearly constant at the TMG pressure under 2 £ 1026 Torr, and decreased gradually with increasing TMG pressure in the range over the value. Thus, the Ga or Ga compound on the surface may not interact with TMG at pressures under 2 £ 1026 Torr, while the interaction rate may increases gradually with increasing TMG pressure.
The reaction products from the surface reaction during MLE were measured by in-situ mass spectroscopy. It appears that at least two reactions occur during TMG injection. One is the initial state reaction corresponding to the rapid increase of amu15 CH31 and the rapid decrease of amu99 Ga(CH3)21. The other is the steady state reaction which corresponds to the formation of amu84 GaCH31 as the dominant species. At 420±5108C the monolayer of GaCH3 would be formed by the introduction of TMG temporarily, from which adsorbed Ga and desorbed CH3 with a time constant of 15±36 s are formed. The time constant of formation of the Ga adsorbed layer is longer if the substrate temperature is lower. The further decomposition of TMG occurs on this Ga adsorbed layer. The products of this reaction might be such volatile molecules as GaCH3 or Ga(CH3)2. The reactions of TMG on GaAs (100) are as follows: ÿ 1 Ga CH3 3 ! GaCH3 ad 1 2CH3 initial state GaCH3 ad ! Ga ad 1 CH3 transient state
2
The reaction between AsH3 and the adsorbed species
4.4. Evacuation of AsH3 and TMG The dependence of the growth rate per cycle on the evacuation duration of AsH3 and TMG was investigated as shown in Fig. 10. On the monolayer growth condition, AsH3 was introduced for 100 s at the pressure of 1 £ 1023 Torr and TMG for 16 s at 5 £ 1025 Torr. Almost complete monolayer growth occurred when the evacuation duration of AsH3 was shorter than 4 s, but the growth rate per cycle decreased gradually with increasing the evacuation duration Ê which coincides with the of AsH3 and saturated near 2 A 70% coverage saturation of arsenic, as discussed. It is suggested that the arsenic coverage changes from 100 to
Fig. 10. The dependence of growth rate per cycle on the evacuation duration of AsH3 and of TMG in GaAs MLE by TMG-AsH3.
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Fig. 11. Schematic drawing of the surface reaction mechanism of TMG and AsH3 in GaAs MLE.
associated with the TMG injection was also measured by QMS. As a result, an amu2 H21 signal along with a weaker amu15 CH31 signal was observed. This means that CH4 and H2 are the byproducts of the reaction with a long time constant (.30 s). We concluded that the main adsorption species formed by the TMG injection would be GaCH3. From the QMS data, the possible reactions with AsH3 are: GaCH3 adsorb 1 AsH3 ! GaAs 1 CH4 1H2
3
Ga adsorb 1 AsH3 ! GaAs 1 3=2H2
4
The reaction in MLE was schematically shown in Fig. 11.
5. Doping technology in GaAs molecular layer epitaxy Fig. 12 shows the schematic diagram of MLE system and the gas injection sequence for doped layer growth. The arsenic source was pure AsH3 (100%), and the gallium source was pure Ga(C2H5)3 (triethylgallium: TEG) without carrier gas. The effect of the doping period was studied by experiments in which the dopant source supplied during AsH3 evacuation period (AA: after As), the TEG injection period (IG: in Ga), the TEG evacuation period (AG: after Ga), or AsH3 injection period (IA: in As) [30]. The growth temperatures were 350±4008C mainly. The electron concentration of the Se doped n 11 layer was controlled in the range of 4 £ 1018 to 3 £ 1019 cm 23 by
Fig. 12. Schematic diagram of the MLE system and the gas injection sequence for doped layer growth.
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changing the injection pressure and the duration of Se(C2H5)2 (diethylselenium: DESe) at the growth temperature of 4008C. In the fabrication process of ISIT, the ®rst epitaxial process is the source-drain fabrication, and the second is the regrowth for the external gate fabrication. Prior to the second epitaxial growth, the surface treatment by heating was necessary to remove the surface contaminations. However, the electrical characteristics of the source-drain was changed by the surface treatment. The dopants pro®les measured by SIMS showed that the barrier characteristics vanished mainly due to the anomalous diffusion of Se from a heavily Se-doped source region to the p 11 barrier layer with a few monolayer thickness. The dopants pro®les of the source-drain structure of the ISIT were measured by using SIMS to measure the doped or diffused dopants pro®les. SIMS measurements were carried out with low energy 2.5 keV Cs 1 beams for each dopants detection to avoid the atomic mixing at higher energy after
annealing at various temperatures [15]. Fig. 13a shows the Ê -thick source-drain structure after dopants pro®le of 1836 A Ê -thick carbon doped heat treatment. The sample has a 36 A 11 p layer to induce a potential barrier. The as-grown sample (i.e. not heat treated) showed an abrupt pro®le of Se. The heat treatment was performed at 620, 525, and 4808C under the H2 ambient at atmospheric pressure for 30 min. No Se diffusion was observed into Si doped substrate, whereas in Ê layer, a signi®cant amount of Se diffuthe undoped 1500 A sion from the source region was observed in each heat treated samples. The redistributed Se pro®les by the heat treatment seem to be the same shape with the distribution of carbon in the p 11 layer. In other words, Se from the source region diffused and gathered at the p 11 layer as `spike like'. To identify this, the structure without the p 11 layer was examined as the same procedure. In this case the `spike like' Se diffusion was not observed, but replaced by a diffused Se pro®le as shown in Fig. 13b. Additionally, the structure without the top Se doped layer (2±3 £ 1019 cm 23)
Ê -thick source-drain structure of ISIT measured by SIMS after heat treatment at each temperature for 30 min. (b) Dopants Fig. 13. (a) Dopants pro®le of 1836 A pro®le of n 11±n 1±i±n 1 structure (source-drain structure of ISIT without p 11 layer) measured by SIMS after heat treatment at each temperature for 30 min.
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showed a remarkable small amount the diffusion of Se. From these results, the Se diffusion source would be a heavily Se-doped layer of 2±3 £ 1019 cm 23 which would contain a larger amount of the interstitial Se atom in the lattice. The carbon doped layer would act as a gettering layer of diffused interstitial Se. As mentioned, for the fabrications of ISIT, the interdiffusion of Se as a donor impurity in the source-drain structure was remarkable when the process temperature was higher than 4508C. To examine the growth condition on impurity diffusion, n 11 (Se doped)-i (undoped) structure was fabricated by doping MLE in various condition of AsH3 supply. The pro®le of Se was measured after heat-treatment as shown in Fig. 14a. The higher amount of AsH3 supply during the growth of undoped layer reduces diffusion of Se from the n 11 layer as shown in Fig. 14b. The excess of AsH3 supply may reduce the arsenic vacancy of the i layer, and therefore the arsenic site of Se, even after the heat treatment [16]. On the other hand, a lower amount of AsH3 supply during the growth of n 11 layer reduces the
Ê )-i Fig. 14. (a) Typical depth pro®le of Se in n 11 (Se doped 500±600 A Ê ) structures as-grown and after the heat treatment at (undoped 500±700 A 480, 525 and 6208C for 30 min in a H2 atmosphere. (b) The diffused Se concentrations in the i layer vs. annealed temperature were examined as parameters of AsH3 injection pressure in the i layer growth. In the ®gure, 4008C annealing temperature means the value of the as-grown one at the growth temperature of 4008C.
21
diffusion of Se from the n 11 layer itself, which seems to be understood by the idea of the increasing the arsenic vacancy and stabilizing the interstitial Se to become substitutional. As related processes with doping MLE, chemical vapor deposition of W on Se doped or Te doped n 11 GaAs for a low resistivity contact has been successfully achieved by using W(CO)6 precursor at temperatures lower than 4008C in MLE chamber. Contact resistance was 3 £ 1027 V cm 2 to Te doped n-type GaAs at Te 3±4 £ 1020 cm 23, and below 2 £ 1028 V cm 2 to C doped p-type GaAs at the electrically active acceptor concentration of 4 £ 1019 cm 23 [31]. This technology is effective for low resistivity ohmic contact for tera-hertz operating devices. In ISIT fabrication, at a sidewall of the chemical etched groove, the homo-junction GaAs channel/gate structure is selectively regrown with MLE. The crystallographic orientation on the sidewall may be gallium stable surface like (111)Ga, or (311)Ga. The ®ve mono-molecular layer thick n 11 layer at the regrowth interface, induces a minimum in the potential barrier, at the interface. Normally-off and normally-on devices can be fabricated in the same process on GaAs, depending on crystal orientation of the channel/ gate side-wall. In order to control the doping MLE at a sidewall, the doping characteristics on each crystallographic orientation surfaces of GaAs substrate have been studied. The AsH3 supply in a cycle was 50 s at the partial pressure of 1 £ 1023 Torr, and the TEG was 4 s at 7:2 £ 1026 Torr. As a dopant gas, Te(C2H5)2 (diethyltellurium: DETe) was introduced for 2 s in a cycle at the partial pressure of 1 £ 1027 Torr. Te doped crystallographic orientation dependence on the carrier concentration has been studied. As the substrate, (001), (111)A, and (111)B-oriented undoped semi-insulating substrate were used. The doping characteristics shows quite different manner in each oriented GaAs surface on each substrates as shown in Fig. 15. On Ga-stable (111)A surface, Te was doped at the lowest temperature in each orientation of the substrate. However, on arsenic-stable (111)B surface, Te doping was performed at the highest temperature. Doped Te should be incorporated in arsenic site, however, the arsenic stability on the growing surface should be different in each orientation of the substrate. For example on (111)A, Ga is stable but not arsenic, therefore, Te might be incorporated at a lower temperature, namely, doped Te is easy to desorb at a higher growth temperature. Additionally, the directional lateral growth on the nm step of GaAs during molecular layer epitaxy was investigated quantitatively by using the table method. MLE growth was performed on the deformation and measured by using AFM and the lateral growth was estimated. The fastest direction and is 5±10 lateral growth rate is in the 110 times greater than the vertical growth rate on GaAs (001) plane. The slowest lateral growth rate is in the [110] directions. With increasing the growth temperature, the lateral growth rate was increased in each direction. The deformation of the table pattern in each direction was proportional to
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Fig. 15. Te doped crystallographic orientation dependence on the carrier concentration. As the substrate, (001), (111)A, and (111)B-oriented undoped semi-insulating substrate were used. Fig. 16. Si and SiO2 MLE system.
sin u (u is the deviation angle from the [110] direction on the GaAs (001) plane). The deformation of lateral growth directions tends to increase followed by along the 110 saturation with increasing the growth cycle. These results show that the lateral growth rate is proportional to the density of arsenic dangling bonds on the surface. 6. Molecular layer epitaxy of other materials MLE growth and digital etching of (001) InP in the MLE chamber has also been achieved [18]. The intermittent injection of uncracked tert-butylphosphine (TBP), the injection and the evacuation of which are cyclically repeated at 3908C, has been used for the selective-area etching of an InP(001) surface in addition to the MLE growth of InP. The etch rate was almost independent of the TBP injection time, TBP injection pressure, and the evacuation time in a selflimiting fashion. These etching techniques promise to improve the device characteristics by removing the damaged and contaminated layers as atomic dimension accuracy before MLE. Si MLE has been performed by using SiH2Cl2±H2 system introducing SiH2Cl2 and H2 alternately on the Si substrate at the temperature range of 800±9008C [32]. However, the growth temperature over 8008C is too high to fabricate nm-scale devices such as ISIT structure. To reduce the growth temperature, Si2H6 was used as a source gas. The growth system is schematically shown in Fig. 16. The MLE growth was performed by using temperature synchronized method, namely, the source gas injection was synchronized with the substrate temperature. In a cycle of gas injection, Si2H6 was introduced at the pressure of 1:3 £ 1022 Pa for 10±100 s at the temperature of 4008C, and the substrate was heated up to 5508C and cooled to 4008C within 30 s. Even enough amount of Si2H6 was introduced at 4008C, no growth occurred, therefore, the heating followed by the Si2H6 supply enables the surface reaction to proceed [19].
As shown in Fig. 17, mass spectroscopic measurement proved that the adsorption of SiZH compound is dominant at 4008C after Si2H6 supply, and the hydrogen from the SiZH will release by the surface reaction of SiZHx adsorbate when the substrate was heated up to 5508C. By using the temperature modulation method [33], Si MLE was ®rst accomplished at low temperature with self-limiting process as parameters of duration and/or pressure of Si2H6 supply as shown in Fig. 18.
Fig. 17. Time dependence of (a) controlled substrate temperature, and (b) in-situ mass spectroscopic signal of amu2 H21.
J. Nishizawa, T. Kurabayashi / Thin Solid Films 367 (2000) 13±24
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been studied. The GaAs ISITs with channels as short as 100 Ê are achieved by using MLE and related processes. The I-V A characteristics and the electroluminescence spectra (below Ê ISIT structure band gap, from 0.6±1.4 eV) from the 160 A indicate tunneling through the potential barrier between the source and the drain as room temperature electron transport mechanism. From these results, the electron transit time was estimated as 2 £ 10214 s. The superior microwave performance will be presented soon in another paper. These studies are continued at the Sendai Research Center, TAO, Japan. Recently, not only GaAs but also InP, Si with SiO2 CVD has been developed to achieve ISITs in other materials. References
Fig. 18. Temperature modulation Si MLE. Si2H6 injection duration dependence (a), and Si2H6 pressure dependence.
As related process with Si MLE, chemical vapor deposition of SiO2 in high vacuum has also been studied by introducing Si2H6 and active oxygen (radical O2) from helicon plasma source in the MLE system [20]. SiO2 CVD was intended to fabricate MOS-gate structure in Si MLE chamber. At the partial pressure of 1 £ 1022 Pa for Si2H6 and radical O2, the deposition rate was nearly constant at 0.2 nm/min at the temperature range from 300 to 7508C, while the oxidation speed was 0.04 nm/min by the same amount of radical O2 introduction. At the next stage, MOS gate structure by the CVD SiO2 in Si MLE chamber, and the doping method in Si MLE will be applied to fabricate the MOS gate ISIT structure. 7. Concluding remarks MLE of GaAs has been developed to realize the tera-hertz operating devices with a basic research in the ®eld of surface science and material science. Doping technology and the related process to control the inter-diffusion of dopant, in-situ metal CVD for low resistivity contact have
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