hexagonal boron nitride heterostructure

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Monolayer graphene/hexagonal boron nitride heterostructure Nikhil Jain a, Tanesh Bansal a, Christopher A. Durcan a, Yang Xu b, Bin Yu a b

a,*

College of Nanoscale Science and Engineering, State University of New York, Albany, NY 12203, USA Institute of Microelectronics and Optoelectronics, Zhejiang University, Hangzhou 310027, China

A R T I C L E I N F O

A B S T R A C T

Article history:

A buried metal-gate field-effect transistor (FET) using a stacked hexagonal boron nitride (h-

Received 30 September 2012

BN) and chemically vapor deposited (CVD) graphene heterostructure is demonstrated. A

Accepted 25 November 2012

thin h-BN multilayer serves as both gate dielectric and supporting layer for the monolayer

Available online 5 December 2012

graphene channel. It is observed that electrical stressing could significantly improve graphene conduction, similar to the effect reported in the graphene/SiO2 system. In the graphene/h-BN/TiN FET structure, p-type doping behavior in graphene is observed, possibly attributed to spontaneous doping due to the work function difference between the graphene channel and the metal gate electrode. At a high-level of stress, graphene exhibits ntype doping behavior due to charge transfer across the thin h-BN multilayer. The dielectric strength and tunneling behavior of h-BN are investigated, showing the robust nature of the layer-structured insulator.  2012 Elsevier Ltd. All rights reserved.

1.

Introduction

Graphene, a two-dimensional crystal of sp2-bonded carbon arranged in a honeycomb lattice, has emerged as an intriguing material for a broad spectrum of applications in nanodevices [1]. Given its superb carrier transport properties [2], thermal conductivity [3], and electromechanical behavior [4], it may be used in radio-frequency transistors [5], on-chip interconnects [6], and flexible/three-dimensional electronics [7]. Recently, several research advancements have been made in graphene synthesis by CVD method. Particularly, graphene grown on 8-inch silicon wafers has been reported [8]. Given the atomically-thin nature of graphene, the material behaviors are strongly impacted by its dielectric environment. The study of graphene/substrate coupling effects has revealed that interfacial traps, impurities, and surface phonons of substrate all contribute to degraded carrier transport in graphene [9]. Although suspended graphene has been shown to nearly preserve the intrinsic material

properties, it is not feasible in real device configurations [10]. Hexagonal boron nitride (h-BN), a planar isomorph of graphite with small lattice mismatch (1.7%), has been demonstrated to exhibit excellent adhesion on graphene, avoiding electron–hole puddles. Layered h-BN is an insulator having a wide band-gap (5.5 eV), higher optical phonon energy (2 times that in SiO2), and chemical inertness, making it an excellent choice as the substrate for graphene [11,12]. It also exhibits excellent thermal conductivity which is desirable in reducing heat-induced failure [13] and improving power dissipation at breakdown in graphene [14]. While the graphene/h-BN stack could serve as a key structural element in graphene-based electronics, study on the stability and robustness of the stacked heterostructure has been lacked. In this work, we report electrical stressing induced effects in a graphene/h-BN heterostructure in a locallyburied metal-gate FET configuration. The dielectric strength and carrier-tunneling behavior in a thin h-BN multilayer is also investigated.

* Corresponding author: Fax: +1 518 956 7492. E-mail address: [email protected] (B. Yu). 0008-6223/$ - see front matter  2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.carbon.2012.11.054

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2.

Experimental methods

2.1. Locally-buried heterostructure FET

metal-gate

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graphene/h-BN

Monolayer graphene was grown by the CVD method. A 25 lm thick copper foil was cut into strips (1 cm · 4 cm) and cleaned by dipping in acetic acid (CH3COOH) for 15 min. This removes organic impurities and native oxide from the surface. Afterwards, the Cu strips were loaded into the growth chamber and annealed at 1000 C in an Ar (80 sccm) + H2 (4.5 sccm) environment. Graphene is grown using CH4 (20 sccm) as carbon precursor in an environment of Ar (180 sccm)+H2 (4.5 sccm) at 1000 C for 30 min. After cooling-down, the Cu/ graphene stack was coated with PMMA in a spin-coater at 2000 rpm for 30 s and annealed on a hot plate at 180 C for 3 min. Small pieces of the Cu/graphene/PMMA stack were cut and placed in iron chloride which etched away the Cu, leaving the graphene/PMMA bilayer floating on top of the solution. The graphene was cleaned by repeatedly washing in deionized water and then transferred onto the target substrate. The PMMA was removed by acetone (65 C). A locally-buried titanium nitride (TiN) gate electrode was used in fabricating the graphene/h-BN heterostructure FET. The key fabrication steps are shown in Fig. 1. A 100 nm thick layer of thermal SiO2 was grown on a p-type doped silicon wafer. Subsequently, the gate regions were defined using deep ultra-violet (DUV) lithography. The thermal SiO2 layer was etched away by 1/2 of its original thickness with hydrofluoric acid (HF), and a thick layer of TiN (50 nm) was then deposited by physical-vapor-deposition (PVD) onto the trenched oxide. A chemical–mechanical-planarization (CMP) step was used to remove the excessive TiN, making fully planarized surface as the receiving structure for the layered nanosheets (h-BN

and graphene). The TiN fingers filled into the oxide trenches would serve as the locally-buried metal-gate electrodes for the graphene/h-BN heterostructure FET. Highly-oriented pyrolytic boron nitride (HOPBN) was exfoliated onto the substrate, making nanosheets of thin h-BN multilayer on the interdigitated TiN gate electrode lines, serving as both, the gate dielectric as well as the supporting layer for graphene. The transferred CVD-graphene is patterned by e-beam lithography (EBL) using a negative resist (Hydrogen silsesquioxane), followed by O2 plasma etching to form the active channels of FETs. The final step includes patterning, metal deposition, and lift-off to form source/drain contacts (10 nm Ti/50 nm Au). All electrical measurements were carried out in vacuum by a Lakeshore Cryogenics probe-station and a semiconductor parameter analyzer (Agilent Technologies B1500A). Fig. 2a shows the schematic top-view and the cross-sectional view of the graphene/h-BN heterostructure FET. Fig. 2b is the image obtained by Scanning Electron Microscopy (SEM) of the fabricated device. The EBLpatterned/etched graphene channel and the buried TiN gate electrodes are marked by dashed line and dotted line, respectively.

2.2. Raman and characterization

atomic

force

microscope

(AFM)

The Raman spectrum was obtained with a Horiba Scientific micro-Raman system. The excitation source is a 532 nm laser (2.33 eV) with a laser power below 0.1 mW to avoid laser-induced heating. The laser spot size at focus was around 1 lm in diameter with a 100· objective lens (NA = 0.95). All the Gand D-mode features were adequately fitted with a Lorentzian component of the Voigt profiles (not shown in Fig. 3a). Fig. 3a is the Raman spectrum showing the signature peaks for

Fig. 1 – Schematic shows key steps in the fabrication of the graphene/h-BN heterostructure field-effect transistor. Locallyburied metal-gate electrodes (TiN) are fabricated by damascene process for the graphene-last device structure. A chemical– mechanical-polishing process step is involved to create an ultra-flat receiving structure for layered nanosheets including thin h-BN (as both gate dielectric and supporting substrate) and monolayer graphene channel.

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Fig. 2 – (a) The schematic shows the top-view and the side-view of the buried-gate graphene transistor. (b) Scanning Electron Microscope micrograph of the fabricated device with the dashed and the dotted lines showing the locations of the graphene channel and buried TiN gates, respectively.

Fig. 3 – (a) Raman spectrum showing the signature peaks for the h-BN multilayer and the graphene monolayer. (b)AFM data showing a line scan profiling along the vector marked in the image (seen in the inset). The actual h-BN multilayer thickness is the sum of step height from graphene to the left-over h-BN nanosheet (after O2 plasma etching) and the step height from the left-over h-BN nanosheet to substrate.

graphene and h-BN, respectively. The CVD-grown graphene on h-BN shows distinct G and 2D peaks and a characteristic h-BN peak along with a weak D peak. The G peak is associated with the doubly degenerate (iTO and LO) phonon modes (E2g symmetry) at the Brillouin zone center. It comes from the normal first order Raman scattering process in graphene. The D and 2D peaks originate from the second order process. The D peak comes from the involvement of one iTO phonon and one defect while the 2D peak involves two iTO phonons. The sharpness/height of the D peak indicates the defect level in graphene. A small/weak D peak signal indicates defect-free graphene. The h-BN peak occurs around 1366 cm 1. We observed the ratio of the intensity of the 2D peak and the G-peak (I2D/IG) to be approximately equal to 5.09. This confirms the presence of monolayer graphene of good quality. Fig. 3b is the AFM image of the graphene transistor. The line-scan result (along the direction as depicted in the inset) shows the measured h-BN multilayer thickness to be approximately 35 nm. It should be noted that the oxygen-based plasma process also etches away a portion of the h-BN multilayer (in the

vicinity of the graphene channel), resulting in a step height of 20 nm from graphene to h-BN. The total h-BN thickness was obtained by adding this to the thickness of the remaining hBN giving a total thickness of 55 nm.

3.

Results and discussion

3.1.

Electrical stressing-induced effects

Electrical characterization was conducted to investigate the basic behavior of the graphene/h-BN heterostructure. Before thermal anneal, the current–voltage (I–V) characteristics of the graphene FET show very limited conduction of current (on the order of nano-amperes) due to poor metal contacts at the source/drain ends and the absorbents on graphene surface. These absorbents could be polymer residues introduced during the graphene transfer and the EBL patterning processes. After thermal annealing in a forming gas (Ar + H2) environment for 5 h at 300 C, the device shows four-ordersof-magnitude improvement in electrical conduction (Fig. 4a).

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Fig. 4 – Thermal annealing and breakdown in graphene. (a) Improvement in drain current vs. drain voltage after thermal anneal with pre-anneal data shown in the inset. (b) Graphene permanent breakdown occurs, as 15 V source–drain voltage is applied. Graphene channel length is 750 nm.

Electrical stressing was performed on the graphene/h-BN heterostructure FET. Briefly, a DC voltage sweep was applied on the drain contact from 0 V to a maximum value with the source contact grounded. It is noted that permanent breakdown of graphene occurs at 15 V stressing voltage with a current level of 900 lA (Fig. 4b). We observed that the power dissipation density at breakdown, defined by PBD = JBD (VBD – JBDRC), is increased by seven times in graphene on h-BN as compared with that on SiO2. Here JBD and VBD are the current density and voltage at breakdown, respectively. The difference is explained by the excellent thermal conductivity in h-BN (600 W/mK in-plane and 30 W/mK through-plane, compared to 1 W/mK of SiO2) [15]. Heat dissipation is more efficient through h-BN than through SiO2 under the heat spreading model for the thermal-induced breakdown in graphene [16]. Fig. 5a shows the measured drain-to-source resistance (Rtotal) plotted as a function of the gate voltage (VG) applied on the TiN metal gate after different levels of voltage stressing. The R – VG characteristics are utilized to extract key parameters of the graphene FET. It should be noted that the

peak of the R – VG curve represents the charge-neutrality point (Dirac peak). By using a thin h-BN multilayer as the gate insulator and the supporting substrate for graphene channel, we observed a much narrower Dirac peak in the R – VG curve (a direct indication of improved carrier mobility), as compared with that measured from the reference sample with a CVD graphene channel on top of a 100 nm SiO2-covered Si substrate (as the back gate). The location of the Dirac peak gives an indication of the doping level in the graphene channel. A positive value of gate voltage at the Dirac peak indicates a p-type doping behavior in graphene due to a positive shift in the Fermi level. This is because graphene’s work function (4.48 eV) is smaller than that of TiN (5.3 eV), forming a potential difference across the thin h-BN. Even though the dielectric screens a part of this potential by forming dipoles at the interfaces with TiN as well as with graphene [17], the screening is not complete. This results in a small charge transfer across the dielectric, causing graphene to be weakly p-type doped. After electrical stressing at 14 V, the total resistance reduced significantly. The maximum stressing voltage was selected based on the observed graphene breakdown voltage

Fig. 5 – (a) Total device resistance vs. gate voltage showing improvement in the graphene channel conductance, after the sample was electrically stressed at varying voltages. (b) The reduction in contact resistance vs. electrical stressing voltage.

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(15 V) shown in Fig. 4b. It should be noted that the electrical stressing resulted in negative shift of the Dirac peak, making the graphene turned into n-type doped. This can be explained as a consequence of charge transfer across the thin h-BN multilayer. A positive voltage on graphene compensated the intrinsic potential difference and attracted electrons from the metal through the h-BN gate dielectric. Our observation is consistent with prior theoretical study in which metals were predicted to cause graphene auto-doping due to work function difference [18]. We then interchanged the drain and source contacts, and stressed the device again at a 14 V voltage. This helped to further reduce the total resistance (Fig. 5a). The extracted graphene-metal contact resistance is plotted as a function of the stressing voltage in Fig. 5b. It is noticed that the reduction of resistance at higher level of voltage stressing (shown in Fig. 5a) was almost entirely from the improvement (reduction) of the contact resistance. While the exact cause is yet to be explored, we suspect that the breaking of a thin layer of native metal oxide at a sufficiently high voltage might help improving contact conduction, and that swapping the source/drain helped to improve both contacts, as revealed in Fig. 5b.

3.2.

Thin h-BN multilayer: dielectric behavior

The dielectric behavior of the h-BN multilayer is critical in designing scalable and reliable graphene FETs. We investigate the insulating properties of the thin h-BN multilayer. Fig. 6a shows the electrical current density through a 55 nm thick h-BN multilayer (in the perpendicular-to-plane direction) as a function of electric field applied in the same direction. It is observed that for electric fields as high as 15 MV/cm, no dielectric breakdown occurs. This may be due to the excellent crystallinity and strong B–N covalent bonding in the h-BN lattice. Different from SiO2 or other commonly used dielectrics, interlayer conduction filament or pathway would be very difficult to form in the layer-structured h-BN. While ultra-thin

h-BN is known to exhibit Direct Tunneling (DT) at low-bias and Fowler–Nordheim Tunneling (FNT) at high-bias, as recently reported [19], we observed neither DT nor FNT for our h-BN multilayer (ranging from 17 nm to 55 nm). At low bias, thin h-BN multilayer behaves as an excellent insulator as shown by the very low leakage current density (10 5 A/cm2). However, as applied voltage across the dielectric is increased, at a certain value we notice a sudden increase in conduction level to 10 1 A/cm2. We define this Transitional Voltage as Vtrans. This observed conduction behavior is different from DT or FNT as the tunneling current does not scale with the applied voltage. The values of Vtrans were measured on a large number of h-BN multilayer samples with varying thicknesses (as confirmed by AFM line-scan measurement). Fig. 6b shows the observed dependence of Vtrans on h-BN thickness. We define the electric field at Vtrans as the Critical Dielectric Strength (CDS), given by the slope of Vtrans vs. h-BN thickness curve. Using a linear fit, we observed the slope to be 3.4 MV/cm. It should be noted that the CDS is different from the dielectric breakdown strength at which the material properties are irreversibly altered. We repeatedly observed the same response from our h-BN samples with applied voltage ranging from 0 V to 100 V with no occurrence of dielectric breakdown. The maximum current density remains almost constant in the sub-A/cm2 level at high voltage bias. We believe this could be a result of carrier hopping through the energy states introduced in the h-BN bandgap by impurity substitution or intercalation in the h-BN lattice [20–22]. While h-BN is a wide-bandgap insulator, at a certain threshold electric field (CDS), the carriers obtain sufficient energy to hop through the impurity states from the valence band to the conduction band, resulting in increased carrier conduction. While higher electric field makes the carriers more energetic, conduction is limited by the density of available states (which is a constant). This explains the saturated current in the high-bias regime. When the voltage is low (as in normal FET operation), the carriers do not possess sufficient energy to overcome the

Fig. 6 – Dielectric behavior of the thin h-BN multilayer. (a) Current density (JG) is plotted against the applied gate electric field, showing the leakage current density increases from 10 lA/cm2 to 0.1 A/cm2 at the critical dielectric strength of 4 MV/cm for a gate area of 10 9 cm2. It should be noted that leakage current stays in the nA level until an electrical field of 15 MV/cm is reached. (b) Dependence of the transition voltage (Vtrans) on h-BN physical thickness showing Critical Dielectric Strength of 3.4 MV/cm.

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Fig. 7 – (a) Resistivity (q) of graphene vs. gate voltage, showing the impact of electrical annealing. (b) Measured carrier mobility vs. vertical effective electric field for three different channel/substrate material systems, i.e., CVD-grown monolayer graphene (MLG) on h-BN, exfoliated monolayer graphene (Ex-MLG) on SiO2 and CVD-grown monolayer graphene on SiO2. It is noted that the carrier mobility is 20,000 cm2/V s at an effective field of 5 · 105 MV/cm.

hopping barrier, resulting in an insulating behavior. The lowleakage behavior and the high breakdown threshold make the thin h-BN multilayer a robust gate dielectric.

3.3.

Graphene/h-BN heterostructure: carrier mobility

Finally, we characterized the carrier transport properties of the graphene/h-BN heterostructure FET. The graphene-channel resistivity (excluding graphene/metal contact resistances) is plotted as a function of the gate voltage applied on TiN gate (Fig. 7a), after performing electrical stressing at different levels. We observed that the improvement in resistivity started at a relatively low stressing voltage (5 V) due to the removal of surface adsorbents under Joule heating effect. The field-effect mobility (leff) is extracted based on the method discussed previously [23]. Fig. 7b shows leff as a function of the effective electric field (Eeff) in the perpendicular-to-channel direction. Here Eeff is defined by VG/tD in which VG is the gate voltage and tD is the physical thickness of the gate dielectric. For comparison, three device samples with different channel/gate dielectric stack were characterized: (i) CVD-grown graphene on h-BN, (ii) exfoliated graphene on SiO2, and (iii) CVD-grown graphene on SiO2. It is observed that the sample (i) exhibits the highest value of carrier mobility, 20,000 cm2/V s at the effective electric field of 5 · 105 MV/cm (at room temperature). Similar to our prior result with a silicon back-gate FET structure, the measured leff values show comparable performance gain in the graphene/h-BN heterostructure using a locallyburied metal-gate configuration.

4.

Conclusion

We demonstrated a graphene/h-BN heterostructure FETwith a locally-buried metal-gate design. The thin h-BN multilayer is used as both the gate dielectric and the supporting layer for the graphene channel. In the metal/h-BN/graphene FET structure, spontaneous doping of graphene is observed due to work function difference between graphene and the metal gate. Electrical stressing could improve the conduction of graphene, while being responsible for inducing charge trans-

fer across the thin h-BN gate dielectric. Abnormal, non-tunneling conducting behavior is observed in the h-BN multilayer at high voltage bias, attributed to possible carrier hopping effect. It is observed that h-BN is immune to dielectric breakdown up to at least 15 MV/cm.

Acknowledgements The research was supported by National Science Foundation (NSF) grants (ECCS-1002228 and ECCS-1028267) and SRC/GRC program. The authors greatly appreciate support from Dr. T. Taniguchi and Dr. K. Watanabe at Advanced Materials Laboratory, National Institute for Materials Science (NIMS), Japan. R E F E R E N C E S

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