Multi-pass Lot Scheduling Algorithm for Maximizing Throughput at Semiconductor Final Test Facilities

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ScienceDirect Procedia Manufacturing 11 (2017) 1992 – 2000

27th International Conference on Flexible Automation and Intelligent Manufacturing, FAIM2017, 27-30 June 2017, Modena, Italy

Multi-Pass Lot Scheduling Algorithm for Maximizing Throughput at Semiconductor Final Test Facilities Young Min Jounga, Tian Hea, Sang Won Yoona* Ravi Vancheeswaranb, Cecille Abelab, Herwina R. Andresb a

Department of Systems Science and Industrial Engineering, State University of New York at Binghamton, Binghamton, NY, 13902, USA b Analog Devices Inc., Gateway Business Park, General Trias, Cavite, 4107, Philippines

Abstract This research proposes a multi-pass oriented scheduling heuristic algorithm to determine the test schedules, machine setups, and job assignments for multi-pass lots at a semiconductor final test facility with an objective of maximizing the lot throughput. The proposed algorithm dispatches a group of selected lots and all their passes at a time. The performance of the algorithm is evaluated using the subset data from industry. The results indicate that the proposed heuristic can improve the rate of weekly lot throughput by 9.46% and 7.76% on average compared to the results obtained from the single-pass oriented and the genetic algorithm, respectively. © byby Elsevier B.V.B.V. This is an open access article under the CC BY-NC-ND license © 2017 2017The TheAuthors. Authors.Published Published Elsevier (http://creativecommons.org/licenses/by-nc-nd/4.0/). Peer-review under responsibility of the scientific committee of the 27th International Conference on Flexible Automation and Peer-review under responsibility of the scientific committee of the 27th International Conference on Flexible Automation and IntelligentManufacturing Manufacturing. Intelligent Keywords: Semiconductor final test; Multi-pass; Re-entrant; Throughput

* Corresponding author. Tel.: +1-607-777-5935; fax: +1-607-777-4094. E-mail address: [email protected]

2351-9789 © 2017 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/). Peer-review under responsibility of the scientific committee of the 27th International Conference on Flexible Automation and Intelligent Manufacturing doi:10.1016/j.promfg.2017.07.350

Young Min Joung et al. / Procedia Manufacturing 11 (2017) 1992 – 2000

1. Introduction In a semiconductor industry, the raw materials (e.g., silicon, germanium) must undergo four different fabrication processes to become a fully functional integrated circuit (IC) for a device. The fabrication processes can be categorized as follows: 1) wafer fabrication, 2) wafer probe, 3) assembly or packaging, 4) and final testing [1]. Each fabrication process has challenging issues and has been studied over decades. Typically, the final testing stage has been focused by many researchers, because the final testing is known as the most time-consuming process, in that it is the bottleneck stage [2]. The final testing process is to examine malfunctions of ICs by functional tests in advance to ensure quality before passing it to the end customers. It is important from the company’s perspective to guarantee all IC demands are tested and qualified within a promised timeline while maintaining full utilization of the company’s resources [3]. Several studies reveal that finding an optimal schedule for the lot assignment to machines is NP-hard because the nature of semiconductor final testing scheduling (SFTS) problem involves distinctive characteristics over the traditional job shop problem [1, 2, 4, 5]. Therefore, a traditional job shop problem solution approach is not suitable in SFTS problem [6]. The followings are the practical characteristics of the semiconductor final testing facility that must be considered: (1) Machine configurations: in a semiconductor final testing facility, machines are combination of multiple resources. A tester, a handler, and a fixture compose a machine configuration. Each resource has different inventory level. A fixture is a set of hardware, such as cables, contactors, boards, etc. (2) Lots to machine configurations compatibility: an appropriate machine configuration must be used for each lot to perform functional tests. Promised machine configurations consist of primary and alternatives. Primary machine configuration is the most preferable in real world settings. (3) Lot availability: lots may arrive at the test facility at different times. Lots cannot be tested until they physically become available at the facility. (4) Multi-pass: multi-pass lots must undergo functional testing (e.g., temperature, voltage, etc.) more than once, which is referred as re-entry. For instance, if a multi-pass lot requires three different temperature tests before the shipment, the test operations must be processed three times in a sequential manner with a certain amount of temperature transition time between any two consecutive tests. (5) Sequence-dependent setup time: all lots require setups in preparing machine configurations. In this research, the setup time includes the original setup disassembly time, the new setup assembly time, and the temperature transition time. Based on the sequence-dependent setups duration study, the setups can be roughly classified into three types: 1) Type 1, lot to lot change only, 2) Type 2, hardware changes, and 3) Type 3, handler to handler changes or new machine setups. The temperature transition time is also the sequence-dependent setup time. (6) Lead time: multi-pass lots must finish the succeeding functional operations within the lead time. For example, if a multi-pass lot’s lead time is 168 time units and its first test operation is started at t = 0, the last operation of the lot must be finished no later than t = 168. This research focuses on maximizing throughput of lots when demands are multi-pass. To the best of knowledge, there are not enough studies conducted to help understand the lot assignments to maximize throughputs of lots when re-entrant characteristic is considered. The throughputs of lots is defined as the number of lots that have finished all the functional test operations within the promised timeline. The study reveals that most of existing heuristic approaches are single-pass oriented, such that the throughputs and testing line utilization are poor and excessive number of temperature transition occurs when dispatching multi-pass lots. The consequence is because the singlepass oriented heuristics assign multi-pass lots’ operations individually to appropriate machine configuration. Thus, the proposed multi-pass oriented heuristic algorithm in this research groups operations together based on the product/part types and assigns the operations by groups to maximize the lot throughputs over the pre-defined plan range while fully accounting for the priority. The rest of this paper is outlined as follows. Discussion on related research of SFTS problem and their methodology are in section 2. Details of the multi-pass oriented dispatching

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heuristic algorithm and explanation of the single-pass oriented heuristic algorithm are presented in section 3. Section 4 demonstrates the effectiveness of the multi-pass oriented heuristic algorithm using a small-scale data example and discusses the results by comparing to the single-pass oriented heuristic algorithm results. The results are presented in the Gantt chart format. Lastly, a summary of this paper and future works are provided in section 5. 2. Literature Review A concept of re-entrant characteristic in a shop floor was introduced in 1983 that it is an inevitable consideration in some of IC fabrication scheduling problem [3, 7]. In the practical final testing stage, some lots must undergo series of functional tests, called multi-pass lots. Therefore, the scheduling solution methodology must acknowledge the lot may re-enter a machine configuration several times before its completion. In addition, it is necessary to consider temperature requirements every time the lot re-enter. Thus, the multi-pass scheduling in final test stage is more complicated than the conventional job shop problem with re-entrant characteristic when objective is to maximize lot throughputs, but there have been only few published researches [3]. As the semiconductor manufacturing industry becoming more competitive, it is imperative to maintain minimal planned/unplanned downtime of their resources and never miss the promised due dates to satisfy the customers [4, 8]. Many researchers have concentrated to minimize makespan, i.e. the completion time of the last lot [9] and/or weighted tardiness, such that machines are fully utilized without missing due dates [10-12]. In contrast, maximizing lot throughputs minimizes the idle time of machines, which is also important in the testing facility where machines are highly expensive and costly to operate [6]. Numerous solution approaches have been proposed to satisfy the company’s best interest. An enhanced type of greedy search algorithm has been proposed to maximize the weighted throughput of lots with demand priority consideration [8]. The algorithm rectifies machine-tooling configurations and lot assignments problem iteratively. However, the model assumption that the machines can only be setup once and neglecting re-entrant flow are inadequate in real-world industry context. Lagrangian relaxation approach has also been utilized to solve the scheduling problem when the objective of minimizing the total weighted tardiness [13]. In addition, a decomposition method to minimize maximum lateness in a final test stage with the re-entrant and the sequence-dependent setup times has been studied in 2000 [12]. The decomposition method uses the rolling horizon heuristics to decompose the problem in to sub-problems and elaborate them with metaheuristic approach [14]. Metaheuristic approaches, such as genetic algorithm and tabu search procedure have been applied many times in the SFTS problem solution [15, 16]. The effectiveness of the genetic algorithm in SFTS problem was studied by comparing with the results of six different dispatching rules. Although the genetic algorithm (GA) approach generally takes longer computational time, the solution is close-to-optimal as compare to the result of the mixed integer linear programming (MILP) that they proposed [17]. However, heuristic approaches are adequate to solve the problem because several experiments and statistical analyses have proven that heuristic algorithms are relatively simple and faster, but still performs well to satisfy the company’s interest [18]. 3. Methodology Practically, integer programming (IP) mathematical modeling is the ideal approach because it can provide an optimal solution of the SFTS problem. However, many researchers only utilize the IP model as a benchmark to propose an efficient approach as the IP model generally cause computational burden when the data size increases. Wu and Chien proposed a GA approach to minimize makespan using a mixed integer linear programming (MILP) model as the benchmark [17]. The solution quality of their GA has been proved by comparing the results with the MILP model when different scales of experimental data are tested. This research utilizes the modified version of the GA approach proposed in [17] and the single-pass oriented heuristic approach to compare the solution quality of the proposed multi-pass oriented algorithm. Because the original GA does not incorporate temperature transition time, lot availability as part of the constraints and the objective is to minimize makespan, appropriate adjustments are made to suit the research interest. The modified GA maximizes weekly throughput while accommodating the

Young Min Joung et al. / Procedia Manufacturing 11 (2017) 1992 – 2000

practical constraints of the SFTS problem. To describe the heuristic algorithms, set of necessary notations are defined in Table 1. Table 1. Notations used in this research Notation bij cij

i

Description Beginning time of operation i of lot j Completion time of operation i of lot j Demand priority of lot j Operation

j

Lot

k

Indices of the elements in the tester set






Selected operation i of lot j on machine m

m

Machine configuration m = (t, h, f) which is a specific combination of a tester type t, a handler type h, and a fixture type

pijm

Processing time for operation i of lot j on machine m

rj

Arrival time of lot j





Product type of lot j





The earliest start times of all testers





The earliest start times of all operations

Ff

Set of all fixtures of type f

Hh

Set of all handlers of type h

Mij

Set of machine configurations that can be used to process operation i of lot j





Machine configuration of



L



List of all operations i of lots j Set of operations







assigned to tester



Tt

Set of all testers of type t

Z

Plan range

3.1. Single-pass oriented heuristic algorithm A single-pass oriented dispatching heuristic algorithm is developed to dispatch both single-pass and multi-pass lots. The algorithm is single-pass oriented because the multiple operations of multi-pass lots are dispatched individually as single-pass lots by considering the earliest start time of the multiple operations as the arrival time of single-pass lots. First, the available time window is updated based on the existing setups of the work week. If no WIP exists in this week, all testing lines are available from 0 to 168 time units. Otherwise, the available time range is from the end time of the WIP’s last operation to 168. Secondly, the candidate operations list is sorted in ascending order based on multiple factors such as, setup time, priority, and processing time. After the sortation, the first operation in the list is considered earlier for the assignment. WIP operations are given the highest priority, if exist. The algorithm checks to see if any machine inventory constraints are violated for the selected candidate operation on the selected tester. Lastly, if all constraints are satisfied, the selected candidate operation is assigned and repeat until the candidate operations list is empty or no more operations can be accommodated within the timeline without any constraints violation. The flowchart for the single-pass oriented heuristic algorithm is described in Fig. 1. 3.2. Multi-pass oriented heuristic algorithm A multi-pass oriented dispatching heuristic algorithm is developed especially for the multi-pass lots with the objective of maximizing the lot throughputs within the plan range. Difference with the single-pass oriented dispatching heuristic algorithm is that the operations are not dispatched individually, but are grouped together based on their product/part types and assigned by groups. The algorithm first determines the assignment sequence of operations using the same method as in the single-pass oriented dispatching heuristic algorithm. Secondly, the

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assignment sequence of the operations is determined by the first occurrence of that product type in the candidate operation list. Then, repeat the following rules until no more lot can be assigned within the pre-defined plan range. The multi-pass oriented heuristic assignment algorithm is described as follows. Step 1 Initialize and sort












using the same method as in Section 3.2.
Step 2 Select

=











. Step 3 Select























, sort

in an ascending order of i. Step 4 For all operations i in

, select

 which has 





. Step 5 Select tester

from




 , using Eq. (1).
 
















 












 Step 6 Find the largest time range [

,


] when




 and




 are available. 














. Step 7 Line up

sequentially within [

,


].

(1)

Fig. 1. Flowchart for the single-pass oriented heuristic algorithm

If multiple setups are dedicated to the same multi-pass product after the lot assignment, adjustments are made to reduce the number of temperature changes without reducing the number of lots accommodated. The adjustment procedure is described in Fig. 2. In addition, the algorithm can find all the assignments that start before the given lot arrival time. It swaps all the same temperature operations of two lots to avoid the lot arrival time constraint violation, if exist. In case if the swapping does not work, it deletes the assignments with lot arrival time violations from the dispatching result.

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Fig. 2. Illustration of the assignment adjustment among multiple dedicated setups

4. Numerical Experiments The major difference between the two heuristic algorithms and the GA lies in the candidate operation selection. The single-pass oriented heuristic is set to allocate the lot with shorter processing and setup time, higher demand priority, and fewer resource alternatives earlier than the other candidates. However, each pass of lots is considered individually and assigned myopically, which results in poor solution quality when assigning multi-pass lots. The GA selects the candidate operation according to the chromosomes, where each gene indicates one of six commonly used operation selection rules [17]. The proposed multi-pass oriented heuristic assigns all passes of a lot at a time and uses four steps to modify the dispatching solution as described in the Section 3.2. For the sample experiments, the dispatching plan range is set to 168 time units to illustrate performance of the multi-pass oriented heuristic algorithm over the single-pass oriented heuristic algorithm and the GA when the sample problems are applied. The sample problem specifications are described in the Table 2. Table 2. Specification of the sample problems # of Part Type


# of Lots

# of Operations Per Lot

Total # of Operation

# of Machine Route

Sample Problem 1

1

40 (3 WIPs)

3

117

1

Sample Problem 2

12

62 (2 WIPs)

2 or 3

163

1-6

Fig. 3. Sample problem 1 multi-pass oriented heuristic results

# of Machine Types

Inventory

T : {1} H : {1} F : {
}

T : {5} H : {5} F : {
}

T : {1,…,6} H : {1,…,8} F : {
}

T : {5,2,3,6,1,2} H : {5,3,1,1,1,5,2,7} F : {
}

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Fig. 4. Sample problem 1 single-pass oriented heuristic results

Fig. 5. Sample problem 1 GA results

As shown in Fig. 3, all testing lines are utilized as fully as possible to accommodate maximum weekly lot throughputs within one week. Fig. 4 and Fig. 5 are the visual representation of the single-pass oriented heuristic algorithm and GA results, respectively. Because of the lead time constraint, any lots that couldn’t finish its all operations within the plan range are not counted as the throughput of the week. It is imperative to perform another experiment with a larger sample-size problem to reflect more complicated real-world cases. Therefore, the sample problem 2 is applied to highlight the outperformance of the proposed multipass oriented heuristic algorithm. Table 3 illustrates the results of each approach on the two sample problems. The performances are measured by weekly throughput rate, testing line utilization, number of setups and temperature transitions, and computation time. Table 3. Dispatching result comparison of the two heuristic algorithms and GA Sample Problem 1

Sample Problem 2

Multi-pass Oriented Heuristic

Single-pass Oriented Heuristic

Genetic Algorithm

Multi-pass Oriented Heuristic

Single-pass Oriented Heuristic

Genetic Algorithm

Weekly throughput rate (%)

13.69

11.90

12.50

31.55

30.36

29.76

Makespan (time unit)

160.83

166.60

165.18

166.47

167.27

167.96

Number of Type 1 setup

65

64

65

138

120

119

Number of Type 2 setup

0

0

0

2

4

7

Number of Type 3 setup

2

4

2

8

10

16

Number of temperature changes

8

10

39

19

24

59

Testing line utilization (%)

78.78

77.13

75.21

55.41

54.14

34.52

Number of operations assigned

67

70

67

148

134

142

Number of lots finished

23

20

21

53

51

50

Computation time (sec.)

0.32

0.63

2385.50

0.45

1.52

5927.95

The comparison results indicate that more number of operations/lots are scheduled with fewer setups using the multi-pass oriented heuristic algorithm than the single-pass oriented and the GA approach. This notes that the multipass oriented heuristic algorithm can improve the rate of weekly throughput of lots by 9.46% and 7.76% on average compared to the results obtained by the single-pass oriented and the genetic algorithm, respectively. It is also superior in maintaining higher testing line utilization and fewer unplanned downtime (i.e., setup). In addition, fewer

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number of temperature change occurrence is observed because of the adjustments procedure made after the assignment in the proposed algorithm. Despite the simplicity of understanding the heuristic approach, implementation easiness, and relatively less computation time, the proposed multi-pass oriented heuristic approach superiors the single-pass oriented and the GA approach in all the performance measures. 5. Summary and Future Works In this paper, a multi-pass oriented heuristic dispatching algorithm is proposed to solve the SFTS problem with maximizing throughput as an objective. The algorithm considers all the practical constraints of the semiconductor final testing facility, such as various machine configurations, lots to machine configuration compatibility, sequencedependent setup time, material availability, re-entrant characteristic of multi-pass lot, and its lead time. A GA [17] and a single-pass oriented heuristic algorithm are used to compare the results when generating a schedule solution of multi-pass lots. Two sample problems, which are the sub-sets of real-industry data, are applied to illustrate efficiency and effectiveness of the proposed multi-pass oriented heuristic algorithm. The comparison results indicate that the proposed multi-pass oriented heuristic outperforms the single-pass oriented heuristic and the GA in terms of the throughputs, testing line utilizations, number of setups and temperature transitions, and computation time. The experiment results show that the multi-pass oriented heuristic improves the throughput rate and the testing line utilization by 7.76% and 32.63% on average compared to the GA results. In addition, the multi-pass oriented heuristic yields fewer number of setups and temperature transitions while consuming much less computation time. Thus, the proposed multi-pass oriented heuristic algorithm approach is effective when dealing with multi-pass lots in real-industry setting to maximize weekly throughput. This research can be extended in several directions by considering more unique features of the multi-pass lots. For example, some multi-pass lots must go through a burn-in process. Burn-in process also has challenging issues, such as batch process scheduling and operational lapse time. The capacity of burn-in oven could be different than the testing machine, such that a lot may have to be separated into two batches. In addition, the lapse time is the limited given time for a lot’s remaining operations to finish after the burn-in operation, otherwise the lot must revisit the burn-in process to properly test the following operation. To study the entire multi-pass test scheduling problem, further research on the burn-in process is necessary. Acknowledgements This research is supported by Analog Devices Inc. at General Trias (ADGT). The authors appreciate generous assistance from all members related to this research project from the planning and dispatching groups of ADGT. Special thanks go to Ed Fortunado, Sammy Lazo, Marivic Floro, Abby Llarena, and Louise Tan for their assistance in empirical studies. References [1] R. Uzsoy, L.K. Church, I.M. Ovacik, and J. Hinchman, Dispatching rules for semiconductor testing operations: A computational study, In Electronics Manufacturing Technology Symposium, 1992, Thirteenth IEEE/CHMT International, pp.272-276, IEEE, 1992. [2] D.M. Chiang, R.S. Guo, and F.Y. Pai, Improved customer satisfaction with a hybrid dispatching rule in semiconductor back-end factories, International Journal of Production Research, 2008, 46, 4903-4923. [3] Z. Gao, J.F. Bard, R. Chacon, J. Stuber, An assignment-sequencing methodology for scheduling assembly and test operations with multi-pass requirements, IIE Transactions, 2015, 47(2), 153-172. [4] W.L. Pearn, S.H. Chung, A.Y. Chen, M.H. Yang, A case study on the multistage IC final testing scheduling problem with reentry, International Journal of Production Economics, 2004, 88(3), 257-267. [5] S.W. Choi, Y.D. Kim, Minimizing makespan on an m-machine re-entrant flowshop, Computers & Operations Research, 2008,35(5), 16841696. [6] T. He, Y.M. Joung, S.W. Yoon, R. Vancheeswaran, R.A. Herwina, Dispatching optimization with sequence dependent setup times in semiconductor final testing scheduling, Proceedings of the 26th International Conference on Flexibile Automation and Intelligent Manufacturing (FAIM 2016), 2016, June 27-30, Seoul, Republic of Korea. [7] S.C. Graves, H.C. Meal, D. Stefek, A.H. Zeghmi, Scheduling of re-entrant flow shops, Journal of Operations Management, 1983, 3(4), 197207

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