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Multichannel direct sequence spectrum signaling using code phase shift keying
Computers and Electrical Engineering 35 (2009) 218–226
Contents lists available at ScienceDirect
Computers and Electrical Engineering journal homepage: www.elsevier.com/locate/compeleceng
Technical Communication
Multichannel direct sequence spectrum signaling using code phase shift keying P.P. Sahu *, Mahipal Singh Department of Electronics and Communication Engineering, Tezpur University, Assam, India
a r t i c l e
i n f o
Article history: Available online 5 November 2008 Keywords: CPSK DSSS BER
a b s t r a c t In this paper, we have designed and realized multichannel direct sequence spread spectrum (DSSS) system using code phase shift keying (CPSK). In the transmitter, taking each bit from each channel, data word is made as a symbol for selecting PN sequence, which is modulated with frequency of 100 MHz as DSSS signals. At the receiver, the correlator, integrator and decoder are used for separation of the signal of respective channel after demodulation. Oscilloscope traces show that the transmitted signals are matched with the simulated signals at the receiver. The bit error rate (BER) variation with jamming signal is estimated by our proposed simulation model, matching well with experimental values of BER measured by BER meter. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction The direct sequence spread spectrum (DSSS) system has become popular in wireless personal communication due to its low susceptibility to interference from other parties and high security. It involves spreading the desired signal over a bandwidth much larger than the minimum bandwidth necessary to send the signal [1]. The interference rejection increases with increase of spreading gain or processing gain. In simple DSSS system [2–4], PN sequences multiplies data signal. The resultant signal is modulated with the carrier via multiplier. The simple DSSS receiver just performs the reverse operation and integrates into the received signal. In comparison to frequency hopping spread spectrum [5–7], it is simpler and easier to implement. Moreover, using simple DSSS, we can accommodate large number of users with code division multiplexing access (CDMA) without increase of bandwidth. The drawback of simple DSSS system is that the PN sequences may interfere with each other resulting degradation of bit error rate performance. It was further modified using by the code phase shift keying [2,4], which has higher throughput. In reference [2,4], CPSK based signaling scheme has been used for single channel. In this paper, we have designed code phase shift keying based DSSS (CPSK/DSSS) system for more than single channel. We have designed and simulated the circuit using Microsim EDA software release 8. The circuit has been analyzed with noise. We have proposed simulation model for BER performance analysis with and without jamming. The experimental result of the implemented four-channel CPSK/DSSS circuit is also shown.
2. Multichannel CPSK/DSSS signaling scheme Fig. 1 shows multichannel CPSK/DSSS signaling scheme, which consists of transmitter and receiver. In figure, we have used the scheme for K number of channels. Each symbol of this signaling scheme is a K bit data word in which each bit
* Corresponding author. E-mail address: [email protected] (P.P. Sahu). 0045-7906/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.compeleceng.2008.09.002
P.P. Sahu, M. Singh / Computers and Electrical Engineering 35 (2009) 218–226
Fig. 1. (a) Block diagram of K-channel CPSK/DSSS transmitter. (b) Block diagram of K-channel CPSK/DSSS receiver.
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has been taken from each channel. Each symbol select one of the M = 2K PN sequences pm(t) which are generated from a PN code generator and the selected PN sequence is then modulated with phase shift keying for transmission via antenna. 2.1. CPSK/DSSS transmitter Fig. 1a shows K-channel CPSK/DSSS transmitter, which consists of PN sequence selector, data word generator, bi-level shifter and multiplier. In figure, for testing purpose, we have used data word generator which generates the signals of Ch-1, Ch-2, Ch-3, . . ., Ch-K. Taking each bit from each channel, we have made K-bit data word (called as a symbol). The CPSK part consists of PN sequence selector and phase shift keying. The PN sequence selector selects a PN sequence according to symbol word and then the binary levels of PN coded signal are converted into +5 V and 5 V level by bi-level shifter. The bileveled PN coded signal is modulated with the carrier frequency fc of 100 MHz to generate DSSS signal. The transmitted signal of mth symbol is defined as
rffiffiffiffiffiffiffiffi 2Es p ðtÞ sin½2pðfc Þ Sm ðtÞ ¼ T m
ð1Þ
where m = 1, 2, 3, . . ., M; M = 2K and K = total number of channel in CMFSK signaling; pm(t) = p(t mcTc); mc = m(L + 1)/M; Tc = chip interval; L = length of PN sequence and T = symbol period; Es = signal power of a symbol.
Fig. 2. (a) Schematic of four-channel CPSK/DSSS transmitter. (b) Schematic of four-channel CPSK/DSSS receiver.
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2.2. CPSK/DSSS receiver Fig. 1b shows the block diagram of K-channel CPSK receiver, which consists of demodulator, PN sequence generator, correlator and integrator and decoder. In the figure, the received signal is mixed with carrier frequency in the demodulator via
Fig. 2 (continued)
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multiplier. The multiplied signal passes through to Sallen-Key filter to get the received PN coded signal. The correlator is EXNOR gate which correlates demodulated signal with the locally generated PN sequences (PN-1, 2, 3, . . ., M) as same as that of transmitter. To synchronize the received PN and locally generated PN sequence in DSSS the acquisition and tracking method is generally used [2]. Here, we have delayed the local PN sequence, to synchronize it with the received PN sequence. In Kchannel receiver, there is M = 2K states corresponding to K-bit address word. So there are M number of correlator and integrator. After correlation, the signal is integrated with the help of integrator circuits. In between the correlator and integrator circuit reset circuit has been introduced for resetting the output of each correlator to zero at the end of integration cycle. Also we see that there is a phase difference between the received PN sequence and locally generated PN sequences. This phase difference has been removed using a delay device, which introduces appropriate delay in the locally generated PN sequence to match with the received PN sequences. So the received PN sequences are correlated with all the M locally generated PN sequences and output of M number of correlated circuit are integrated simultaneously. One of the M correlator, in which the received PN sequence is matched with a locally generated PN sequence, gives more signal power. In the figure, there are M comparators to compare the corresponding integrated signal with reference level. After comparison, the signal is fed to decoder, which consists of K number of OR gate for K-channels. The number of inputs of OR gate is 2K. The decoder separates the channels. 2.3. Simulation result with out noise We have simulated both CPSK/DSSS transmitter and receiver circuit with four channels (K = 4) using Microsim EDA software release version 8. Fig. 2a shows schematic of four channels CPSK/DSSS transmitter, whereas Fig. 2b shows the schematic of CPSK/DSSS receiver. Fig. 3a shows simulated waveform of different stages of the transmitter. First waveform in the figure indicates signals, a–d of four channels, ch-1–ch-4, respectively. In the figure, these channels construct two data word – 0000 and 1000. These two symbol words are coded with two PN sequences as seen in figure. The PN coded signal is modulated with carrier frequency of 100 MHz using BPSK as DSSS signal. Fig. 3b shows simulated waveform of different stages of receiver. First waveform indicates demodulated signal. Second waveform represents the filtered PN coded signal. The filtered PN coded signal is converted into two data words – 0000 and 1000 using correlator and integrator. The four channels are separated using decoder as per Table 1. Third waveform
Data
PN coded signal
DSSS Transmitted Signal
Waveform of different stages of transmitter
Received signal after BPSK demodulation
Filtered PN coded signal Decoded data
Waveform of different stages of Receiver Fig. 3. (a) Waveform of different stages of transmitter. (b) Waveform of different stages of receiver.
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P.P. Sahu, M. Singh / Computers and Electrical Engineering 35 (2009) 218–226 Table 1 Inputs of decoders for separation of channels ch-1, ch-2, ch-3, ch-4 Inputs of decoder
Decoder
Outputs
A1, A2, A4, A8,
Decoder-1 Decoder-2 Decoder-3 Decoder-4
Y0 Y1 Y2 Y3
A3, A3, A5, A9,
A5, A7, A9, A11, A13, A15 A6, A7, A10, A11, A14, A15 A6, A7, A12, A13, A14, A15 A10, A11, A12, A13, A14, A15
in the figure shows the separated signals, a–d for four channels, ch-1–ch-4, respectively. These waveforms are as same as transmitted channels. 3. Simulation model for BER performance analysis Fig. 4 shows the block diagram of simulation model for bit error rate (BER) analysis. Simulation model consists of data generator, CPSK transmitter, CPSK demodulator, additive white Gaussian noise (AWGN) generator (2 kHz–150 MHz), and Jamming signal generator, and comparator. The data generator generates the signal of four channels and CPSK transmitter modulates the signal at the carrier frequency of 100 MHz. AWGN generator develops noise, which is mixed with CPSK signal by mixer circuit. The generated jamming signal is then mixed with CPSK signal via mixer circuit as shown in Fig. 4. The mixed signal is fed to the CPSK demodulator. CPSK demodulator processes the signal and decodes back to the transmitted data with some delay depending upon different active and passive component used in the demodulator. So, to synchronize the received and transmitted data, a delay device is introduced in the transmitted signal. The received data is synchronized using a D flip-flop with the data generator clock. The comparator is an EX-OR gate, which determines error bit after comparison. If both, the transmitted data and received data are same, the output of EX_ OR gate will be low. If transmitted and received data are differed, the output of EX-OR gate will become high. These high outputs are treated as errors. The bit error rate (BER) is estimated by dividing the total numbers of error bit by total number of bits transmitted. 3.1. Results for BER performance We have tested our simulation model for BER analysis using Microsim EDA software release 8 for four channels and compared the same with FPGA based CPSK/DSSS system [4]. Fig. 5 shows the comparison of BER performance between the FPGA based CPSK/DSSS system [4] and four-channel CPSK/DSSS system. It is evident from the figure that the BER performance is degraded as SNR decreases in both the DSSS system. The BER performance of four-channel CPSK/DSSS system is better than that of FPGA based CPSK/DSSS system [4]. The BER performance is analyzed when the predefined data patterns sent by transmitter is mixed with the jamming signals. For BER analysis under jamming, we have taken SNR 4, 12, and 14 dB. Fig. 6 shows the variation of BER with jamming to signal ratio (JSR) in case of four-channel CPSK/DSSS circuit with our simulation model of carrier frequency fc = 100 MHz. It is evident from the figure that the BER increases with JSR for all SNR. As SNR decreases, the system is more tolerant to the
Jamming Signal
Clock
Data Generator
CPSK Transmitt
Mixer
AWGN Generator (6KHz-25 MHz
CPSK Demod Comparator Delay
D Flip Flop
Fig. 4. Simulation model for bit error rate.
Error Bits
224
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10-2
Simulation model for 4 channels 10-3
FPGA based CPSK/DS [4]
BER
10-4
10-5
10-6
10-7 0
2
4
6
8
10
12
14
S/N (dB) Fig. 5. Comparison of BER performance between CPSK/DSSS using our simulation model and FPGA based CPSK/DSSS.
10 -1
10 -2
BER
SNR ~ 8dB
10 -3
SNR~ 12dB
10 -4
SNR~14 dB
10 -5 -18
-16
-14
-12
-10
-8
-6
-4
JSR (dB) Fig. 6. BER performance of four-channel CPSK/DSSS with CPSK jamming (cross points represent experimental point for BER at SNR of 8, 12, and 14 dB).
jamming signal. When there is no jamming, the BER is 1.5 105 at an SNR of 8 dB. With introduction of jamming signal the BER is increased to 3.2 103 and 8 103 at JSR of 11 and 8 dB, respectively. The cross points in the figure represent the experimental values of BER for SNR of 8, 12, and 14 dB measured by BER meter (which is discussed later on). 4. Implementation in PCB level and measurement We have implemented the four-channel CPSK/DSSS circuit in PCB level using copper clad plate. We have made the PCB as per the layout of the circuit. Fig. 7 shows oscilloscope traces of different stages of the transmitter and receiver of four-channel CPSK/DSSS system.. We have constructed data patterns of four channels for testing of the circuit as shown in trace (a). In trace (a), there are two data symbol, 0000 and 1000. The trace (b) shows the coded PN sequence of these symbols of
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Fig. 7. Oscilloscope traces of different stages of transmitter and receiver of four-channel CPSK/DSSS system.
Fig. 8. Oscilloscope traces of 16 PN sequences used for four-channel CPSK/DSSS circuit.
four-channel. After demodulation, we get the PN coded signals, which are shown in trace (c). After decoding, we separate the signals, which are given in trace (d). In trace (d), there are two symbols 0000 and 1000 which are also matched with symbols obtained with simulation using Microsim EDA software release version 8. The traces of 16 PN sequences used for four-channel CPSK/DSSS are shown in Fig. 8. We have also measured BER at SNR of 8, 12, and 14 dB by using BER meter. These experimental values of BER obtained at JSR of 5.6, 7.2, 10.7, and 16.8 dB are almost close to theoretical curves in Fig. 6. 5. Conclusion We have designed and implemented both CPSK/DSSS transmitter and receiver circuit with four channels (K = 4) using Microsim EDA software release version 8. We have developed simulation model for BER performance analysis of CPSK/DSSS system. The BER performance for CPSK/DSSS system is better than that of existing FPGA based CPSK system [4]. The simulated waveforms are also matched with oscilloscope traces. The experimental values of BER obtained at JSR of 5.6, 7.2, 10.7, and 16.8 dB are almost close to the simulated curves.
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References [1] Magill DT, Natali FD, Edwards GP. Spread spectrum technology for commercial applications. Proc IEEE 1994;82:572–8. [2] Wong AYC, Leung VCM. Code-phase-shift keying: a power and bandwidth efficient spread spectrum signaling technique for wireless local area network applications. In: Proceedings of the IEEE CCECE’97; 1997. p. 478–81. [3] Link R, Leung VCM. Design of a DSP-based code phase shift keying modem for wireless local are network applications. In: Proceedings of the IEEE VTC‘97; 1997. p. 1069–73. [4] Chan SKS, Leung VCM. A FPGA receiver for CPSK spread spectrum signaling. IEEE Trans Consum Electron 1999;45(1):181–91. [5] Ryu Heung-Gyoon, Li Yingshan, Park Jin-Soo. Effects of frequency instability caused by phase noise on the performance of the fast FH communications system. IEEE Trans Vehicul Technol 2004;53(5):1626–32. [6] Taub H, Schilling DL. Principles of communication systems. NewYork: McGraw Hill Inc.; 1986. [7] Sahu PP, Singh M. Multichannel frequency hopping spread spectrum signaling using code M-ary frequency shift keying. Comput Electr Eng J 2008;34(4):338–45.
P.P. Sahu received M.Tech. degree from Indian Institute of Technology, Delhi and Ph.D. degree in Engineering from Jadavpur University, India. In 1991, he joined Haryana State Electronics Development Corporation Limited. In 1996, he joined North Eastern Regional Institute of Science and Technology as a faculty member. At present, he is working as a Reader in Department of Electronics, Tezpur Central University, India, since 1998. His field of interest is integrated optic and electronic circuits, wireless and optical communication networks. He has published more than 40 papers in International Journals and conference. He is Fellow of Optical Society of India, member of IEE, UK, member of optical society of America and life member of Indian Society for Technical Education.
Mahipal Singh received M.Tech. from Tezpur University in 2005. He was working in Indian Air force for 16 years. Now, he is working as Lecturer in Soviet Institute of Technology, Saharanpur, Uttar Pradesh, India.
Contents lists available at ScienceDirect
Computers and Electrical Engineering journal homepage: www.elsevier.com/locate/compeleceng
Technical Communication
Multichannel direct sequence spectrum signaling using code phase shift keying P.P. Sahu *, Mahipal Singh Department of Electronics and Communication Engineering, Tezpur University, Assam, India
a r t i c l e
i n f o
Article history: Available online 5 November 2008 Keywords: CPSK DSSS BER
a b s t r a c t In this paper, we have designed and realized multichannel direct sequence spread spectrum (DSSS) system using code phase shift keying (CPSK). In the transmitter, taking each bit from each channel, data word is made as a symbol for selecting PN sequence, which is modulated with frequency of 100 MHz as DSSS signals. At the receiver, the correlator, integrator and decoder are used for separation of the signal of respective channel after demodulation. Oscilloscope traces show that the transmitted signals are matched with the simulated signals at the receiver. The bit error rate (BER) variation with jamming signal is estimated by our proposed simulation model, matching well with experimental values of BER measured by BER meter. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction The direct sequence spread spectrum (DSSS) system has become popular in wireless personal communication due to its low susceptibility to interference from other parties and high security. It involves spreading the desired signal over a bandwidth much larger than the minimum bandwidth necessary to send the signal [1]. The interference rejection increases with increase of spreading gain or processing gain. In simple DSSS system [2–4], PN sequences multiplies data signal. The resultant signal is modulated with the carrier via multiplier. The simple DSSS receiver just performs the reverse operation and integrates into the received signal. In comparison to frequency hopping spread spectrum [5–7], it is simpler and easier to implement. Moreover, using simple DSSS, we can accommodate large number of users with code division multiplexing access (CDMA) without increase of bandwidth. The drawback of simple DSSS system is that the PN sequences may interfere with each other resulting degradation of bit error rate performance. It was further modified using by the code phase shift keying [2,4], which has higher throughput. In reference [2,4], CPSK based signaling scheme has been used for single channel. In this paper, we have designed code phase shift keying based DSSS (CPSK/DSSS) system for more than single channel. We have designed and simulated the circuit using Microsim EDA software release 8. The circuit has been analyzed with noise. We have proposed simulation model for BER performance analysis with and without jamming. The experimental result of the implemented four-channel CPSK/DSSS circuit is also shown.
2. Multichannel CPSK/DSSS signaling scheme Fig. 1 shows multichannel CPSK/DSSS signaling scheme, which consists of transmitter and receiver. In figure, we have used the scheme for K number of channels. Each symbol of this signaling scheme is a K bit data word in which each bit
* Corresponding author. E-mail address: [email protected] (P.P. Sahu). 0045-7906/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.compeleceng.2008.09.002
P.P. Sahu, M. Singh / Computers and Electrical Engineering 35 (2009) 218–226
Fig. 1. (a) Block diagram of K-channel CPSK/DSSS transmitter. (b) Block diagram of K-channel CPSK/DSSS receiver.
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has been taken from each channel. Each symbol select one of the M = 2K PN sequences pm(t) which are generated from a PN code generator and the selected PN sequence is then modulated with phase shift keying for transmission via antenna. 2.1. CPSK/DSSS transmitter Fig. 1a shows K-channel CPSK/DSSS transmitter, which consists of PN sequence selector, data word generator, bi-level shifter and multiplier. In figure, for testing purpose, we have used data word generator which generates the signals of Ch-1, Ch-2, Ch-3, . . ., Ch-K. Taking each bit from each channel, we have made K-bit data word (called as a symbol). The CPSK part consists of PN sequence selector and phase shift keying. The PN sequence selector selects a PN sequence according to symbol word and then the binary levels of PN coded signal are converted into +5 V and 5 V level by bi-level shifter. The bileveled PN coded signal is modulated with the carrier frequency fc of 100 MHz to generate DSSS signal. The transmitted signal of mth symbol is defined as
rffiffiffiffiffiffiffiffi 2Es p ðtÞ sin½2pðfc Þ Sm ðtÞ ¼ T m
ð1Þ
where m = 1, 2, 3, . . ., M; M = 2K and K = total number of channel in CMFSK signaling; pm(t) = p(t mcTc); mc = m(L + 1)/M; Tc = chip interval; L = length of PN sequence and T = symbol period; Es = signal power of a symbol.
Fig. 2. (a) Schematic of four-channel CPSK/DSSS transmitter. (b) Schematic of four-channel CPSK/DSSS receiver.
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221
2.2. CPSK/DSSS receiver Fig. 1b shows the block diagram of K-channel CPSK receiver, which consists of demodulator, PN sequence generator, correlator and integrator and decoder. In the figure, the received signal is mixed with carrier frequency in the demodulator via
Fig. 2 (continued)
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multiplier. The multiplied signal passes through to Sallen-Key filter to get the received PN coded signal. The correlator is EXNOR gate which correlates demodulated signal with the locally generated PN sequences (PN-1, 2, 3, . . ., M) as same as that of transmitter. To synchronize the received PN and locally generated PN sequence in DSSS the acquisition and tracking method is generally used [2]. Here, we have delayed the local PN sequence, to synchronize it with the received PN sequence. In Kchannel receiver, there is M = 2K states corresponding to K-bit address word. So there are M number of correlator and integrator. After correlation, the signal is integrated with the help of integrator circuits. In between the correlator and integrator circuit reset circuit has been introduced for resetting the output of each correlator to zero at the end of integration cycle. Also we see that there is a phase difference between the received PN sequence and locally generated PN sequences. This phase difference has been removed using a delay device, which introduces appropriate delay in the locally generated PN sequence to match with the received PN sequences. So the received PN sequences are correlated with all the M locally generated PN sequences and output of M number of correlated circuit are integrated simultaneously. One of the M correlator, in which the received PN sequence is matched with a locally generated PN sequence, gives more signal power. In the figure, there are M comparators to compare the corresponding integrated signal with reference level. After comparison, the signal is fed to decoder, which consists of K number of OR gate for K-channels. The number of inputs of OR gate is 2K. The decoder separates the channels. 2.3. Simulation result with out noise We have simulated both CPSK/DSSS transmitter and receiver circuit with four channels (K = 4) using Microsim EDA software release version 8. Fig. 2a shows schematic of four channels CPSK/DSSS transmitter, whereas Fig. 2b shows the schematic of CPSK/DSSS receiver. Fig. 3a shows simulated waveform of different stages of the transmitter. First waveform in the figure indicates signals, a–d of four channels, ch-1–ch-4, respectively. In the figure, these channels construct two data word – 0000 and 1000. These two symbol words are coded with two PN sequences as seen in figure. The PN coded signal is modulated with carrier frequency of 100 MHz using BPSK as DSSS signal. Fig. 3b shows simulated waveform of different stages of receiver. First waveform indicates demodulated signal. Second waveform represents the filtered PN coded signal. The filtered PN coded signal is converted into two data words – 0000 and 1000 using correlator and integrator. The four channels are separated using decoder as per Table 1. Third waveform
Data
PN coded signal
DSSS Transmitted Signal
Waveform of different stages of transmitter
Received signal after BPSK demodulation
Filtered PN coded signal Decoded data
Waveform of different stages of Receiver Fig. 3. (a) Waveform of different stages of transmitter. (b) Waveform of different stages of receiver.
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P.P. Sahu, M. Singh / Computers and Electrical Engineering 35 (2009) 218–226 Table 1 Inputs of decoders for separation of channels ch-1, ch-2, ch-3, ch-4 Inputs of decoder
Decoder
Outputs
A1, A2, A4, A8,
Decoder-1 Decoder-2 Decoder-3 Decoder-4
Y0 Y1 Y2 Y3
A3, A3, A5, A9,
A5, A7, A9, A11, A13, A15 A6, A7, A10, A11, A14, A15 A6, A7, A12, A13, A14, A15 A10, A11, A12, A13, A14, A15
in the figure shows the separated signals, a–d for four channels, ch-1–ch-4, respectively. These waveforms are as same as transmitted channels. 3. Simulation model for BER performance analysis Fig. 4 shows the block diagram of simulation model for bit error rate (BER) analysis. Simulation model consists of data generator, CPSK transmitter, CPSK demodulator, additive white Gaussian noise (AWGN) generator (2 kHz–150 MHz), and Jamming signal generator, and comparator. The data generator generates the signal of four channels and CPSK transmitter modulates the signal at the carrier frequency of 100 MHz. AWGN generator develops noise, which is mixed with CPSK signal by mixer circuit. The generated jamming signal is then mixed with CPSK signal via mixer circuit as shown in Fig. 4. The mixed signal is fed to the CPSK demodulator. CPSK demodulator processes the signal and decodes back to the transmitted data with some delay depending upon different active and passive component used in the demodulator. So, to synchronize the received and transmitted data, a delay device is introduced in the transmitted signal. The received data is synchronized using a D flip-flop with the data generator clock. The comparator is an EX-OR gate, which determines error bit after comparison. If both, the transmitted data and received data are same, the output of EX_ OR gate will be low. If transmitted and received data are differed, the output of EX-OR gate will become high. These high outputs are treated as errors. The bit error rate (BER) is estimated by dividing the total numbers of error bit by total number of bits transmitted. 3.1. Results for BER performance We have tested our simulation model for BER analysis using Microsim EDA software release 8 for four channels and compared the same with FPGA based CPSK/DSSS system [4]. Fig. 5 shows the comparison of BER performance between the FPGA based CPSK/DSSS system [4] and four-channel CPSK/DSSS system. It is evident from the figure that the BER performance is degraded as SNR decreases in both the DSSS system. The BER performance of four-channel CPSK/DSSS system is better than that of FPGA based CPSK/DSSS system [4]. The BER performance is analyzed when the predefined data patterns sent by transmitter is mixed with the jamming signals. For BER analysis under jamming, we have taken SNR 4, 12, and 14 dB. Fig. 6 shows the variation of BER with jamming to signal ratio (JSR) in case of four-channel CPSK/DSSS circuit with our simulation model of carrier frequency fc = 100 MHz. It is evident from the figure that the BER increases with JSR for all SNR. As SNR decreases, the system is more tolerant to the
Jamming Signal
Clock
Data Generator
CPSK Transmitt
Mixer
AWGN Generator (6KHz-25 MHz
CPSK Demod Comparator Delay
D Flip Flop
Fig. 4. Simulation model for bit error rate.
Error Bits
224
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10-2
Simulation model for 4 channels 10-3
FPGA based CPSK/DS [4]
BER
10-4
10-5
10-6
10-7 0
2
4
6
8
10
12
14
S/N (dB) Fig. 5. Comparison of BER performance between CPSK/DSSS using our simulation model and FPGA based CPSK/DSSS.
10 -1
10 -2
BER
SNR ~ 8dB
10 -3
SNR~ 12dB
10 -4
SNR~14 dB
10 -5 -18
-16
-14
-12
-10
-8
-6
-4
JSR (dB) Fig. 6. BER performance of four-channel CPSK/DSSS with CPSK jamming (cross points represent experimental point for BER at SNR of 8, 12, and 14 dB).
jamming signal. When there is no jamming, the BER is 1.5 105 at an SNR of 8 dB. With introduction of jamming signal the BER is increased to 3.2 103 and 8 103 at JSR of 11 and 8 dB, respectively. The cross points in the figure represent the experimental values of BER for SNR of 8, 12, and 14 dB measured by BER meter (which is discussed later on). 4. Implementation in PCB level and measurement We have implemented the four-channel CPSK/DSSS circuit in PCB level using copper clad plate. We have made the PCB as per the layout of the circuit. Fig. 7 shows oscilloscope traces of different stages of the transmitter and receiver of four-channel CPSK/DSSS system.. We have constructed data patterns of four channels for testing of the circuit as shown in trace (a). In trace (a), there are two data symbol, 0000 and 1000. The trace (b) shows the coded PN sequence of these symbols of
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225
Fig. 7. Oscilloscope traces of different stages of transmitter and receiver of four-channel CPSK/DSSS system.
Fig. 8. Oscilloscope traces of 16 PN sequences used for four-channel CPSK/DSSS circuit.
four-channel. After demodulation, we get the PN coded signals, which are shown in trace (c). After decoding, we separate the signals, which are given in trace (d). In trace (d), there are two symbols 0000 and 1000 which are also matched with symbols obtained with simulation using Microsim EDA software release version 8. The traces of 16 PN sequences used for four-channel CPSK/DSSS are shown in Fig. 8. We have also measured BER at SNR of 8, 12, and 14 dB by using BER meter. These experimental values of BER obtained at JSR of 5.6, 7.2, 10.7, and 16.8 dB are almost close to theoretical curves in Fig. 6. 5. Conclusion We have designed and implemented both CPSK/DSSS transmitter and receiver circuit with four channels (K = 4) using Microsim EDA software release version 8. We have developed simulation model for BER performance analysis of CPSK/DSSS system. The BER performance for CPSK/DSSS system is better than that of existing FPGA based CPSK system [4]. The simulated waveforms are also matched with oscilloscope traces. The experimental values of BER obtained at JSR of 5.6, 7.2, 10.7, and 16.8 dB are almost close to the simulated curves.
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References [1] Magill DT, Natali FD, Edwards GP. Spread spectrum technology for commercial applications. Proc IEEE 1994;82:572–8. [2] Wong AYC, Leung VCM. Code-phase-shift keying: a power and bandwidth efficient spread spectrum signaling technique for wireless local area network applications. In: Proceedings of the IEEE CCECE’97; 1997. p. 478–81. [3] Link R, Leung VCM. Design of a DSP-based code phase shift keying modem for wireless local are network applications. In: Proceedings of the IEEE VTC‘97; 1997. p. 1069–73. [4] Chan SKS, Leung VCM. A FPGA receiver for CPSK spread spectrum signaling. IEEE Trans Consum Electron 1999;45(1):181–91. [5] Ryu Heung-Gyoon, Li Yingshan, Park Jin-Soo. Effects of frequency instability caused by phase noise on the performance of the fast FH communications system. IEEE Trans Vehicul Technol 2004;53(5):1626–32. [6] Taub H, Schilling DL. Principles of communication systems. NewYork: McGraw Hill Inc.; 1986. [7] Sahu PP, Singh M. Multichannel frequency hopping spread spectrum signaling using code M-ary frequency shift keying. Comput Electr Eng J 2008;34(4):338–45.
P.P. Sahu received M.Tech. degree from Indian Institute of Technology, Delhi and Ph.D. degree in Engineering from Jadavpur University, India. In 1991, he joined Haryana State Electronics Development Corporation Limited. In 1996, he joined North Eastern Regional Institute of Science and Technology as a faculty member. At present, he is working as a Reader in Department of Electronics, Tezpur Central University, India, since 1998. His field of interest is integrated optic and electronic circuits, wireless and optical communication networks. He has published more than 40 papers in International Journals and conference. He is Fellow of Optical Society of India, member of IEE, UK, member of optical society of America and life member of Indian Society for Technical Education.
Mahipal Singh received M.Tech. from Tezpur University in 2005. He was working in Indian Air force for 16 years. Now, he is working as Lecturer in Soviet Institute of Technology, Saharanpur, Uttar Pradesh, India.