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relaxed-SiGe heterostructure grown by UHVCVD
Solid-State Electronics 45 (2001) 1945±1949
N2O oxidation of strained-Si/relaxed-SiGe heterostructure grown by UHVCVD C.S. Tan a, W.K. Choi a,*,1, L.K. Bera a, K.L. Pey a,1, D.A. Antoniadis b,1, E.A. Fitzgerald b,1, M.T. Currie b, C.K. Maiti c a
c
Microelectronics Laboratory, Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, Singapore 117576, Singapore b Massachusetts Institute of Technology, Cambridge, MA 02139, USA Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur 721302, India Accepted 27 April 2001
Abstract Oxidation of strained-Si/relaxed-SiGe heterostructure grown by UHVCVD method using a rapid thermal processing technique in N2 O ambient is investigated. The electrical properties of the grown oxide have been characterized using a MOS structure. Hole con®nement in the SiGe layer at low ®eld is observed from the capacitance±voltage curve and this suggests that the strain in the initially strained Si epilayer is retained after oxidation. The experimental results are compared with simulation results obtained from a 1D Poisson solver. Dit and Qf =q values are estimated to be 3 1011 cm 2 eV 1 and 1:2 1011 cm 2 , respectively. These high values of Dit and negative Qf =q could possibly be due to Ge out diusion and pile up at the SiO2 /strained-Si interface. The oxide exhibits an excellent breakdown ®eld of 15 MV cm 1 . Ó 2001 Elsevier Science Ltd. All rights reserved. Keywords: N2 O oxidation; Strained-Si/relaxed-SiGe heterostructure
1. Introduction Continuous down scaling of Si-based devices becomes more challenging as we approach the sub-micron regime [1]. New alternatives must be sought to meet the ever-growing demand for higher speed. It has been shown that strained Si pseudomorphically grown on a relaxed SiGe virtual substrate can provide higher mobility for both holes [2] and electrons [3]. The mobility improvement using a tensile strained Si channel comes mainly from a reduction of the in-plane carrier eective mass and a reduction of intervalley scattering. However,
a high thermal budget processing step like oxidation can relax the strained Si epilayer by the formation of mis®t dislocations [4]. These defects are detrimental to the electronics properties of heterostructure devices. Various low thermal budget gate oxidation techniques have been used for strained Si. They include microwave N2 O plasma oxidation [5], conventional furnace oxidation [6] and LPCVD low temperature oxide [7]. Here we present the electrical properties of gate oxide grown on strained Si in a N2 O ambient using rapid thermal processing.
2. Experiment * Corresponding author. Tel.: +65-874-6473; fax: +65-7791103. E-mail address: [email protected] (W.K. Choi). 1 Singapore-MIT Alliance Fellow.
The strained-Si/relaxed-SiGe heterostructure was grown by UHVCVD. Fig. 1 shows the detailed material structure, the growth conditions and the corresponding band alignment. The chemical-mechanical polishing
0038-1101/01/$ - see front matter Ó 2001 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 0 1 ) 0 0 2 3 8 - 6
1946
C.S. Tan et al. / Solid-State Electronics 45 (2001) 1945±1949
simulated using a 1D Poisson solver assuming the fol dopant lowing parameters: oxide thickness 90 A, concentration 5 1014 cm 3 , remaining strained Si with conduction band offset 0:158 thickness 35 A, eV and valence band offset 0:152 eV from theoretical calculation [7].
3. Results and discussion
Fig. 1. Schematics of strained-Si/relaxed-SiGe heterostructure, growth conditions and its band alignment.
(CMP) step aimed at reducing the ®nal threading dislocation density and surface roughness on the strained Si caused by cross hatch [8]. Note that all epilayers were unintentionally doped to p type with a concentration of 1014 ±1015 cm 3 due to background dopant contamination being present in the UHVCVD growth chamber. The samples were cleaned by piranha (H2 SO4 : H2 O2 3:1) instead of a normal RCA SC1 cleaning step (H2 O:H2 O2 :NH4 OH 5:1:1) which is known to etch the thin strained Si epilayer [9]. Prior to loading the samples into the oxidation chamber, they received a 10 min diluted HF dip (49%HF:H2 O 1:50) leaving the strained Si surface both hydrophobic and hydrogenated. Rapid thermal oxidation (RTO) was carried out with an AST SHS 10 rapid thermal processor. The main advantages of this system are its high temperature ramp up rate (and hence a reduced thermal exposure to the strained Si) and a better control of thin oxide thickness. The system consists of a double-sided tungsten halogen lamp heater with independent top and bottom lamp bank control. A quartz reactor chamber is installed in a highly re¯ecting, gold-plated reactor block. The ramp up rate of the rapid thermal processor is 30°C s 1 while the ramp down rate is lower. The strained Si samples were placed on top of a 4 in. Si wafer. The temperature control was obtained with the help of a pyrometer. RTO was performed at 1000°C for 400 s in N2 O ambient. The from an ellipsooxide thickness was found to be 90 A meter. Immediately after oxidation, 250 nm of Al was evaporated on top of the oxide to form MOS capacitors with an area of 7:85 10 3 cm 2 . Ohmic contact was formed at the back with Al. The MOS capacitors were annealed in forming gas (H2 :N2 1:9) at 400°C for 5 min after metallization. Capacitance±voltage (C±V ) and current±voltage (I± V ) measurements were carried out using a HP4192A impedance analyzer and a HP4156A semiconductor parameter analyzer, respectively. The C±V curve was
Fig. 2 gives the normalized C±V curve of the MOS capacitor measured at 10 kHz. The high frequency C±V curve is well-formed and does not exhibit prominent hysteresis as it is swept into and out of accumulation. The plateau shape of the slow varying capacitance at low ®eld is due to hole con®nement at the strained-Si/relaxed-SiGe interface [10]. Note that the plateau shape in C±V curve is sensitive to the valence band oset at the strained-Si/relaxed-SiGe heterointerface. This valence band oset is reduced if the quality of the heterointerface is degraded due to the formation of mis®t dislocation (strain relaxation) [11]. The prominent plateau shape in the C±V curve in Fig. 2 indicates the presence of valence band oset at the strained-Si/relaxed-SiGe heterointerface even after oxidation. This implies that the heterointerface is not severely degraded after the oxidation step and that strain strained Si is not sigrelaxation in the remaining 35 A ni®cant. The ®xed oxide charge density, calculated from the ¯at band voltage shift, was found to be 1:2 1011 cm 2 . Fig. 3 gives the conductance±voltage (G±V ) characteristics of the MOS capacitor. The interface states density is estimated using the conductance method as [12]
Fig. 2. Experimental and theoretical C±V characteristics. Hole con®nement at low negative electric ®eld is clearly observed.
C.S. Tan et al. / Solid-State Electronics 45 (2001) 1945±1949
Fig. 3. Measured G±V characteristics of the MOS capacitor.
Dit
2:5 qA
Gp x
Fig. 4. Ge pro®le at the strained-Si/SiGe interface before and after oxidation.
;
1
max
where Gp =xmax is the peak value in a Gp =x vs x plot, x is the measurement frequency, A is the area of the MOS capacitor and q is the electronic charge. The Dit value was found to be 3 1011 cm 2 eV 1 . This high Dit value could be due to the ®nite amount of threading dislocation density that protrude into the strained Si layer from the relaxed SiGe substrate. Another contributing factor is Ge out diusion from the relaxed SiGe substrate and pile up at the SiO2 /strained-Si interface. It has been observed, in the case of oxidation of SiGe, that Ge atoms are ejected from the SiO2 region and pile up at the SiO2 /SiGe interface resulting in high interface state density and negative ®xed charge [13]. A simple model was used to estimate the amount of Ge atoms that out diuse into the strained Si epilayer. The Ge concentration at a particular temperature, c, as a function of time and distance is given by [14] c x; t
1947
c0 x d=2 p erf 2 2 Dt
erf
x d=2 p 2 Dt
;
2
where D is the diusivity of Ge in Si and is given by D D0 exp Ea =kT with D0 400 cm2 s 1 and Ea 4:7 eV [14]. The initial Ge concentration in the Si0:75 Ge0:25 cap layer (c0 ) is 25% and the Si0:75 Ge0:25 cap layer thickness (d) is 5 lm. Note that x 0 corresponds to the center of the Si0:75 Ge0:25 cap layer. We have simulated the Ge pro®le after oxidation assuming that Ge can diuse in®nitely. Fig. 4 shows the Ge pro®le at the strained-Si/relaxedSiGe interface before and after oxidation. The simulation shows that a signi®cant amount of Ge atoms have out diused into the strained Si layer under our oxida-
Fig. 5. Hole sheet density in the buried SiGe layer and the surface strained Si layer extracted from simulation.
tion condition. This gives rise to a high interface states density and a negative ®xed charge at the SiO2 /strainedSi interface as discussed above. The fact that the C±V characteristic from the simulation matches the experimental C±V curve reasonably well implies band alignment of the strained-Si/relaxedSiGe heterostructure. Fig. 5 is a plot showing the hole sheet density con®ned in the SiGe buried layer and in the strained Si surface layer as a function of gate bias of the MOS capacitor extracted from the simulation. These data are obtained from a simultaneous solution of Poisson's and Schr odinger's equations. 2 Referring to the band structure in Fig. 1, it is clear that there are two channels in which holes can reside
2
The simulation was performed at IIT Kharagpur, India.
1948
C.S. Tan et al. / Solid-State Electronics 45 (2001) 1945±1949
4. Conclusion We have shown that direct oxidation in N2 O ambient using rapid thermal processing can be used to grow a reasonably high quality gate oxide on a strained-Si/relaxed-SiGe heterostructure, without signi®cant strain relaxation. Methods that can suppress Ge out diusion should be pursued to enable the application of this oxidation technique in actual strained Si MOSFET fabrication. Acknowledgements Fig. 6. J ±E characteristic of the MOS capacitor. FN tunneling behavior is clearly seen for an electric ®eld higher than 9 MV cm 1 and oxide breakdown at 15 MV cm 1 .
The authors would like to thank the Singapore-MIT Alliance (SMA) for the ®nancial assistance and the provision of a research scholarship (T.C.S). References
when the gate is biased into the negative region. They are the buried relaxed SiGe layer and the surface strained Si layer with a valence band oset DEv 0:152 eV between them. At low negative ®eld (after the buried channel threshold VTH 0:74 V), the holes populate predominantly in the relaxed SiGe buried channel near the strained-Si/relaxed-SiGe interface as shown in Fig. 5. The eective gate capacitance (equivalent to the slope of hole density versus the gate voltage plot) is given by the series combination of the oxide capacitance, Cox and strained-Si layer capacitance. As the ®eld becomes more negative (after surface channel threshold VTS 1:46 V), the rate of increase of holes at the strained-Si/SiO2 interface will increase and eventually equal the rate of increase of holes in the relaxed SiGe layer. Beyond this point, the additional holes will be added predominantly to the accumulation layer at the strained-Si/SiO2 interface instead of the relaxed SiGe buried layer, with the eective gate capacitance approaching that of the oxide at suciently high negative ®eld. Therefore, the valence band oset can eectively con®ne holes and result in a hole buildup in the relaxed SiGe layer [15]. This is known as hole con®nement and it gives rise to the plateau in the C±V curve. The J ±E characteristic of the MOS capacitor, biased into accumulation, is given in Fig. 6. The leakage current density at low ®eld is low and a Fowler±Nordheim (FN) tunneling is clearly observed for an electric ®eld higher than 9 MV cm 1 . Our analysis on the FN mechanism gives an electron eective mass of 0.45m0 (m0 9:1 10 31 kg) and a barrier height of 3.0 eV. The oxide conductivity is in the order of 10 16 X 1 cm 1 at 5 MV cm 1 . The oxide is also found to be resistant to breakdown with a breakdown ®eld as high as 15 MV cm 1 . We attribute this high breakdown ®eld to the nature of N2 O oxidation [16].
[1] Taur Y, Buchanan DA, Chen W, Frank DJ, Ismail KE, Lo SH, Sai-Halasz GA, Viswanathan RG, Wann HJC, Wind SJ, Wong HS. CMOS scaling into the nanometer regime. Proc IEEE 1997;85(4):486±504. [2] Nayak DK, Chun SK. Low-®eld hole mobility of strained Si on (1 0 0) Si1 x Gex substrate. Appl Phys Lett 1994;64(19):2514±6. [3] Nelson SF, Ismail K, Chu JO, Meyerson BS. Room temperature electron mobility in strained Si/SiGe heterostructures. Appl Phys Lett 1993;63(3):367±9. [4] Samavedam SB, Taylor WJ, Grant JM, Smith JA, Tobin PJ, Dip A, Philips AM. Relaxation of strained Si layers grown on SiGe buers. J Vac Sci Technol B 1999;17(4): 1424±9. [5] Bera LK, Ray SK, Nayak DK, Usami N, Shiraki Y, Maiti CK. Electrical properties of oxides grown on strained Si using microwave N2 O plasma. Appl Phys Lett 1997;70(1):66±8. [6] Welser J, Hoyt JL, Gibbons JF. Growth and processing of relaxed-Si1 x Gex /strained-Si structures for metal-oxide semiconductor applications. Jpn J Appl Phys 1994;13: 2419±22. [7] Armstrong MA. Technology for SiGe heterostructurebased CMOS devices. PhD thesis, MIT, 1999. [8] Currie MT, Samavedam SB, Langdo TA, Leitz CW, Fitzgerald EA. Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemicalmechanical polishing. Appl Phys Lett 1998;72(14):1718± 20. [9] Jackson KM. Summary of wet etch rates for RCA, pirhanna, and hot phosphoric processing. Spring: MIT, 1999. [10] Welser JJ. The application of strained-silicon/relaxedsilicon germanium heterostructures to metal-oxide-semiconductor ®eld-eect transistors. PhD thesis, Stanford University, 1995. [11] Nayak DK. Physics and technology of GeSi quantum-well PMOSFETs. PhD thesis, University of California, Los Angeles, 1992.
C.S. Tan et al. / Solid-State Electronics 45 (2001) 1945±1949 [12] Schroder DK. Semiconductor material and device characterisation. New York: Wiley; 1990. [13] Ahn CG, Kang HS, Kwon YK, Lee SM, Ryum BR, Kang BK. Oxidation-induced traps near SiO2 /SiGe interface. J Appl Phys 1999;86(3):1542±7. [14] Klauk H, Jackson TN, Nelson SF, Chu JO. Thermal stability of undoped strained Si channel SiGe heterostructures. Appl Phys Lett 1996;68(14):1975±7.
1949
[15] Garone PM, Venkataraman V, Sturm JC. Hole con®nement in MOS-gated Gex Si1 x /Si heterostructures. IEEE Electron Dev Lett 1991;12(5):230±2. [16] Hwang H, Ting W, Kwong DL, Lee J. Electrical and reliability characteristics of submicron nMOSFET's with oxynitride gate dielectric prepared by rapid thermal oxidation in N2 O. 49th Annual Device Research Conference 1991, IVB_6-0_61.
N2O oxidation of strained-Si/relaxed-SiGe heterostructure grown by UHVCVD C.S. Tan a, W.K. Choi a,*,1, L.K. Bera a, K.L. Pey a,1, D.A. Antoniadis b,1, E.A. Fitzgerald b,1, M.T. Currie b, C.K. Maiti c a
c
Microelectronics Laboratory, Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, Singapore 117576, Singapore b Massachusetts Institute of Technology, Cambridge, MA 02139, USA Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur 721302, India Accepted 27 April 2001
Abstract Oxidation of strained-Si/relaxed-SiGe heterostructure grown by UHVCVD method using a rapid thermal processing technique in N2 O ambient is investigated. The electrical properties of the grown oxide have been characterized using a MOS structure. Hole con®nement in the SiGe layer at low ®eld is observed from the capacitance±voltage curve and this suggests that the strain in the initially strained Si epilayer is retained after oxidation. The experimental results are compared with simulation results obtained from a 1D Poisson solver. Dit and Qf =q values are estimated to be 3 1011 cm 2 eV 1 and 1:2 1011 cm 2 , respectively. These high values of Dit and negative Qf =q could possibly be due to Ge out diusion and pile up at the SiO2 /strained-Si interface. The oxide exhibits an excellent breakdown ®eld of 15 MV cm 1 . Ó 2001 Elsevier Science Ltd. All rights reserved. Keywords: N2 O oxidation; Strained-Si/relaxed-SiGe heterostructure
1. Introduction Continuous down scaling of Si-based devices becomes more challenging as we approach the sub-micron regime [1]. New alternatives must be sought to meet the ever-growing demand for higher speed. It has been shown that strained Si pseudomorphically grown on a relaxed SiGe virtual substrate can provide higher mobility for both holes [2] and electrons [3]. The mobility improvement using a tensile strained Si channel comes mainly from a reduction of the in-plane carrier eective mass and a reduction of intervalley scattering. However,
a high thermal budget processing step like oxidation can relax the strained Si epilayer by the formation of mis®t dislocations [4]. These defects are detrimental to the electronics properties of heterostructure devices. Various low thermal budget gate oxidation techniques have been used for strained Si. They include microwave N2 O plasma oxidation [5], conventional furnace oxidation [6] and LPCVD low temperature oxide [7]. Here we present the electrical properties of gate oxide grown on strained Si in a N2 O ambient using rapid thermal processing.
2. Experiment * Corresponding author. Tel.: +65-874-6473; fax: +65-7791103. E-mail address: [email protected] (W.K. Choi). 1 Singapore-MIT Alliance Fellow.
The strained-Si/relaxed-SiGe heterostructure was grown by UHVCVD. Fig. 1 shows the detailed material structure, the growth conditions and the corresponding band alignment. The chemical-mechanical polishing
0038-1101/01/$ - see front matter Ó 2001 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 0 1 ) 0 0 2 3 8 - 6
1946
C.S. Tan et al. / Solid-State Electronics 45 (2001) 1945±1949
simulated using a 1D Poisson solver assuming the fol dopant lowing parameters: oxide thickness 90 A, concentration 5 1014 cm 3 , remaining strained Si with conduction band offset 0:158 thickness 35 A, eV and valence band offset 0:152 eV from theoretical calculation [7].
3. Results and discussion
Fig. 1. Schematics of strained-Si/relaxed-SiGe heterostructure, growth conditions and its band alignment.
(CMP) step aimed at reducing the ®nal threading dislocation density and surface roughness on the strained Si caused by cross hatch [8]. Note that all epilayers were unintentionally doped to p type with a concentration of 1014 ±1015 cm 3 due to background dopant contamination being present in the UHVCVD growth chamber. The samples were cleaned by piranha (H2 SO4 : H2 O2 3:1) instead of a normal RCA SC1 cleaning step (H2 O:H2 O2 :NH4 OH 5:1:1) which is known to etch the thin strained Si epilayer [9]. Prior to loading the samples into the oxidation chamber, they received a 10 min diluted HF dip (49%HF:H2 O 1:50) leaving the strained Si surface both hydrophobic and hydrogenated. Rapid thermal oxidation (RTO) was carried out with an AST SHS 10 rapid thermal processor. The main advantages of this system are its high temperature ramp up rate (and hence a reduced thermal exposure to the strained Si) and a better control of thin oxide thickness. The system consists of a double-sided tungsten halogen lamp heater with independent top and bottom lamp bank control. A quartz reactor chamber is installed in a highly re¯ecting, gold-plated reactor block. The ramp up rate of the rapid thermal processor is 30°C s 1 while the ramp down rate is lower. The strained Si samples were placed on top of a 4 in. Si wafer. The temperature control was obtained with the help of a pyrometer. RTO was performed at 1000°C for 400 s in N2 O ambient. The from an ellipsooxide thickness was found to be 90 A meter. Immediately after oxidation, 250 nm of Al was evaporated on top of the oxide to form MOS capacitors with an area of 7:85 10 3 cm 2 . Ohmic contact was formed at the back with Al. The MOS capacitors were annealed in forming gas (H2 :N2 1:9) at 400°C for 5 min after metallization. Capacitance±voltage (C±V ) and current±voltage (I± V ) measurements were carried out using a HP4192A impedance analyzer and a HP4156A semiconductor parameter analyzer, respectively. The C±V curve was
Fig. 2 gives the normalized C±V curve of the MOS capacitor measured at 10 kHz. The high frequency C±V curve is well-formed and does not exhibit prominent hysteresis as it is swept into and out of accumulation. The plateau shape of the slow varying capacitance at low ®eld is due to hole con®nement at the strained-Si/relaxed-SiGe interface [10]. Note that the plateau shape in C±V curve is sensitive to the valence band oset at the strained-Si/relaxed-SiGe heterointerface. This valence band oset is reduced if the quality of the heterointerface is degraded due to the formation of mis®t dislocation (strain relaxation) [11]. The prominent plateau shape in the C±V curve in Fig. 2 indicates the presence of valence band oset at the strained-Si/relaxed-SiGe heterointerface even after oxidation. This implies that the heterointerface is not severely degraded after the oxidation step and that strain strained Si is not sigrelaxation in the remaining 35 A ni®cant. The ®xed oxide charge density, calculated from the ¯at band voltage shift, was found to be 1:2 1011 cm 2 . Fig. 3 gives the conductance±voltage (G±V ) characteristics of the MOS capacitor. The interface states density is estimated using the conductance method as [12]
Fig. 2. Experimental and theoretical C±V characteristics. Hole con®nement at low negative electric ®eld is clearly observed.
C.S. Tan et al. / Solid-State Electronics 45 (2001) 1945±1949
Fig. 3. Measured G±V characteristics of the MOS capacitor.
Dit
2:5 qA
Gp x
Fig. 4. Ge pro®le at the strained-Si/SiGe interface before and after oxidation.
;
1
max
where Gp =xmax is the peak value in a Gp =x vs x plot, x is the measurement frequency, A is the area of the MOS capacitor and q is the electronic charge. The Dit value was found to be 3 1011 cm 2 eV 1 . This high Dit value could be due to the ®nite amount of threading dislocation density that protrude into the strained Si layer from the relaxed SiGe substrate. Another contributing factor is Ge out diusion from the relaxed SiGe substrate and pile up at the SiO2 /strained-Si interface. It has been observed, in the case of oxidation of SiGe, that Ge atoms are ejected from the SiO2 region and pile up at the SiO2 /SiGe interface resulting in high interface state density and negative ®xed charge [13]. A simple model was used to estimate the amount of Ge atoms that out diuse into the strained Si epilayer. The Ge concentration at a particular temperature, c, as a function of time and distance is given by [14] c x; t
1947
c0 x d=2 p erf 2 2 Dt
erf
x d=2 p 2 Dt
;
2
where D is the diusivity of Ge in Si and is given by D D0 exp Ea =kT with D0 400 cm2 s 1 and Ea 4:7 eV [14]. The initial Ge concentration in the Si0:75 Ge0:25 cap layer (c0 ) is 25% and the Si0:75 Ge0:25 cap layer thickness (d) is 5 lm. Note that x 0 corresponds to the center of the Si0:75 Ge0:25 cap layer. We have simulated the Ge pro®le after oxidation assuming that Ge can diuse in®nitely. Fig. 4 shows the Ge pro®le at the strained-Si/relaxedSiGe interface before and after oxidation. The simulation shows that a signi®cant amount of Ge atoms have out diused into the strained Si layer under our oxida-
Fig. 5. Hole sheet density in the buried SiGe layer and the surface strained Si layer extracted from simulation.
tion condition. This gives rise to a high interface states density and a negative ®xed charge at the SiO2 /strainedSi interface as discussed above. The fact that the C±V characteristic from the simulation matches the experimental C±V curve reasonably well implies band alignment of the strained-Si/relaxedSiGe heterostructure. Fig. 5 is a plot showing the hole sheet density con®ned in the SiGe buried layer and in the strained Si surface layer as a function of gate bias of the MOS capacitor extracted from the simulation. These data are obtained from a simultaneous solution of Poisson's and Schr odinger's equations. 2 Referring to the band structure in Fig. 1, it is clear that there are two channels in which holes can reside
2
The simulation was performed at IIT Kharagpur, India.
1948
C.S. Tan et al. / Solid-State Electronics 45 (2001) 1945±1949
4. Conclusion We have shown that direct oxidation in N2 O ambient using rapid thermal processing can be used to grow a reasonably high quality gate oxide on a strained-Si/relaxed-SiGe heterostructure, without signi®cant strain relaxation. Methods that can suppress Ge out diusion should be pursued to enable the application of this oxidation technique in actual strained Si MOSFET fabrication. Acknowledgements Fig. 6. J ±E characteristic of the MOS capacitor. FN tunneling behavior is clearly seen for an electric ®eld higher than 9 MV cm 1 and oxide breakdown at 15 MV cm 1 .
The authors would like to thank the Singapore-MIT Alliance (SMA) for the ®nancial assistance and the provision of a research scholarship (T.C.S). References
when the gate is biased into the negative region. They are the buried relaxed SiGe layer and the surface strained Si layer with a valence band oset DEv 0:152 eV between them. At low negative ®eld (after the buried channel threshold VTH 0:74 V), the holes populate predominantly in the relaxed SiGe buried channel near the strained-Si/relaxed-SiGe interface as shown in Fig. 5. The eective gate capacitance (equivalent to the slope of hole density versus the gate voltage plot) is given by the series combination of the oxide capacitance, Cox and strained-Si layer capacitance. As the ®eld becomes more negative (after surface channel threshold VTS 1:46 V), the rate of increase of holes at the strained-Si/SiO2 interface will increase and eventually equal the rate of increase of holes in the relaxed SiGe layer. Beyond this point, the additional holes will be added predominantly to the accumulation layer at the strained-Si/SiO2 interface instead of the relaxed SiGe buried layer, with the eective gate capacitance approaching that of the oxide at suciently high negative ®eld. Therefore, the valence band oset can eectively con®ne holes and result in a hole buildup in the relaxed SiGe layer [15]. This is known as hole con®nement and it gives rise to the plateau in the C±V curve. The J ±E characteristic of the MOS capacitor, biased into accumulation, is given in Fig. 6. The leakage current density at low ®eld is low and a Fowler±Nordheim (FN) tunneling is clearly observed for an electric ®eld higher than 9 MV cm 1 . Our analysis on the FN mechanism gives an electron eective mass of 0.45m0 (m0 9:1 10 31 kg) and a barrier height of 3.0 eV. The oxide conductivity is in the order of 10 16 X 1 cm 1 at 5 MV cm 1 . The oxide is also found to be resistant to breakdown with a breakdown ®eld as high as 15 MV cm 1 . We attribute this high breakdown ®eld to the nature of N2 O oxidation [16].
[1] Taur Y, Buchanan DA, Chen W, Frank DJ, Ismail KE, Lo SH, Sai-Halasz GA, Viswanathan RG, Wann HJC, Wind SJ, Wong HS. CMOS scaling into the nanometer regime. Proc IEEE 1997;85(4):486±504. [2] Nayak DK, Chun SK. Low-®eld hole mobility of strained Si on (1 0 0) Si1 x Gex substrate. Appl Phys Lett 1994;64(19):2514±6. [3] Nelson SF, Ismail K, Chu JO, Meyerson BS. Room temperature electron mobility in strained Si/SiGe heterostructures. Appl Phys Lett 1993;63(3):367±9. [4] Samavedam SB, Taylor WJ, Grant JM, Smith JA, Tobin PJ, Dip A, Philips AM. Relaxation of strained Si layers grown on SiGe buers. J Vac Sci Technol B 1999;17(4): 1424±9. [5] Bera LK, Ray SK, Nayak DK, Usami N, Shiraki Y, Maiti CK. Electrical properties of oxides grown on strained Si using microwave N2 O plasma. Appl Phys Lett 1997;70(1):66±8. [6] Welser J, Hoyt JL, Gibbons JF. Growth and processing of relaxed-Si1 x Gex /strained-Si structures for metal-oxide semiconductor applications. Jpn J Appl Phys 1994;13: 2419±22. [7] Armstrong MA. Technology for SiGe heterostructurebased CMOS devices. PhD thesis, MIT, 1999. [8] Currie MT, Samavedam SB, Langdo TA, Leitz CW, Fitzgerald EA. Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemicalmechanical polishing. Appl Phys Lett 1998;72(14):1718± 20. [9] Jackson KM. Summary of wet etch rates for RCA, pirhanna, and hot phosphoric processing. Spring: MIT, 1999. [10] Welser JJ. The application of strained-silicon/relaxedsilicon germanium heterostructures to metal-oxide-semiconductor ®eld-eect transistors. PhD thesis, Stanford University, 1995. [11] Nayak DK. Physics and technology of GeSi quantum-well PMOSFETs. PhD thesis, University of California, Los Angeles, 1992.
C.S. Tan et al. / Solid-State Electronics 45 (2001) 1945±1949 [12] Schroder DK. Semiconductor material and device characterisation. New York: Wiley; 1990. [13] Ahn CG, Kang HS, Kwon YK, Lee SM, Ryum BR, Kang BK. Oxidation-induced traps near SiO2 /SiGe interface. J Appl Phys 1999;86(3):1542±7. [14] Klauk H, Jackson TN, Nelson SF, Chu JO. Thermal stability of undoped strained Si channel SiGe heterostructures. Appl Phys Lett 1996;68(14):1975±7.
1949
[15] Garone PM, Venkataraman V, Sturm JC. Hole con®nement in MOS-gated Gex Si1 x /Si heterostructures. IEEE Electron Dev Lett 1991;12(5):230±2. [16] Hwang H, Ting W, Kwong DL, Lee J. Electrical and reliability characteristics of submicron nMOSFET's with oxynitride gate dielectric prepared by rapid thermal oxidation in N2 O. 49th Annual Device Research Conference 1991, IVB_6-0_61.