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Nanostructures of pyramidal shape, technology and applications
Microelectronic Engineering 61–62 (2002) 675–680 www.elsevier.com / locate / mee
Nanostructures of pyramidal shape, technology and applications Irina Kleps*, Anca Angelescu, Marioara Avram, Mihaela Miu, Monica Simion National Institute for Research and Development in Microtechnologies ( IMT —Bucharest), P.O. Box 38 -160, 72225 Bucharest, Romania
Abstract Different nanostructures of pyramidal or conical shape, such as silicon (Si), dielectric / Si, metal / Si, dielectric / metal / Si, dielectric / metal / dielectric / Si, were prepared using standard semiconductor devices processes: dry and wet etching, thin film deposition, and photolithography. Test devices arrays with pyramidal tips of 2 3 2 mm 2 and 8 3 8 mm 2 base area and 5–250 nm top radius of the tip were realised. Each array is constituted from many types of test devices with different tips number and distances between them. We have investigated these nanostructures for vacuum microelectronics devices and as nanoelectrodes for cyclic voltammetry pollution control measurements. 2002 Elsevier Science B.V. All rights reserved. Keywords: Pyramidal nanostructures; Tips; Silicon nanoelectrodes; Micromachining
1. Introduction Pyramidal structures were extensively used especially for field emitter applications [1–6]. Different technologies were developed in order to obtain sharper and sharper pyramidal or conical emitters in order to improve their field emitter properties. Recently, such structures realised by Si or Si 3 N 4 micromachining technologies were used for nanoelectrode array fabrication [7–10].
2. Experiments for field emitter array preparation Silicon emitters arrays of various geometrical characteristics were realised using different micromachining technologies. These techniques are well known and previously described in some of our papers [11,12]; the field emitter array preparation is briefly presented. Different technological processes were used: (a) by a combined dry–wet etching process (Fig. 1) [11]; (b) using porous silicon as sacrificial layer (Figs. 2 and 3) [12]; (c) Si or Si 3 N 4 dry etching (Fig. 4). The emitter * Corresponding author. Tel.: 1 40-1-4908412; fax: 1 40-1-4908238. E-mail address: [email protected] (I. Kleps). 0167-9317 / 02 / $ – see front matter PII: S0167-9317( 02 )00502-6
2002 Elsevier Science B.V. All rights reserved.
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I. Kleps et al. / Microelectronic Engineering 61 – 62 (2002) 675 – 680
Fig. 1. Si emitters arrays obtained by dry (a), wet (b) etching processes (r 5 2 mm).
geometry was modified by varying the technological parameters like: etch rate, selectivity and surface morphology. Silicon emitters were covered with various materials in order to improve their field emission properties. The field emission properties of some coating films, such as diamond, silicon carbide and porous silicon were evaluated [11]. It can be observed that the micromachined surfaces obtained by dry etching technology are more smooth than the surfaces obtained by wet etching solutions; the apex radius of these tips was between 5 and 20 nm, comparatively with the wet etching apex radius of 30–200 nm.
I. Kleps et al. / Microelectronic Engineering 61 – 62 (2002) 675 – 680
Fig. 2. Technological process for Si emitter array realised using porous silicon as sacrificial layer.
Fig. 3. Silicon emitters array realised using porous silicon as sacrificial layer.
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Fig. 4. Silicon emitter array realised by dry etching process.
3. Nanoelectrode arrays for electrochemical measurements Based on the previous experience, regarding the pyramidal / conical structure fabrication, we have realized nanoelectrode structures on the same kind of structures. Different nanoelectrode array geometry with electrodes of pyramidal shape of 2 3 2 mm 2 and 8 3 8 mm 2 base area and 50–250 nm top radius were realised. Each array is constituted from many types of test devices with different nanoelectrode number and distances. The substrate material was a p-type (100) silicon wafer of 6–10 V cm electrical resistivity. Pyramidal structures were realized by Si etching through a 0.6 mm silicon dioxide mask. An additional oxidation process was applied in order to sharpen the structure. After etching, the substrate was again oxidized to assure the isolation of the electrode layer from the semiconducting substrate. The electrode material was deposited on the whole Si surface. We have used either gold (Au) film (200 nm) prepared by evaporation method, either platinum (Pt) film (100–300 nm) prepared by metal organic chemical vapour deposition (MOCVD) using platinum bisacetonate as precursor. The insulating material was organic polymer or inorganic films SiO 2 or SiO 2 / Si 3 N 4 sandwich. A short UV exposition process was performed without any mask in order to release the top of the electrodes. Two kinds of such structures with Au and Pt were realised (Fig. 5). Finally, contact wires were bonded and the structures were isolated with siliconic resin. The described SiO 2 / Pt / Si 3 N 4 and SiO 2 /Au / SiO 2 nanostructures have important applications in the electrochemical system fabrication for pollution control and biomedical measurements. A variable
I. Kleps et al. / Microelectronic Engineering 61 – 62 (2002) 675 – 680
679
Fig. 5. Gold (a) and platinum (b) pyramidal electrodes were microfabricated on Si or on Si 3 N 4 / Si substrates.
electrode number and position in the array related to different applications represent the main advantage of these new nano / microelectrode arrays.
4. Conclusions In this paper we presented the technological processes to obtain pyramidal nanostructures for two different applications: field emitters arrays and nanoelectrode arrays. These metal / dielectric nanostructures realised by standard Si technology processes are more suitable than similar self organised nanostructures, in order to be used as nanoelectrode arrays in the electrochemical systems. Different materials for dielectric / metal nanostructures can be used.
Acknowledgements The electrode array conception and design were done by the National Institute for Research and Development in Microtechnologies (IMT—Bucharest). Some of the technological processes were
680
I. Kleps et al. / Microelectronic Engineering 61 – 62 (2002) 675 – 680
effectuated at the Institute of Microtechnology Mainz (IMM) under the project No. HPRI-CT-199900023 funded under the IHP-Programme of the European Commission. The authors grateful acknowledge the contribution of Eng. Stefan Schmitt (IMM, Mainz, Germany) for his assistance with the Pt electrode fabrication.
References [1] W.B. Choi, J.J. Cuomo, V.V. Zhirnov, A.F. Myers, J.J. Hren, Field emission from silicon and molybdenum tips coated with diamond powder by dielectrophoresis, Appl. Phys. Lett. 68 (1996) 720. [2] Y. Kim, E. Choi, S. Kang, G. Cho, Computer-controlled fabrication of ultra-sharp tungsten tips, J. Vac. Sci. Technol. B 16 (4) (1998) 2079. [3] I. Brodie, C.A. Spindt, Vacuum microelectronics, Adv. Electron. Electron Phys. 83 (1992) 1–106. [4] H.H. Busta, Review: vacuum microelectronics—1992, J. Micromech. Microeng. 2 (1992) 43. [5] S. Iannazzo, A survey of the present status of vacuum microelectronics, Solid State Electron. 36 (3) (1993) 301–320. [6] R.G. Musket, Sharpening of field emitter tips using high-energy ions, US Pat. 5993281, 30 November 1999. [7] I. Kleps, A. Angelescu, R. Vasilco, D. Dascalu, New micro- and nanoelectrode array for biomedical applications, Biomed. Microdevices 3 (1) (2001) 29–33. [8] I. Kelps, A. Angelescu, M. Miu, Measurement systems based on metal / dielectric nanostructures for electrochemical analyses, EMRS 2001 Spring Meeting, Strasbourg, 2001. [9] I. Kleps, A. Angelescu, M. Miu, M. Avram, M. Simion, Technology of silicon nano- and microelectrode arrays for pollution control, to be presented at CAS 2001. [10] M. Avram, A. Angelescu, I. Kleps, M. Miu, A. Popescu, Fast scan cyclic voltammetry simulation for silicon nanoelectrodes, to be presented at CAS 2001. [11] I. Kleps, A. Angelescu, N. Samfirescu, A. Gil, A. Correia, Study of porous silicon, silicon carbide and DLC coated field field emitters for pressure sensor application, Solid State Electron. 45 (2001) 997–1001. [12] I. Kleps, G. Banoiu, V. Avramescu, A. Angelescu, Field emitter arrays technologies and materials, in: Proceedings of the International Conference on Semiconductors (CAS‘98), Sinaia, Vol. 1, 7–11 October 1998, pp. 365–368.
Nanostructures of pyramidal shape, technology and applications Irina Kleps*, Anca Angelescu, Marioara Avram, Mihaela Miu, Monica Simion National Institute for Research and Development in Microtechnologies ( IMT —Bucharest), P.O. Box 38 -160, 72225 Bucharest, Romania
Abstract Different nanostructures of pyramidal or conical shape, such as silicon (Si), dielectric / Si, metal / Si, dielectric / metal / Si, dielectric / metal / dielectric / Si, were prepared using standard semiconductor devices processes: dry and wet etching, thin film deposition, and photolithography. Test devices arrays with pyramidal tips of 2 3 2 mm 2 and 8 3 8 mm 2 base area and 5–250 nm top radius of the tip were realised. Each array is constituted from many types of test devices with different tips number and distances between them. We have investigated these nanostructures for vacuum microelectronics devices and as nanoelectrodes for cyclic voltammetry pollution control measurements. 2002 Elsevier Science B.V. All rights reserved. Keywords: Pyramidal nanostructures; Tips; Silicon nanoelectrodes; Micromachining
1. Introduction Pyramidal structures were extensively used especially for field emitter applications [1–6]. Different technologies were developed in order to obtain sharper and sharper pyramidal or conical emitters in order to improve their field emitter properties. Recently, such structures realised by Si or Si 3 N 4 micromachining technologies were used for nanoelectrode array fabrication [7–10].
2. Experiments for field emitter array preparation Silicon emitters arrays of various geometrical characteristics were realised using different micromachining technologies. These techniques are well known and previously described in some of our papers [11,12]; the field emitter array preparation is briefly presented. Different technological processes were used: (a) by a combined dry–wet etching process (Fig. 1) [11]; (b) using porous silicon as sacrificial layer (Figs. 2 and 3) [12]; (c) Si or Si 3 N 4 dry etching (Fig. 4). The emitter * Corresponding author. Tel.: 1 40-1-4908412; fax: 1 40-1-4908238. E-mail address: [email protected] (I. Kleps). 0167-9317 / 02 / $ – see front matter PII: S0167-9317( 02 )00502-6
2002 Elsevier Science B.V. All rights reserved.
676
I. Kleps et al. / Microelectronic Engineering 61 – 62 (2002) 675 – 680
Fig. 1. Si emitters arrays obtained by dry (a), wet (b) etching processes (r 5 2 mm).
geometry was modified by varying the technological parameters like: etch rate, selectivity and surface morphology. Silicon emitters were covered with various materials in order to improve their field emission properties. The field emission properties of some coating films, such as diamond, silicon carbide and porous silicon were evaluated [11]. It can be observed that the micromachined surfaces obtained by dry etching technology are more smooth than the surfaces obtained by wet etching solutions; the apex radius of these tips was between 5 and 20 nm, comparatively with the wet etching apex radius of 30–200 nm.
I. Kleps et al. / Microelectronic Engineering 61 – 62 (2002) 675 – 680
Fig. 2. Technological process for Si emitter array realised using porous silicon as sacrificial layer.
Fig. 3. Silicon emitters array realised using porous silicon as sacrificial layer.
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I. Kleps et al. / Microelectronic Engineering 61 – 62 (2002) 675 – 680
Fig. 4. Silicon emitter array realised by dry etching process.
3. Nanoelectrode arrays for electrochemical measurements Based on the previous experience, regarding the pyramidal / conical structure fabrication, we have realized nanoelectrode structures on the same kind of structures. Different nanoelectrode array geometry with electrodes of pyramidal shape of 2 3 2 mm 2 and 8 3 8 mm 2 base area and 50–250 nm top radius were realised. Each array is constituted from many types of test devices with different nanoelectrode number and distances. The substrate material was a p-type (100) silicon wafer of 6–10 V cm electrical resistivity. Pyramidal structures were realized by Si etching through a 0.6 mm silicon dioxide mask. An additional oxidation process was applied in order to sharpen the structure. After etching, the substrate was again oxidized to assure the isolation of the electrode layer from the semiconducting substrate. The electrode material was deposited on the whole Si surface. We have used either gold (Au) film (200 nm) prepared by evaporation method, either platinum (Pt) film (100–300 nm) prepared by metal organic chemical vapour deposition (MOCVD) using platinum bisacetonate as precursor. The insulating material was organic polymer or inorganic films SiO 2 or SiO 2 / Si 3 N 4 sandwich. A short UV exposition process was performed without any mask in order to release the top of the electrodes. Two kinds of such structures with Au and Pt were realised (Fig. 5). Finally, contact wires were bonded and the structures were isolated with siliconic resin. The described SiO 2 / Pt / Si 3 N 4 and SiO 2 /Au / SiO 2 nanostructures have important applications in the electrochemical system fabrication for pollution control and biomedical measurements. A variable
I. Kleps et al. / Microelectronic Engineering 61 – 62 (2002) 675 – 680
679
Fig. 5. Gold (a) and platinum (b) pyramidal electrodes were microfabricated on Si or on Si 3 N 4 / Si substrates.
electrode number and position in the array related to different applications represent the main advantage of these new nano / microelectrode arrays.
4. Conclusions In this paper we presented the technological processes to obtain pyramidal nanostructures for two different applications: field emitters arrays and nanoelectrode arrays. These metal / dielectric nanostructures realised by standard Si technology processes are more suitable than similar self organised nanostructures, in order to be used as nanoelectrode arrays in the electrochemical systems. Different materials for dielectric / metal nanostructures can be used.
Acknowledgements The electrode array conception and design were done by the National Institute for Research and Development in Microtechnologies (IMT—Bucharest). Some of the technological processes were
680
I. Kleps et al. / Microelectronic Engineering 61 – 62 (2002) 675 – 680
effectuated at the Institute of Microtechnology Mainz (IMM) under the project No. HPRI-CT-199900023 funded under the IHP-Programme of the European Commission. The authors grateful acknowledge the contribution of Eng. Stefan Schmitt (IMM, Mainz, Germany) for his assistance with the Pt electrode fabrication.
References [1] W.B. Choi, J.J. Cuomo, V.V. Zhirnov, A.F. Myers, J.J. Hren, Field emission from silicon and molybdenum tips coated with diamond powder by dielectrophoresis, Appl. Phys. Lett. 68 (1996) 720. [2] Y. Kim, E. Choi, S. Kang, G. Cho, Computer-controlled fabrication of ultra-sharp tungsten tips, J. Vac. Sci. Technol. B 16 (4) (1998) 2079. [3] I. Brodie, C.A. Spindt, Vacuum microelectronics, Adv. Electron. Electron Phys. 83 (1992) 1–106. [4] H.H. Busta, Review: vacuum microelectronics—1992, J. Micromech. Microeng. 2 (1992) 43. [5] S. Iannazzo, A survey of the present status of vacuum microelectronics, Solid State Electron. 36 (3) (1993) 301–320. [6] R.G. Musket, Sharpening of field emitter tips using high-energy ions, US Pat. 5993281, 30 November 1999. [7] I. Kleps, A. Angelescu, R. Vasilco, D. Dascalu, New micro- and nanoelectrode array for biomedical applications, Biomed. Microdevices 3 (1) (2001) 29–33. [8] I. Kelps, A. Angelescu, M. Miu, Measurement systems based on metal / dielectric nanostructures for electrochemical analyses, EMRS 2001 Spring Meeting, Strasbourg, 2001. [9] I. Kleps, A. Angelescu, M. Miu, M. Avram, M. Simion, Technology of silicon nano- and microelectrode arrays for pollution control, to be presented at CAS 2001. [10] M. Avram, A. Angelescu, I. Kleps, M. Miu, A. Popescu, Fast scan cyclic voltammetry simulation for silicon nanoelectrodes, to be presented at CAS 2001. [11] I. Kleps, A. Angelescu, N. Samfirescu, A. Gil, A. Correia, Study of porous silicon, silicon carbide and DLC coated field field emitters for pressure sensor application, Solid State Electron. 45 (2001) 997–1001. [12] I. Kleps, G. Banoiu, V. Avramescu, A. Angelescu, Field emitter arrays technologies and materials, in: Proceedings of the International Conference on Semiconductors (CAS‘98), Sinaia, Vol. 1, 7–11 October 1998, pp. 365–368.