- Email: [email protected]
SiO2 interface
ARTICLE IN PRESS
Physica E 38 (2007) 1–5 www.elsevier.com/locate/physe
Nanostructuring Si surface and Si/SiO2 interface using porous-alumina-on-Si template technology. Electrical characterization of Si/SiO2 interface M. Kokonou, A.G. Nassiopoulou IMEL/NCSR Demokritos, Terma Patriarchou Grigoriou, Aghia Paraskevi, 153 10 Athens, Greece Available online 16 December 2006
Abstract In this work, anodic porous alumina thin films with pores in the nanometer range are grown on silicon by electrochemistry and are used as masking material for the nanopatterning of the silicon substrate. The pore diameter and density are controlled by the electrochemical process. Through the pores of the alumina film chemical oxidation of the silicon substrate is performed, leading to the formation of regular arrays of well-separated stoichiometric silicon dioxide nanodots on silicon, with a density following the alumina pores density and a diameter adjustable by adjusting the chemical oxidation time. The alumina film is dissolved chemically after the SiO2 nanodots growth, revealing the arrays of silicon dioxide dots on silicon. In a next step, the nanodots are also removed, leaving a nanopatterned bare silicon surface with regular arrays of nanopits at the footprint of each nanodot. This silicon surface structuring finds interesting applications in nanoelectronics. One such application is in silicon nanocrystals memories, where the structuring of the oxidized silicon surface leads to the growth of discrete silicon nanocrystals of uniform size. In this work, we examine the electrical quality of the Si/SiO2 interface of a nanostructured oxidized silicon surface fabricated as above and we find that it is appropriate for electronic applications (an interface trap density below 1–3 1010 eV1 cm2 is obtained, indicative of the high quality of the thermal silicon oxide). r 2007 Elsevier B.V. All rights reserved. PACS: 82.45 h; 81.16Rf; 81.16 Pr; 61.46w; 68.65 K Keywords: Porous alumina; Nanostructuring; Nanopatterning; Si/SiO2 interface
1. Introduction Nanopatterned oxidized silicon surfaces find important applications in nanoelectronics and self-assembly of quantum dots [1–4]. Conventional techniques used in this respect are (a) electron beam lithography combined with etching and (b) ion beam milling using focused ion beams. Both of these techniques offer accuracy, repeatability and flexibility in the design, but are costly and relatively slow. Alternatively, when periodic structures are needed on silicon, template technology by electrochemistry may be used, which may be applied on large areas, and is consequently very fast and low-cost technique. Anodic alumina thin films on silicon may be used in this respect. Corresponding author. Tel.: +302106503137; fax: +302106511723.
E-mail address: [email protected] (M. Kokonou). URL: http://www.imel.demokritos.gr. 1386-9477/$ - see front matter r 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.physe.2006.12.008
These films are fabricated by anodization of aluminum films on a silicon substrate and, under specific electrochemical conditions, they show regular vertical pores distributed in the plane in a hexagonal close-packed (HCP) structure. The size and density of pores is adjustable by changing the electrochemical conditions used [5–11]. In a previous work [12,13], the authors developed a technology using very thin anodic porous alumina films on silicon for fabricating two-dimensional arrays of SiO2 quantum dots on silicon by chemical oxidation of the silicon substrate through the pores. The size of the dots depends on the oxidation time and chemical solution used and the dots material is stoichiometric SiO2. Since the dots are grown by consuming silicon from the substrate, the remaining silicon surface if we remove the dots shows the negative pattern of that of the dots-containing surface (arrays of pits on Si following the pore distribution).
ARTICLE IN PRESS 2
M. Kokonou, A.G. Nassiopoulou / Physica E 38 (2007) 1–5
In this work, we used capacitance–voltage (C–V) techniques to characterize the Si/SiO2 interface in two cases: (a) In samples with the two-dimensional arrays of SiO2 dots fabricated as above and further oxidized at high temperature in order to grow 6-nm-thick thermal silicon oxide in the areas between the dots and at the same time to increase the vertical thickness of the dots. (b) In samples as in (a) from which the SiO2 dots were removed and the samples were then oxidized under the same conditions as above so as to fabricate a 6-nmthick silicon oxide film of homogeneous thickness on all the patterned silicon surface. From C–V curves on fabricated capacitors, the density of interface states was calculated. 2. Experimental results and discussion 2.1. Sample fabrication The process for sample fabrication is illustrated in more detail in Fig. 1. An Al film, 500-nm thick, was first grown on a p-type silicon wafer by electron gun evaporation. An ohmic contact was formed on the backside of the wafer and the sample was anodized in sulfuric acid aqueous solution, 6% in volume, under a constant voltage of 20 V at room temperature. Under these conditions, a porous alumina thin film was grown on silicon, containing vertical pores ordered on the surface in HCP arrays. The average diameter of the pores was 16 nm, while their density was about 6 1010 pores/cm2. Their length was that of the alumina film thickness. Following the current–voltage anodization curve, the time at which the Al films was fully consumed was determined and anodization was further left to proceed for few more seconds so as the oxygen of the electrolyte started to diffuse into the Si substrate and to oxidize it locally, forming SiO2 nanoislands (dots) at each pore tip (Fig. 1(b)). The diameter of these dots was in general larger than the pore diameter due to isotropic lateral oxidation underneath the alumina film. By dissolving the alumina template at the end of the anodization process in phosphoric acid aqueous solution 5% in weight, a silicon surface with two-dimensional arrays of SiO2 dots on top was obtained (Fig. 1(c)). Dot distribution on the silicon surface followed the hexagonal structure of the alumina template. This is illustrated in Fig. 2(a), where a top view AFM image of the SiO2 nanodots is shown. In Fig. 2(b) we see an AFM image of the nanostructured bare silicon surface after chemical dissolution of the SiO2 nanodots, where the arrays of nanopits at the footprint of the removed nanodots are identified. Two different patterned oxidized silicon samples were then fabricated: (a) Sample S1 (structure shown in Fig. 1(d)): This sample was composed of the silicon substrate with SiO2 dots,
Fig. 1. Process flow for the fabrication of a nanopatterned silicon surface. An Al film is deposited on Si (a), which is fully transformed into porous alumina by anodization (b). After full Al consumption, anodization proceeds further for a short time in order to chemically oxidize the silicon surface at each pore tip, thus growing SiO2 nanodots of diameter slightly larger than the pore diameter (b). The alumina film is then removed (c) and the remaining structure contains two-dimensional arrays of SiO2 nanodots on Si. This structure may be oxidized as is (d) or after removal of the SiO2 dots (e). After step (e) the oxidized structure has an undulated silicon oxide layer of homogeneous thickness on top (f).
which was then further oxidized in a high-temperature furnace at 850 1C for 17 min. Under these oxidation conditions, a silicon oxide layer, 6-nm thick, is in general grown on a bare Si surface of p-type silicon, (1 0 0) oriented, with resistivity in the range of 1–10 O cm. This film was grown in-between the dots, while under the dots the oxidation proceeds more slowly than on the bare Si area. The maximum height of the dots in the vertical direction was about 10 nm. An annealing step at 920 1C for 30 min followed the oxidation. (b) Sample S2 (structure shown in Fig. 1(f)): In this case, the dots on the silicon surface were dissolved in dilute
ARTICLE IN PRESS M. Kokonou, A.G. Nassiopoulou / Physica E 38 (2007) 1–5
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[12]. The density of the dots under the above fabrication conditions for samples S1 and S2 was about 4–5 1010 cm2, their lateral diameter on the silicon surface was in the range of 35–45 nm, while their height was E10 nm. The above samples S1 and S2 were used to fabricate aluminum-gated MOS capacitors. Al was deposited on the oxidized silicon surface and patterned in order to define the capacitor area (104 cm2). The samples were subjected to forming gas annealing (N2/H2 environment) in an open furnace at 420 1C for 20 min. They were then characterized by double sweep C–V measurements at frequencies of 1 MHz, 100, 10 and 1 kHz. Quasi-static current–voltage measurements were also performed on the samples and the interface trap densities were calculated by the high–low frequency method. 2.2. Electrical characterization of Si/SiO2 interfaces
Fig. 2. AFM top view images showing a silicon surface with arrays of SiO2 dots (a) or pits left on the surface after the chemical dissolution of the dots (b).
HF and a bare silicon surface with pits following the dots position was obtained (Fig. 1(e)). The depth of the pits was 2–3 nm. The wafers were then oxidized so as to obtain a thin undulated silicon oxide layer, 6-nmthick, on the undulated silicon surface (oxidation was done also at 850 1C for 17 min). An annealing step at 920 1C for 30 min followed the oxidation. Samples with SiO2 nanoislands were characterized by atomic force microscopy (AFM) and X-ray photoelectron spectroscopy (XPS) and results were published elsewhere
As it was mentioned before, both samples S1 and S2 were oxidized under the same conditions that give a 6-nm-thick oxide film on bare Si. In sample S2, this silicon oxide layer was homogeneous in thickness and followed the patterned silicon topography. In sample S1, we expected to get areas with 6-nm-thick oxide between the islands and areas with thicker oxide in the initial island areas. Both the electrochemical and the thermal oxides were stoichiometric SiO2, as verified experimentally elsewhere [13]. In both cases of samples S1 and S2, the interface between the silicon substrate and the oxide was scalloped. Since in general steps the silicon surface may introduce stresses that increase the interface states, in this work we investigated the electronic quality of the scalloped Si/SiO2 interface of the above samples, in order to verify if the structures are appropriate for applications in electronic devices. The interface trap density was calculated using the wellknown high–low frequency method [13–16]. Double sweep C–V measurements were performed at four different frequencies, namely at 1 MHz, 100, 10 and 1 KHz. Fig. 3 shows C–V curves for samples S1 (Fig. 3(a)) and S2 (Fig. 3(b)). We see that in both cases all C–V curves coincide perfectly between them at all frequencies and no hysteresis effects are observed. This is a first indication of the high quality of the oxide films. Quasi-static current–voltage measurements were also performed and they were compared with the high frequency C–V curves, as shown in Fig. 4. Again, 4a corresponds to sample S1 and 4b to sample S2. We see that in both cases the offset corresponding to interface traps is negligible. Using detailed calculations we estimated the interface traps density and the results are shown in Fig. 5. The interface traps density near midgap was about 2.7 1010 eV1 cm2 in the case of sample S1 containing the silicon oxide dots (Fig. 5(a)), while it was about 1.7 1010 eV1 cm2 in the case of sample S2 with the homogeneous SiO2 thickness (Fig. 5(b)). The reference of the energy in these diagrams is the highest level of the valence band. These densities are certainly
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Fig. 3. C–V curves of samples S1 (a) and S2 (b) at 4 different frequencies. The coincidence of all 4 curves in each case is indicative of the high quality of the oxides in both cases.
Fig. 4. High-frequency and quasi-static (low-frequency) C–V curves from samples S1 (a) and S2 (b). No hysteresis is observed, indicative of the low density of interface traps.
Fig. 5. Density of interface states in the cases of sample S1 (a) and S2 (b) as a function of energy.
within the range of interface traps densities of the highest quality flat Si/SiO2 interfaces used in microelectronics. This means that any stress effects due to interface undulations were minimized by the high-temperature annealing and they did not affect the quality of the interface. The Al annealing in N2–H2 ambient was also an important step for minimizing the interface trap density. From the high-frequency C–V measurements, we estimated the equivalent oxide thickness in both cases of
samples S1 and S2, using the equation: tox ¼
o A , C ox
where tox is the equivalent oxide thickness, e is the dielectric constant of SiO2, eo the dielectric constant of vacuum, A the capacitor area and Cox the capacitance of the structure in accumulation. The measured Cox was 56.9 pF for sample S1 containing the SiO2 nanodots, while it was 57.6 pF in the
ARTICLE IN PRESS M. Kokonou, A.G. Nassiopoulou / Physica E 38 (2007) 1–5
case of sample S2 with the undulated oxide of homogeneous thickness. This result is unexpected, since it gives an equivalent oxide thickness of a capacitor with a flat SiO2 surface equal to tox1 ¼ 6.1 nm for sample S1 and tox2 ¼ 6.3 nm for sample S2. Taking into account that sample S1 contained already the SiO2 nanodots before oxidation, it was expected that a thicker equivalent oxide would have been grown on the surface of this sample. Although it is well known that the oxidation rate is different on an already oxidized surface compared with a non-oxidized one, the total oxide thickness effect was expected to be higher under the same oxidation conditions if an oxide of a certain thickness was already there. However, it seems from our results that the oxidation process is more complicated in the presence of the nanodots and an accurate simulation taking into account the ellipsoidal shape of the nanodots and possible strains/ stresses at the nanodots interface with silicon is needed. 4. Conclusions Nanopatterning of a silicon surface was performed by growing two-dimensional arrays of SiO2 dots on silicon through an anodic porous alumina thin film and oxidizing the resulting samples after chemical etching of the alumina film. Two kinds of samples with an undulated Si/SiO2 interface were fabricated. In the first sample, the SiO2 dots were left on the silicon surface, thus an oxide structure of inhomogeneous thickness was grown after oxidation, while in the second case the dots were removed before oxidation and an undulated SiO2 film of homogeneous thickness on all the Si surface was grown. In both cases C–V
5
measurements revealed a high electronic quality scalloped Si/SiO2 interface with a low density of interface traps, adequate for applications in nanoelectronic devices.
References [1] L. Vescan, T. Stoica, B. Hollander, A. Nassiopoulou, A. Olzierski, I. Raptis, I. Sutter, Appl. Phys. Lett. 82 (20) (2003) 3517. [2] E.S. Kim, N. Usami, Y. Shiraki, Appl. Phys. Lett. 72 (13) (1998) 1617. [3] I. Berbezier, A. Karmous, A. Ronda, T. Stoica, L. Vescan, R. Geurt, A. Olzierski, E. Tsoi, A.G. Nassiopoulou, J. Phys.: Conf. Ser. 10 (2005) 73. [4] A. Karmous, I. Berbezier, A. Ronda, Phys. Rev. B 73 (2006) 075323. [5] Y. Nitta, M. Shibata, K. Fujita, M. Ischikawa, Surf Sci. 462 (2000) L587. [6] A.P. Li, F. Mu¨ller, A. Briner, K. Nielsch, U. Go¨sele, J. Appl. Phys. 84 (11) (1998) 6023. [7] S. Lazarouk, S. Katsouba, A. Demianovich, V. Stanovski, S. Voitech, V. Vysotski, V. Ponomar, Microl. Eng. 50 (2000) 321. [8] D.H. Kuo, B.Y. Chung, R.J. Wu, Thin Sol. Films 398 (2001) 35. [9] S.Z. Chu, K. Wada, S. Inoue, S. Todoroki, J. Electrochem. Soc. 149 (7) (2002) B321. [10] M. Kokonou, A.G. Nassiopoulou, A. Travlos, Mater. Sci. Eng. B101 (2003) 65. [11] Y.F. Mei, X.L. Wu, X.F. Shao, G.S. Huang, G.G. Siu, Physics Lett A 309 (2003) 109. [12] M. Kokonou, A.G. Nassiopoulou, K.P. Giannakopoulos, Nanotechnology 16 (2005) 103. [13] M. Kokonou, A.G. Nassiopoulou, K.P. Giannakopoulos, A. Travlos, T. Stoica, S. Kennou, Nanotechnology 17 (2006) 2146. [14] D.K. Schroder, Semiconductor Material and Device Characterization, second ed, Wiley, New York, 1998. [15] E.H. Nicollian, J.R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology, Wiley, 1981. [16] M. Schulz, Microelectron. Eng. 40 (1998) 113.
Physica E 38 (2007) 1–5 www.elsevier.com/locate/physe
Nanostructuring Si surface and Si/SiO2 interface using porous-alumina-on-Si template technology. Electrical characterization of Si/SiO2 interface M. Kokonou, A.G. Nassiopoulou IMEL/NCSR Demokritos, Terma Patriarchou Grigoriou, Aghia Paraskevi, 153 10 Athens, Greece Available online 16 December 2006
Abstract In this work, anodic porous alumina thin films with pores in the nanometer range are grown on silicon by electrochemistry and are used as masking material for the nanopatterning of the silicon substrate. The pore diameter and density are controlled by the electrochemical process. Through the pores of the alumina film chemical oxidation of the silicon substrate is performed, leading to the formation of regular arrays of well-separated stoichiometric silicon dioxide nanodots on silicon, with a density following the alumina pores density and a diameter adjustable by adjusting the chemical oxidation time. The alumina film is dissolved chemically after the SiO2 nanodots growth, revealing the arrays of silicon dioxide dots on silicon. In a next step, the nanodots are also removed, leaving a nanopatterned bare silicon surface with regular arrays of nanopits at the footprint of each nanodot. This silicon surface structuring finds interesting applications in nanoelectronics. One such application is in silicon nanocrystals memories, where the structuring of the oxidized silicon surface leads to the growth of discrete silicon nanocrystals of uniform size. In this work, we examine the electrical quality of the Si/SiO2 interface of a nanostructured oxidized silicon surface fabricated as above and we find that it is appropriate for electronic applications (an interface trap density below 1–3 1010 eV1 cm2 is obtained, indicative of the high quality of the thermal silicon oxide). r 2007 Elsevier B.V. All rights reserved. PACS: 82.45 h; 81.16Rf; 81.16 Pr; 61.46w; 68.65 K Keywords: Porous alumina; Nanostructuring; Nanopatterning; Si/SiO2 interface
1. Introduction Nanopatterned oxidized silicon surfaces find important applications in nanoelectronics and self-assembly of quantum dots [1–4]. Conventional techniques used in this respect are (a) electron beam lithography combined with etching and (b) ion beam milling using focused ion beams. Both of these techniques offer accuracy, repeatability and flexibility in the design, but are costly and relatively slow. Alternatively, when periodic structures are needed on silicon, template technology by electrochemistry may be used, which may be applied on large areas, and is consequently very fast and low-cost technique. Anodic alumina thin films on silicon may be used in this respect. Corresponding author. Tel.: +302106503137; fax: +302106511723.
E-mail address: [email protected] (M. Kokonou). URL: http://www.imel.demokritos.gr. 1386-9477/$ - see front matter r 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.physe.2006.12.008
These films are fabricated by anodization of aluminum films on a silicon substrate and, under specific electrochemical conditions, they show regular vertical pores distributed in the plane in a hexagonal close-packed (HCP) structure. The size and density of pores is adjustable by changing the electrochemical conditions used [5–11]. In a previous work [12,13], the authors developed a technology using very thin anodic porous alumina films on silicon for fabricating two-dimensional arrays of SiO2 quantum dots on silicon by chemical oxidation of the silicon substrate through the pores. The size of the dots depends on the oxidation time and chemical solution used and the dots material is stoichiometric SiO2. Since the dots are grown by consuming silicon from the substrate, the remaining silicon surface if we remove the dots shows the negative pattern of that of the dots-containing surface (arrays of pits on Si following the pore distribution).
ARTICLE IN PRESS 2
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In this work, we used capacitance–voltage (C–V) techniques to characterize the Si/SiO2 interface in two cases: (a) In samples with the two-dimensional arrays of SiO2 dots fabricated as above and further oxidized at high temperature in order to grow 6-nm-thick thermal silicon oxide in the areas between the dots and at the same time to increase the vertical thickness of the dots. (b) In samples as in (a) from which the SiO2 dots were removed and the samples were then oxidized under the same conditions as above so as to fabricate a 6-nmthick silicon oxide film of homogeneous thickness on all the patterned silicon surface. From C–V curves on fabricated capacitors, the density of interface states was calculated. 2. Experimental results and discussion 2.1. Sample fabrication The process for sample fabrication is illustrated in more detail in Fig. 1. An Al film, 500-nm thick, was first grown on a p-type silicon wafer by electron gun evaporation. An ohmic contact was formed on the backside of the wafer and the sample was anodized in sulfuric acid aqueous solution, 6% in volume, under a constant voltage of 20 V at room temperature. Under these conditions, a porous alumina thin film was grown on silicon, containing vertical pores ordered on the surface in HCP arrays. The average diameter of the pores was 16 nm, while their density was about 6 1010 pores/cm2. Their length was that of the alumina film thickness. Following the current–voltage anodization curve, the time at which the Al films was fully consumed was determined and anodization was further left to proceed for few more seconds so as the oxygen of the electrolyte started to diffuse into the Si substrate and to oxidize it locally, forming SiO2 nanoislands (dots) at each pore tip (Fig. 1(b)). The diameter of these dots was in general larger than the pore diameter due to isotropic lateral oxidation underneath the alumina film. By dissolving the alumina template at the end of the anodization process in phosphoric acid aqueous solution 5% in weight, a silicon surface with two-dimensional arrays of SiO2 dots on top was obtained (Fig. 1(c)). Dot distribution on the silicon surface followed the hexagonal structure of the alumina template. This is illustrated in Fig. 2(a), where a top view AFM image of the SiO2 nanodots is shown. In Fig. 2(b) we see an AFM image of the nanostructured bare silicon surface after chemical dissolution of the SiO2 nanodots, where the arrays of nanopits at the footprint of the removed nanodots are identified. Two different patterned oxidized silicon samples were then fabricated: (a) Sample S1 (structure shown in Fig. 1(d)): This sample was composed of the silicon substrate with SiO2 dots,
Fig. 1. Process flow for the fabrication of a nanopatterned silicon surface. An Al film is deposited on Si (a), which is fully transformed into porous alumina by anodization (b). After full Al consumption, anodization proceeds further for a short time in order to chemically oxidize the silicon surface at each pore tip, thus growing SiO2 nanodots of diameter slightly larger than the pore diameter (b). The alumina film is then removed (c) and the remaining structure contains two-dimensional arrays of SiO2 nanodots on Si. This structure may be oxidized as is (d) or after removal of the SiO2 dots (e). After step (e) the oxidized structure has an undulated silicon oxide layer of homogeneous thickness on top (f).
which was then further oxidized in a high-temperature furnace at 850 1C for 17 min. Under these oxidation conditions, a silicon oxide layer, 6-nm thick, is in general grown on a bare Si surface of p-type silicon, (1 0 0) oriented, with resistivity in the range of 1–10 O cm. This film was grown in-between the dots, while under the dots the oxidation proceeds more slowly than on the bare Si area. The maximum height of the dots in the vertical direction was about 10 nm. An annealing step at 920 1C for 30 min followed the oxidation. (b) Sample S2 (structure shown in Fig. 1(f)): In this case, the dots on the silicon surface were dissolved in dilute
ARTICLE IN PRESS M. Kokonou, A.G. Nassiopoulou / Physica E 38 (2007) 1–5
3
[12]. The density of the dots under the above fabrication conditions for samples S1 and S2 was about 4–5 1010 cm2, their lateral diameter on the silicon surface was in the range of 35–45 nm, while their height was E10 nm. The above samples S1 and S2 were used to fabricate aluminum-gated MOS capacitors. Al was deposited on the oxidized silicon surface and patterned in order to define the capacitor area (104 cm2). The samples were subjected to forming gas annealing (N2/H2 environment) in an open furnace at 420 1C for 20 min. They were then characterized by double sweep C–V measurements at frequencies of 1 MHz, 100, 10 and 1 kHz. Quasi-static current–voltage measurements were also performed on the samples and the interface trap densities were calculated by the high–low frequency method. 2.2. Electrical characterization of Si/SiO2 interfaces
Fig. 2. AFM top view images showing a silicon surface with arrays of SiO2 dots (a) or pits left on the surface after the chemical dissolution of the dots (b).
HF and a bare silicon surface with pits following the dots position was obtained (Fig. 1(e)). The depth of the pits was 2–3 nm. The wafers were then oxidized so as to obtain a thin undulated silicon oxide layer, 6-nmthick, on the undulated silicon surface (oxidation was done also at 850 1C for 17 min). An annealing step at 920 1C for 30 min followed the oxidation. Samples with SiO2 nanoislands were characterized by atomic force microscopy (AFM) and X-ray photoelectron spectroscopy (XPS) and results were published elsewhere
As it was mentioned before, both samples S1 and S2 were oxidized under the same conditions that give a 6-nm-thick oxide film on bare Si. In sample S2, this silicon oxide layer was homogeneous in thickness and followed the patterned silicon topography. In sample S1, we expected to get areas with 6-nm-thick oxide between the islands and areas with thicker oxide in the initial island areas. Both the electrochemical and the thermal oxides were stoichiometric SiO2, as verified experimentally elsewhere [13]. In both cases of samples S1 and S2, the interface between the silicon substrate and the oxide was scalloped. Since in general steps the silicon surface may introduce stresses that increase the interface states, in this work we investigated the electronic quality of the scalloped Si/SiO2 interface of the above samples, in order to verify if the structures are appropriate for applications in electronic devices. The interface trap density was calculated using the wellknown high–low frequency method [13–16]. Double sweep C–V measurements were performed at four different frequencies, namely at 1 MHz, 100, 10 and 1 KHz. Fig. 3 shows C–V curves for samples S1 (Fig. 3(a)) and S2 (Fig. 3(b)). We see that in both cases all C–V curves coincide perfectly between them at all frequencies and no hysteresis effects are observed. This is a first indication of the high quality of the oxide films. Quasi-static current–voltage measurements were also performed and they were compared with the high frequency C–V curves, as shown in Fig. 4. Again, 4a corresponds to sample S1 and 4b to sample S2. We see that in both cases the offset corresponding to interface traps is negligible. Using detailed calculations we estimated the interface traps density and the results are shown in Fig. 5. The interface traps density near midgap was about 2.7 1010 eV1 cm2 in the case of sample S1 containing the silicon oxide dots (Fig. 5(a)), while it was about 1.7 1010 eV1 cm2 in the case of sample S2 with the homogeneous SiO2 thickness (Fig. 5(b)). The reference of the energy in these diagrams is the highest level of the valence band. These densities are certainly
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Fig. 3. C–V curves of samples S1 (a) and S2 (b) at 4 different frequencies. The coincidence of all 4 curves in each case is indicative of the high quality of the oxides in both cases.
Fig. 4. High-frequency and quasi-static (low-frequency) C–V curves from samples S1 (a) and S2 (b). No hysteresis is observed, indicative of the low density of interface traps.
Fig. 5. Density of interface states in the cases of sample S1 (a) and S2 (b) as a function of energy.
within the range of interface traps densities of the highest quality flat Si/SiO2 interfaces used in microelectronics. This means that any stress effects due to interface undulations were minimized by the high-temperature annealing and they did not affect the quality of the interface. The Al annealing in N2–H2 ambient was also an important step for minimizing the interface trap density. From the high-frequency C–V measurements, we estimated the equivalent oxide thickness in both cases of
samples S1 and S2, using the equation: tox ¼
o A , C ox
where tox is the equivalent oxide thickness, e is the dielectric constant of SiO2, eo the dielectric constant of vacuum, A the capacitor area and Cox the capacitance of the structure in accumulation. The measured Cox was 56.9 pF for sample S1 containing the SiO2 nanodots, while it was 57.6 pF in the
ARTICLE IN PRESS M. Kokonou, A.G. Nassiopoulou / Physica E 38 (2007) 1–5
case of sample S2 with the undulated oxide of homogeneous thickness. This result is unexpected, since it gives an equivalent oxide thickness of a capacitor with a flat SiO2 surface equal to tox1 ¼ 6.1 nm for sample S1 and tox2 ¼ 6.3 nm for sample S2. Taking into account that sample S1 contained already the SiO2 nanodots before oxidation, it was expected that a thicker equivalent oxide would have been grown on the surface of this sample. Although it is well known that the oxidation rate is different on an already oxidized surface compared with a non-oxidized one, the total oxide thickness effect was expected to be higher under the same oxidation conditions if an oxide of a certain thickness was already there. However, it seems from our results that the oxidation process is more complicated in the presence of the nanodots and an accurate simulation taking into account the ellipsoidal shape of the nanodots and possible strains/ stresses at the nanodots interface with silicon is needed. 4. Conclusions Nanopatterning of a silicon surface was performed by growing two-dimensional arrays of SiO2 dots on silicon through an anodic porous alumina thin film and oxidizing the resulting samples after chemical etching of the alumina film. Two kinds of samples with an undulated Si/SiO2 interface were fabricated. In the first sample, the SiO2 dots were left on the silicon surface, thus an oxide structure of inhomogeneous thickness was grown after oxidation, while in the second case the dots were removed before oxidation and an undulated SiO2 film of homogeneous thickness on all the Si surface was grown. In both cases C–V
5
measurements revealed a high electronic quality scalloped Si/SiO2 interface with a low density of interface traps, adequate for applications in nanoelectronic devices.
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