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Nanowatt devices
A B S T R A C T S ON M I C R O E L E C T R O N I C S AND R E L I A B I L I T Y
87
performance parameter control attained through use of compatible thin-film/monolithic processing technologies is demonstrated. It is further demonstrated that an overall design approach which considers both the electronic functions to be performed and limitations and advantages of the processing techniques involved can result in integrated circuit performance characteristics which are superior to those of the "discrete component" counterpart.
"Tuning forks" sound a hopeful note. H. C. NATHANSON,W. E. NEWELL and R. A. WICKSTROM, Electronics, p. 84 (September 1965). A new type of transistor offers a solution to the tuning problem without depending on inductance. The output signal's frequency is controlled by a stable mechanical resonator that works like a tiny tuning fork. Because the resonator is the gate electrode of a surface-fieldeffect transistor, the new device is called a resonant-gate transistor, or R G T . z Hundreds of R G T s can be made on a silicon wafer, with materials and fabrication techniques that are compatible with the manufacture of integrated circuits. Resonant devices can be made in a variety of configurations, which may make integrated circuits suitable for many new applications in communications and control.
The impact of microelectronics on industry. A. T. LAWTON,Instrument Practice, p. 711 (August 1965). The increasing use of miniaturized electronics equipment in industry means that instrument and control engineers are going to need an increasing awareness of the developments in the fastest changing of all industries. Miniaturization is not undertaken solely to reduce the size of a unit, it also provides faster operating and more reliable equipment. Vacuum equipment in microelectronics. R. P. RIEGERT,SCP and Solid State Technology, p. 17 (July 1965). A general review of vacuum equipment used in microelectronics is presented. The areas discussed are the system, gauging and instrumentation, and evaporation sources. Nanowatt devices. W. W. GAERTNER, Proc. IEEE, p. 592 (June 1965). It is shown, with the aid of several examples, that as microelectronic circuits with a power consumption of a few microwatts have been engineered for practical systems applications, it becomes technologically feasible to build silicon transistors with substantial power gain at a supply power of one nanowatt or lower. The investigation covers the limitations with respect togain, speed, size, and noise which one encounters as the supply power for circuits is reduced below the microwatt level, and also the experimental results that have already been achieved in the laboratory. The design characteristics of nanowatt transistors, plus guidelines for their practical fabrication, are derived. Figures of merit for minimum-power devices and circuits are defined. The performance of experimental transistors and of anslog and logic circuits operating at 20 nanowatts and lower is described. The four-pole parameters and the maximum achievable power gain of a transistor operating in the nanoampere range are derived, and the necessary source and load resistors are shown to rise into the 100-megohm range and higher, so that they may become a limitation to further power reduction before the transistor itself loses its capacity for power gain. The speed of small-signal and large-signal nanowatt circuits is investigated and found to be limited only by RC time constants. With the required high resistors, the device capacitances and, more important, the circuit stray capacitances must be reduced by several orders of magnitude, with 10 -1~ farads as a technological goal. This means not only that the conducting cross section of all devices and interconnections must be reduced approximately proportional to the bias currents but that the length of resistors and interconnections and thus the distance between adjacent circuits must be reduced by approximately the same ratio. It is shown that circuit geometries will have to undergo major changes, that nanowatt microelectronic circuits most likely will not be based on silicon as the host crystal, and that entire systems rather than individual devices and circuits will have to be fabricated in the same crystal or on the same substrate. Assuming certain size restrictions derived earlier by Wallmark and Marcus, it appears at present that nanowatt circuits will be restricted to operating frequencies below one megacycle. Transistors with a collector area of 3 by 3 microns, and resistors with a linewidth of less than 1 micron, a length of less than 100 microns and sheet resistances as high as 100 megohms per square are established as technological goals. These goals do not violate any laws of device physics, but the technology necessary to achieve them is not known at present in all cases. Electron and ion beams are noted as potentially important tools in the advanced technology necessary to reach such extremely small size in integrated structures. Noise is shown not to be a basic limitation. Billion-element systems with a power consumption of a few watts
88
A B S T R A C T S ON M I C R O E L E C T R O N I C S AND R E L I A B I L I T Y
are found to be technologically--though not yet economically--feasible, and the conclusion is drawn that solid-state technology will allow the building of electronic systems that simulate the function of major biological nerve systems in the same volume and with the same power consumption as their living counterparts.
SEMICONDUCTOR INTEGRATED CIRCUITS Cubic F-silicon carbide films on silicon substrates. N. C. TOMBS, J. J. COMERand J. F. FITZGERALD, Solid-State Electronics 8, p. 839 (1965). Highly adherent films of cubic ~-silicon carbide have been grown on single-crystal silicon substrates by heating in the presence of graphite in an argon atmosphere. The reaction process and film characteristics were investigated by electron diffraction. Initially, a singlecrystal [3-silicon carbide film is formed, having an epitaxial relationship to the silicon substrate. Growth proceeds by diffusion of a carbon-bearing species, from the gas phase, inward to the silicon-silicon carbide interface. Beyond a certain thickness, growth becomes polycrystalline. Both n- and p-type films resulted from spontaneous doping, but high resistivities were not observed. Controlled phosphorus diffusion into silicon from P~O~ vpaour using a red phosphorous source. A. G. NASSIBIANand G. WHITINg, Solid-State Electronics 8, p. 843 (1965). A single-stage method for low concentration diffusion of phosphorus into silicon using a red phosphorous source is described. When accurately controlled vapour of red phosphorous is combined with oxygen in the diffusion furnace to form a P205 vapour, accurate control of surface concentration on silicon slices from 1017 atoms cm -3 to greater than 3 × 10 ~° atoms cm -3 can be achieved. Results of sheet resistivity and surface concentrations are presented as a function of partial pressure of oxygen and source temperature. It is concluded from these results that the surface concentration is dependent on the oxide thickness grown on the slice during the diffusion. Results on surface concentration as a function of diffusion time at constant pressures of oxygen are also presented. From these results a definite relationship between surface concentration and the rate of oxidation and diffusion time has been demonstrated. A mechanism for this system of diffusion is described in terms of the diffusion rate of the phosphorus through the oxide and the rate of oxidation of the silicon slice. A condition for constant surface concentration for all diffusion times has been deduced and from this condition a value for the diffusion coefficient of phosphorus in the oxide has been calculated. The shape of the impurity profiles of diffused layers has been studied and show that at low concentrations, impurity distribution characterized by erfc can be obtained. Finally the application of this method in two stage diffusion is described to indicate that it can replace the conventional P~O5 diffusion system. A simple m e t h o d for determining the impurity distribution near a p-n junction. P. E. GRAY and R. B. ADLER,IEEE Transactions on Electron Devices ED-12, No. 8, p. 475 (August 1965). It is well known that the form of the dependence upon bias voltage of the increment21 space-charge layer capacitance of an asymmetrically-doped p-n junction depends (in a rather complicated way) upon the concentration profile of the impurity charge on the high-resistivity side. It is shown in this paper that this impurity profile is related, in a very simple way, to the dependence of the incremental space-charge layer elastance upon the total depletion charge in either half of the dipole layer. The incrementalelastance vs. charge relationship has been employed in a simple pulsed-charge automatic measurement system which yields the impurity profile directly, as the slope of an x - y recording. The system has advantages for rapid evaluation of impurity distributions in the base regions of transistors. These same advantages apply for the high-resistivity sides of asymmetrically doped diodes, under circumstances in which the quick automatic plotting feature is needed, very high accuracy is not required, and the reverse saturation current of the junction is small. Massive heterovalent substitutions in octahedrally coordinated semiconductors. A. J. ROSENRERC and F. WALD, J. Phys. Chem. Solids 26, p. 1079 (1965). The alloying of indium in Bi2Se 3 and of cadmium and indium in PbSe and PbTe have been studied using melt-grown crystals containing up to 5 mol per cent of the impurity atoms. In each case, the mixed crystal retains the basic crystal structure type of the host crystal with diminution in the volume of the unit cell. In the lead compounds, the densities of the mixed crystals are in accord with a stoichiometric replacement of cations. The lattice parameter of cadmium-doped PbTe indicates that direct substitution takes place in the octahedral sites of the tellurium atom sublattice, while, in indium-doped PbTe, the indications are that at least one-third
87
performance parameter control attained through use of compatible thin-film/monolithic processing technologies is demonstrated. It is further demonstrated that an overall design approach which considers both the electronic functions to be performed and limitations and advantages of the processing techniques involved can result in integrated circuit performance characteristics which are superior to those of the "discrete component" counterpart.
"Tuning forks" sound a hopeful note. H. C. NATHANSON,W. E. NEWELL and R. A. WICKSTROM, Electronics, p. 84 (September 1965). A new type of transistor offers a solution to the tuning problem without depending on inductance. The output signal's frequency is controlled by a stable mechanical resonator that works like a tiny tuning fork. Because the resonator is the gate electrode of a surface-fieldeffect transistor, the new device is called a resonant-gate transistor, or R G T . z Hundreds of R G T s can be made on a silicon wafer, with materials and fabrication techniques that are compatible with the manufacture of integrated circuits. Resonant devices can be made in a variety of configurations, which may make integrated circuits suitable for many new applications in communications and control.
The impact of microelectronics on industry. A. T. LAWTON,Instrument Practice, p. 711 (August 1965). The increasing use of miniaturized electronics equipment in industry means that instrument and control engineers are going to need an increasing awareness of the developments in the fastest changing of all industries. Miniaturization is not undertaken solely to reduce the size of a unit, it also provides faster operating and more reliable equipment. Vacuum equipment in microelectronics. R. P. RIEGERT,SCP and Solid State Technology, p. 17 (July 1965). A general review of vacuum equipment used in microelectronics is presented. The areas discussed are the system, gauging and instrumentation, and evaporation sources. Nanowatt devices. W. W. GAERTNER, Proc. IEEE, p. 592 (June 1965). It is shown, with the aid of several examples, that as microelectronic circuits with a power consumption of a few microwatts have been engineered for practical systems applications, it becomes technologically feasible to build silicon transistors with substantial power gain at a supply power of one nanowatt or lower. The investigation covers the limitations with respect togain, speed, size, and noise which one encounters as the supply power for circuits is reduced below the microwatt level, and also the experimental results that have already been achieved in the laboratory. The design characteristics of nanowatt transistors, plus guidelines for their practical fabrication, are derived. Figures of merit for minimum-power devices and circuits are defined. The performance of experimental transistors and of anslog and logic circuits operating at 20 nanowatts and lower is described. The four-pole parameters and the maximum achievable power gain of a transistor operating in the nanoampere range are derived, and the necessary source and load resistors are shown to rise into the 100-megohm range and higher, so that they may become a limitation to further power reduction before the transistor itself loses its capacity for power gain. The speed of small-signal and large-signal nanowatt circuits is investigated and found to be limited only by RC time constants. With the required high resistors, the device capacitances and, more important, the circuit stray capacitances must be reduced by several orders of magnitude, with 10 -1~ farads as a technological goal. This means not only that the conducting cross section of all devices and interconnections must be reduced approximately proportional to the bias currents but that the length of resistors and interconnections and thus the distance between adjacent circuits must be reduced by approximately the same ratio. It is shown that circuit geometries will have to undergo major changes, that nanowatt microelectronic circuits most likely will not be based on silicon as the host crystal, and that entire systems rather than individual devices and circuits will have to be fabricated in the same crystal or on the same substrate. Assuming certain size restrictions derived earlier by Wallmark and Marcus, it appears at present that nanowatt circuits will be restricted to operating frequencies below one megacycle. Transistors with a collector area of 3 by 3 microns, and resistors with a linewidth of less than 1 micron, a length of less than 100 microns and sheet resistances as high as 100 megohms per square are established as technological goals. These goals do not violate any laws of device physics, but the technology necessary to achieve them is not known at present in all cases. Electron and ion beams are noted as potentially important tools in the advanced technology necessary to reach such extremely small size in integrated structures. Noise is shown not to be a basic limitation. Billion-element systems with a power consumption of a few watts
88
A B S T R A C T S ON M I C R O E L E C T R O N I C S AND R E L I A B I L I T Y
are found to be technologically--though not yet economically--feasible, and the conclusion is drawn that solid-state technology will allow the building of electronic systems that simulate the function of major biological nerve systems in the same volume and with the same power consumption as their living counterparts.
SEMICONDUCTOR INTEGRATED CIRCUITS Cubic F-silicon carbide films on silicon substrates. N. C. TOMBS, J. J. COMERand J. F. FITZGERALD, Solid-State Electronics 8, p. 839 (1965). Highly adherent films of cubic ~-silicon carbide have been grown on single-crystal silicon substrates by heating in the presence of graphite in an argon atmosphere. The reaction process and film characteristics were investigated by electron diffraction. Initially, a singlecrystal [3-silicon carbide film is formed, having an epitaxial relationship to the silicon substrate. Growth proceeds by diffusion of a carbon-bearing species, from the gas phase, inward to the silicon-silicon carbide interface. Beyond a certain thickness, growth becomes polycrystalline. Both n- and p-type films resulted from spontaneous doping, but high resistivities were not observed. Controlled phosphorus diffusion into silicon from P~O~ vpaour using a red phosphorous source. A. G. NASSIBIANand G. WHITINg, Solid-State Electronics 8, p. 843 (1965). A single-stage method for low concentration diffusion of phosphorus into silicon using a red phosphorous source is described. When accurately controlled vapour of red phosphorous is combined with oxygen in the diffusion furnace to form a P205 vapour, accurate control of surface concentration on silicon slices from 1017 atoms cm -3 to greater than 3 × 10 ~° atoms cm -3 can be achieved. Results of sheet resistivity and surface concentrations are presented as a function of partial pressure of oxygen and source temperature. It is concluded from these results that the surface concentration is dependent on the oxide thickness grown on the slice during the diffusion. Results on surface concentration as a function of diffusion time at constant pressures of oxygen are also presented. From these results a definite relationship between surface concentration and the rate of oxidation and diffusion time has been demonstrated. A mechanism for this system of diffusion is described in terms of the diffusion rate of the phosphorus through the oxide and the rate of oxidation of the silicon slice. A condition for constant surface concentration for all diffusion times has been deduced and from this condition a value for the diffusion coefficient of phosphorus in the oxide has been calculated. The shape of the impurity profiles of diffused layers has been studied and show that at low concentrations, impurity distribution characterized by erfc can be obtained. Finally the application of this method in two stage diffusion is described to indicate that it can replace the conventional P~O5 diffusion system. A simple m e t h o d for determining the impurity distribution near a p-n junction. P. E. GRAY and R. B. ADLER,IEEE Transactions on Electron Devices ED-12, No. 8, p. 475 (August 1965). It is well known that the form of the dependence upon bias voltage of the increment21 space-charge layer capacitance of an asymmetrically-doped p-n junction depends (in a rather complicated way) upon the concentration profile of the impurity charge on the high-resistivity side. It is shown in this paper that this impurity profile is related, in a very simple way, to the dependence of the incremental space-charge layer elastance upon the total depletion charge in either half of the dipole layer. The incrementalelastance vs. charge relationship has been employed in a simple pulsed-charge automatic measurement system which yields the impurity profile directly, as the slope of an x - y recording. The system has advantages for rapid evaluation of impurity distributions in the base regions of transistors. These same advantages apply for the high-resistivity sides of asymmetrically doped diodes, under circumstances in which the quick automatic plotting feature is needed, very high accuracy is not required, and the reverse saturation current of the junction is small. Massive heterovalent substitutions in octahedrally coordinated semiconductors. A. J. ROSENRERC and F. WALD, J. Phys. Chem. Solids 26, p. 1079 (1965). The alloying of indium in Bi2Se 3 and of cadmium and indium in PbSe and PbTe have been studied using melt-grown crystals containing up to 5 mol per cent of the impurity atoms. In each case, the mixed crystal retains the basic crystal structure type of the host crystal with diminution in the volume of the unit cell. In the lead compounds, the densities of the mixed crystals are in accord with a stoichiometric replacement of cations. The lattice parameter of cadmium-doped PbTe indicates that direct substitution takes place in the octahedral sites of the tellurium atom sublattice, while, in indium-doped PbTe, the indications are that at least one-third