New analog implementation technique for fractional-order controller: A DC motor control

Accepted Manuscript New analog implementation technique for fractional-order controller: A DC motor control Ilias Dimeas, Ivo Petras, Costas Psychalinos PII: DOI: Reference:

S1434-8411(17)30161-9 http://dx.doi.org/10.1016/j.aeue.2017.03.010 AEUE 51816

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International Journal of Electronics and Communications

Please cite this article as: I. Dimeas, I. Petras, C. Psychalinos, New analog implementation technique for fractionalorder controller: A DC motor control, International Journal of Electronics and Communications (2017), doi: http:// dx.doi.org/10.1016/j.aeue.2017.03.010

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New analog implementation technique for fractional-order controller: A DC motor control Ilias Dimeasa , Ivo Petrasb,∗, Costas Psychalinosa a University b Technical

of Patras, Physics Department, GR-26504 Rio Patras, Greece University of Kosice, Faculty of BERG, 042 00 Kosice, Slovakia

Abstract This paper deals with a new method for analog implementation of the fractionalorder controller using an active element in form of the operational transconductance amplifier. Transfer function of such controller is performed by the inverse-follow-the-leader feedback topology. Presented implementation is resistorless, energy effective and suitable for realization in integrated form. Proposed and implemented fractional-order controller is used for a DC motor control. Obtained simulation results in frequency and time domains are presented as well. Keywords: fractional calculus, fractional-order control, filter, operational transconductance amplifier (OTA), inverse-follow-the-leader feedback (IFLF) topology, CMOS circuit 2010 MSC: 26A33, 47N70

1. Introduction and motivation Fractional calculus is known since the regular calculus with the first written reference dated in September 1695 in letter from Leibniz to L’Hospital. Nowadays, the fractional calculus has a wide area of applications [23, 31, 34]. One 5

of the most important field is control system engineering where a new model of the controlled systems and new controllers have been described [3, 8, 10, 19, 20, 30, 40]. ∗ Corresponding

author Email address: [email protected] (Ivo Petras)

Preprint submitted to International Journal of Electronics and Communications March 14, 2017

Moreover, the use of industrial controllers such as for instance classical tunable proportional-integral-derivative (PID) controllers or its particular cases as 10

for example PI, are ubiquitous in all kind of industries [2]. Such controllers have been constructed and designed to help technicians and engineers maintain the plant to the desired performances of the systems by incorporating these controllers in feedback and forward loops. One of the areas for improvement of such controllers is having the ability to incorporate fractional-order dynamics.

15

Nowadays, most industry controllers are implemented in digital form on PLC automata or industrial computer. Such implementation has limits because of microprocessor speed and memory capacity. There are many processes where digital controller cannot reach desired behavior due to mentioned limitations. In such case, the analog form of industrial controller implementation is necessary

20

[9, 33, 36]. Especially in control of fast processes, as for instance motor speed in mechatronics system, chemical reactions, and so on. So far, for an analog implementation of the fractional-order controller an approximation technique based on fractance or constant phase element (CFE) circuit has been used [33]. This circuit consists of passive electrical elements as for instance resistors, capacitors, coils in various structures connected with an operating amplifier. The impedance of the CFE has transfer function [4]: ZF = Qs−α ,

(1)

where Q is the coefficient of the CFE and α, α ∈ R, is the exponent (order) of the CFE. Fractional-order elements described by (1) have a constant magnitude slope of 20α dB per decade, and a flat horizontal phase at απ/2 radians, where 25

α > 0 is the order. We can summarize, that such device has the following characteristics [13, 14, 21, 22]: first the phase angle is constant independent of the frequency within a wide frequency band; second it is possible to construct a filter which has moderated characteristics that can not be realized by using the conventional devices.

30

Generally speaking, there are three basic structures of fractance (constant phase element) devices: 2

• the most popular is a domino ladder circuit network (with parallel, series, or cascade arrangement of elements), or symmetrical ladder called also as transmission line circuit; 35

• and very often used is a tree structure of basic electrical elements; • finally, constant phase element realized by simple device using electrodes in some chemical substance or other dielectric (e.g. fractor [1, 5]). The ladder and tree networks are multi-component realization and fractor is a single-component realization of constant phase element. Here we must

40

mention that all basic electrical elements (resistor, memristor, capacitor and coil) are not ideal and they also should be described by fractional-order models [7, 18, 29, 43]. Design of fractances (or constant phase elements) can be done easily using any of the rational approximations [26, 35] or by using direct relations given on

45

[38, 42]. The results of such computation are exact values of the basic elements as for example resistors, capacitors and coils. Based on advantages of the analog circuits described above and taking into account the fact that such structures are energy consuming circuits, we would like to design and show resistorless, energy effective and suitable realization

50

in integrated form. In such OTA implementation an electronic tuning of its characteristics is possible. Typically, α could be tuned in the range [0.2, 0.8] using the specific OTA. This is also demonstrated in [37]. In this paper a novel method and topology for the analog implementation of the integrated fractional-order controller are presented.

55

This paper is organized as follows: In Section 1 some introduction and motivation to problem is briefly discussed. Section 2 is focused on fractional calculus fundamentals. In Section 3 a DC motor mathematical model is described. Section 4 brings a definition of fractional-order control and fractional-order PID controller design. In Section 5 a new analog implementation technique is de-

60

scribed. In Section 6 the simulation results of an illustrative example are pre-

3

sented. Section 7 concludes this paper with some additional remarks and discussion. 2. Preliminaries 2.1. Definitions 65

Fractional calculus is a generalization of integration and differentiation to non-integer (fractional) order fundamental operator a Dtr , where a and t are the bounds of operation and r (r ∈ R) is the order of the operation. There are several definitions of fractional integration and differentiation (see e.g. [22, 31]). The most often used are the Gr¨ unwald-Letnikov (GLD) definition, the Riemann-

70

Liuville definition (RLD) and Caputo’s definition (CD). For a wide class of functions, the three definitions - GLD, RLD, and CD - are equivalent [31]. Due to the fact, that the initial conditions (especially for real experiments in electrical circuits) for fractional-order differential equations with Caputo’s derivative are in the same form as for integer-order differential equations, we will focus only to the Caputo’s definition, which can be written as [31]: Z t 1 f (n) (τ ) C r D f (t) = dτ, (n − 1 < r < n). a t Γ(n − r) a (t − τ )r−n+1

(2)

One important property of this operator is that it captures the history of all past events contrary to what occurs with integer derivatives/integrals that are ”local“ operators. This means that fractional order systems have intrinsically 75

a memory of the previous dynamical evolution. For many engineering applications are often used the Laplace transform methods. The Laplace transform of the GLD, RLD, and CD of the fractional derivative/integral, under zero initial conditions for order r is given by [22, 31]: £{a Dt±r f (t); s} = s±r F (s).

(3)

Some other important properties of the fractional derivatives and integrals we can find in several works (e.g.: [20, 22, 31], etc.). Geometric and physical interpretation of fractional integration and fractional differentiation were exactly described in Podlubny’s work [32]. 4

80

2.2. Continuous time approximation of fractional-order operator A detailed review of the various approximation methods and techniques for continuous and discrete fractional-order models in form of IIR and FIR filters was done in work [39]. Moreover, the Oustaloup’s approximation method has been compared with the biquadratic approximation method proposed in [15]. For simulation purpose, here we present the Oustaloup’s approximation algorithm based on a recursive distribution of zeros and poles at well chosen intervals [24]. The method is based on the approximation of a function of the form: H(s) = sr ,

r ∈ R,

r ∈ [−1; 1]

(4)

for the frequency range selected as (ωb , ωh ) by a rational function: b H(s) = Co

N Y s + ω0

k

k=1 85

(5)

s + ωk

using the following set of synthesis formulas for zeros, poles and the gain: ωk0

 = ωb 

ωk

= ωb

Co

= ωhr ,

ωh ωb ωh ωb

+0.5(1−r)  k+N2N +1

, +0.5(1+r)  k+N2N +1

,

(6) (7)

where ωh , ωb are the high and low transitional frequencies. An implementation of this algorithm in Matlab as a function script ora foc() is given in [11]. Using the described Oustaloup’s-Recursive-Approximation (ORA) method with: ωb = 10−3 ,

ωh = 103 ,

(8)

the obtained 5th order approximations for fractional function H(s) = s−0.5 is: 1 s0.5

≈

0.03162 s5 + 16.92 s4 + 537.1 s3 + 1072 s2 + 134.4 s + 1 s5 + 134.4 s4 + 1072 s3 + 537.1 s2 + 16.92 s + 0.03162

(9)

and for fractional function H(s) = s0.5 is: s0.5 ≈

31.62 s5 + 4249 s4 + 3.389 × 104 s3 + 1.698 × 104 s2 + 534.9 s + 1 s5 + 534.9 s4 + 1.698 × 104 s3 + 3.389 × 104 s2 + 4249 s + 31.62 (10) 5

3. A DC motor model We will consider the general model of the DC motor (DCM) which is depicted in Fig. 1. The applied voltage Va controls the angular velocity ω(t).

Figure 1: General model of a DC motor.

Figure 2: Mathematical model of a DC motor. 90

The relations for the armature controlled DC motor are shown schematically in Fig. 2. Transfer function (with Td (s) = 0) has the form [12, 16]: GDCM (s) =

θ(s) Km = . Va (s) s[(Ls + R)(Js + Kf ) + Kb Km ]

(11)

However, for many DCM the time constant of the armature is negligible and therefore we can simplify model (11). A simplified continuous mathematical model has the following form: GDCM (s)

= =

θ(s) Km = Va (s) s[R(Js + Kf ) + Kb Km ] [Km /(RKf + Kb Km )] KDCM = , s(τ s + 1) s(τ s + 1)

(12)

where the time constant τ = RJ/(RKf + Kb Km ) and KDCM = Km /(RKf + 95

Kb Km ). It is of interest to note that Km = Kb . In this paper we consider a mini DC motor with model number PPN13KA12C which is great for robots, remote control applications, CD/DVD mechanics, etc. 6

Specifications are [17]: min. voltage 1.5 [V], nominal voltage 2 [V], max. voltage 2.5 [V], max. rated current 0.08 [A], no load speed 3830 [r/min] and rated load speed 3315 [r/min]. For our mini DC motor the physical constants are: R = 6 [Ω], Km = Kb = 0.1, Kf = 0.2 [N ms] and J = 0.01 [kgm2 /s2 ]. For these motor constants the transfer function (12) of the DC motor has the form: GDCM (s) =

0.08 . s(0.05s + 1)

(13)

4. Fractional-order control 4.1. Preliminary consideration As we mentioned in introduction, we can also find works dealing with the application of the fractional calculus tool in control theory, but these works have 100

usually theoretical character, whereas the number of works, in which a real object is analyzed and the fractional - order controller is designed and implemented in practice, is very small. The main reason for this fact is the difficulty of controller implementation. This difficulty arises from the mathematical nature of fractional operators, which, defined by convolution and implying a non-limited

105

memory, demand hard requirements of processors memory and velocity capacities. Due to this reason the analog implementation is appropriate. In the area of automation and process control, the fractional-order controllers which are the generalization of classical integer-order controllers, would lead to more precise and robust control performances. Historically, there are four basic

110

types of the fractional-order controllers [20, 28]: • CRONE controller (3 generations), • Tilted Proportional and Integral (TID) controller, • Fractional-order PID controller, • Fractional-order Lead-Lag compensator.

115

In this paper we will consider only the fractional-order PID controller (a.k.a. fractional-order PIλ Dµ or PIλ Dδ controller). 7

4.2. Fractional-order PID controllers The fractional-order PIλ Dδ controller (FOC) was proposed as a generalization of the PID controller with integrator of real order λ and differentiator of real order δ. The transfer function of such type controller in Laplace domain has form [30]: C(s) =

U (s) = Kp + Ki s−λ + Kd sδ , E(s)

(λ, δ > 0),

(14)

where Kp is the proportional constant, Ki is the integration constant and Kd is the differentiation constant. Transfer function (14) corresponds in time domain with the fractional differential equation in the following expression: u(t) = Kp e(t) + Ki 0 Dt−λ e(t) + Kd 0 Dtδ e(t), 120

(15)

where λ and δ are arbitrary real numbers. Taking λ = 1 and δ = 1, we obtain a classical PID controller. If δ = 0 and Kd = 0, we obtain a PIλ controller, etc. All these types of controllers are particular cases of the PIλ Dδ controller, which is more flexible and gives an opportunity for better adjustment of the dynamical properties of the fractional-

125

order control system. All those fractional-order controllers are sometimes called optimal phase controllers because only with non-integer order we can get a constant phase somewhere between 0o and −180o depending on the parameters λ and δ. 4.3. Fractional-order controller design

130

Several methods and tuning techniques for the FOC parameters were developed during the past ten years. They are based on various approaches (see e.g.: [20, 25, 28, 40]). In Fig. 3 is depicted feedback control loop, where C(s) is the transfer function of the controller and GDCM (s) is the transfer function of the DC motor.

135

Following [27], we will design the controller, which will give us a step response of feedback control loop with overshoot independent of payload changes 8

Figure 3: Feedback control loop.

(iso-damping). In the frequency domain point of view it means phase margin independent of the payload changes. Phase margin of controlled system is [6, 41]: Φm = arg [C(jωg )GDCM (jωg )] + π,

(16)

where jωg is the crossover frequency. Independent phase margin means in other words constant phase. This can be accomplished by controller of the form: C(s) = k1

k2 s + 1 , sµ

k1 = 1/KDCM ,

k2 = τ.

(17)

Such controller gives a constant phase margin and obtained phase margin is   k1 KDCM Φm = arg [C(jω)GDCM (jω)] + π = arg +π (jω)(1+µ) h i π = arg (jω)−(1+µ) + π = π − (1 + µ) . (18) 2 140

For our parameters of controlled object (13) and desired phase margin Φm = 45o , we get the following constants of the fractional-order controller (17): k1 = 12.5, k2 = 0.05 and µ = 0.5. With these constants we obtain a fractional Iλ Dδ controller, which is a particular case of the PIλ Dδ controller and has the form: C(s)

= =

τ KDCM

s0.5 +

1 KDCM s0.5

√ 12.5 Kd s0.5 + Ki s−0.5 = 0.625 s + √ , s

(19)

where Ki = 12.5, Kd = 0.625 and δ = λ = 0.5. According to relation (18), by using a controller (19), we can obtain a phase margin: Φm = arg [C(jω)GDCM (jω)] + π = π − (1.5) 145

which was desired phase margin specification. 9

π = 45o , 2

5. New analog implementation of the fractional-order controller 5.1. Inverse-Follow-the-Leader Feedback Topology The transfer functions of fractional-order differentiators and integrators could be performed by the inverse-follow-the-leader feedback (IFLF) topology depicted in Fig. 4, where the realized transfer function is given by the form: H (s) =

Figure 4:

G5 s5 + s5 +

G4 τ1

1 τ1

G3 G2 G1 3 2 τ1 τ2 s + τ1 τ2 τ3 s + τ1 τ2 τ3 τ4 1 1 1 3 2 τ1 τ2 s + τ1 τ2 τ3 s + τ1 τ2 τ3 τ4 s

s4 +

s4 +

G0 τ 1 τ2 τ3 τ 4 τ5 1 τ 1 τ2 τ3 τ 4 τ5

s+ +

(20)

5th order IFLF filter topology for approximating a fractional-order integra-

tor/differentiator.

5.2. Operational Transconductance Amplifier (OTA) Technique Following [37], an active element will be the OTA, while the emulation of 150

CPE will be performed using the OTA-C realization. The realization of Fig. 4, using OTAs as active elements, is demonstrated in Fig. 5. The chosen OTA is given in Fig. 6. Considering that the MOS transistors operate in sub-threshold region, the expression of their small-signal transconductance is:

gm0 = 155

I0 , nVT

(21)

where VT is the thermal voltage (26mV @ 27 o C), I0 is the bias current, and n, (1 < n < 2) is the sub-threshold slope factor of an MOS transistor. From Fig. 6, taking into account that transistors Mn1-Mn2 and Mn3-Mn4 have aspect ratios (A : 1) and (1 : A) respectively, the value of the transcoductance of the OTA is then given by:

gm = gm0

4A (1 + A)

2

⇔ gm =

10

I0 nVT

4A 2

(1 + A)

(22)

Figure 5: 5th order IFLF filter topology using OTAs.

160

The scaling factor A is used to increase linearity of the active cell and has been chosen equal to 5 [37]. Using (22) it is readily obtained that the realized time-constants τi , with (i = 0, 1, 2, . . . 5), in the transfer function (20) are: τi =

Ci 9 Ci n V T = gm 5 I0

(23)

and therefore, are electronically controlled through the dc bias current I0 . Moreover, the required voltage scaling factors Gi , with (i = 0, 1, 2, . . . , 5), 165

can be easily implemented on OTAs with appropriate transconductance values (i.e. Gi = gmi /gm ). In order to achieve that, the corresponding bias currents must be equal to Gi .I0 . The OTAs with transconductance gm have a bias current I0 =2.5 nA, so that the minimum bias current of an OTA with transconductance gmi is higher than

170

20 pA, which is a critical value for avoiding the effect of leakage currents. Also according to (22), the transconductance gm is considered 35.61 nS. The employed power supply voltages of the circuit depicted in Fig. 6 are: VDD = 0.75 V, VSS = - 0.75 V and VCM = 0 V. The MOS transistors aspect ratios are provided in Table 1.

175

Using (9)-(10) and (19)-(20), we obtain the following values for the time constants and gain factors summarized in Tables 2 and 3.

11

Table 1: MOS Transistors aspect ratio for OTA realization in Fig. 6.

Transistor

Aspect ratio

Mp1 , Mp2

10µm/2µm

Mn1 , Mn4

25µm/5µm

Mn2 , Mn3

25µm/5µm

Mb1 , Mb2 , Mb3

60µm/1.5µm

Table 2: Values of gain factors and time-constants for fractional-order integrator.

index i

Gi

τi (sec)

0

31.63

−

1

7.943

47.6µ

2

1.996

803µ

3

0.501

12.8m

4

0.126

203m

5

0.032

3.42

Utilizing the expression τi = Ci/gm and the values from Tables 2 and 3, we can calculate the values of the capacitances Ci , of each integrator stage. The calculated values are depicted in Table 4. 180

In order to have an indication of the practical behavior of the proposed circuit topology, considering the effect of parasitics, its layout design has been performed and is demonstrated in Fig. 7 . The dimensions of the layout design are: (543.5 µm) x (442.9 µm).

6. Simulation results 185

The functional simulation of the proposed circuit topology has been performed through the Analog Design Environment of Cadence software. The technology we used is the AMS 0.35µm C35B4 CMOS. The obtained post-layout magnitude and phase responses of the fractional-order differentiator are demonstrated in Figs. 8(a)-8(b), where the corresponding theoretically predicted plots 12

Figure 6: OTA structure with enhanced linearity.

190

are also given. The unity-gain frequency of the differentiator was 465 mHz, while the corresponding theoretical value was 405 mHz. In addition, the corresponding phase error plot is provided in Fig. 8(c) where it is derived that an error less than ±10 % is observed within the range [1.4 mHz, 26 Hz]. The corresponding plots for the integrator are given in Fig. 9. The unity-gain

195

frequency of the integrator was 31.26 Hz, while the corresponding theoretical value was 24.83 Hz. The corresponding range for the same level of accuracy as in the case of differentiator was [150 mHz, 375 Hz]. The open-loop gain and phase responses of the controller are demonstrated in Fig. 10, where the measured phase-margin was 53o close to the theoretically

200

predicted value of 45o . Also, the unity-gain frequency was 160 mHz, while the theoretical value was 158 mHz. The corresponding responses of the closed-loop system are given in Fig. 11. The time-domain behavior of the controller has been evaluated through its stimulation by a step voltage with level equal to 5 mV. The obtained output

13

Table 3: Values of gain factors and time-constants for fractional-order differentiator.

index i

Gi

τi (sec)

0

0.032

–

1

0.126

0.73m

2

0.501

12.3m

3

1.996

196m

4

7.943

3.12

5

31.63

52.5

Table 4: Capacitor values of fractional-order differentiator and integrator.

205

Capacitor

Differentiator

Integrator

C1

26pF

1.7pF

C2

438pF

28.6pF

C3

6.97nF

455pF

C4

110.9nF

7.24nF

C5

1.87µF

122nF

waveform along with the corresponding theoretical one are plotted in Fig. 12. The settling-time of the controller was 10 sec, while the overshoot was 19%. The steady state error between the two responses in Fig. 12 is caused by the OTAs imperfections, including non-linearity, finite output impedance, etc. The behavior of the controller at process, power supply voltage, and temper-

210

ature (PVT) corners has been evaluated over 32 different PVT corners. Thus, worst case power (fast-fast), worst case speed (slow-slow), worst case one (fastslow), and worst zero (slow-fast) MOS transistors model parameters, 0o C, 27o C, 60o C temperature values, and ±5 % supply voltages variations have been considered. The derived open-loop responses are depicted in the plots of Fig. 13.

215

The corners of the gain at unity-gain frequency (i.e. 158 mHz) were -0.2dB and +0.1dB. The corresponding corners of the phase margin were 57o and 51o , respectively. The corresponding nominal values were 0 dB and 53o , respectively.

14

Figure 7: The layout design of the proposed controller.

The same test has been performed for the step response of the controller and the obtained waveforms are given in Fig. 14. The measured worst-case overshot 220

was 23.73% and the settling-time was 10.5 sec. The corresponding nominal values were 19% and 10 sec, respectively. A nominal case and the worst-case are marked in Fig. 14 by arrows.

7. Conclusion and discussion A novel topology of a fractional-order controller is presented in this paper. 225

Owing to the fact that Operational Transconductance Amplifiers (OTA) have been employed as active elements, the topology offers the advantage of resistorless realization. According to the authors best knowledge, this is the first time in the literature, where such benefit is offered by a fractional-order controller configuration. In addition, the utilization of the small-signal transconductance 15

230

parameter (gm ) of the OTA offers the capability for electronic adjustment of the characteristics of the controller, in order to compensate the effects of MOS transistors imperfections. Due to the low-frequency nature of operation of the controller, MOS transistors biased in the weak inversion are used and, consequently, the topology offers the benefit of the reduced power consumption and,

235

also, low-voltage operation. More specifically, the power dissipation was 906 nW, while a ±0.75V power supply scheme has been employed for implementing the system. On the other hand, a drawback is originated from the fact that the transconductance parameter is used for realizing the time-constants; more specifically, this imposes a restriction on the maximum level of the signals that

240

could be successfully handled by the systems in the order of mVs. The presented post-layout simulation results confirmed the correct operation of the system in terms of accuracy and fulfillment of specifications. It should be also mentioned at this point that the proposed method is general and, consequently, it could be followed for implementing controllers in various types of

245

applications.

Acknowledgment This work was supported in part by the Slovak Grant Agency for Science under grant VEGA 1/0908/15, and by the Slovak Research and Development Agency under the contracts: No. APVV-14-0892, No. SK-PL-2015250

0038, project ARO W911NF-15-1-0228, and COST Action CA15225 a network supported by COST (European Cooperation in Science and Technology).

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(a) Magnitude

(b) Phase

(c) Phase error

Figure 8: Responses of the fractional-order differentiator of order 0.5 using 5th order of Oustaloup approximation.

22

(a) Magnitude

(b) Phase

(c) Phase error

Figure 9: Responses of the fractional-order integrator of order 0.5 using 5th order of Oustaloup approximation.

23

(a) Magnitude

(b) Phase

Figure 10: Open-loop frequency responses of the DC motor system.

24

(a) Magnitude

(b) Phase

Figure 11: Closed-loop frequency responses of the DC motor system.

25

Figure 12: Step response of the DC motor closed-loop system stimulated by an input voltage 5 mV.

26

(a) Magnitude

(b) Phase

Figure 13: PVT corner analysis results for the open-loop frequency response of the DC motor system.

27

Figure 14: PVT corner analysis results for step response of the DC motor system.

28