New concerns about integrated circuit reliability

World Abstracts on Microelectronics and Reliability A/cm 2 were employed. Some tests were also performed at frequencies of 20 kHz and 100 kHz, The conductor lifetime was found to depend strongly on the pulse duty factor, with the mean time to failure, measured in on-time hours, showing a monotonic improvement as the duty factor of testing was decreased. At a pulse current density of 1 x 10 ? A,,cm 2, the results demonstrated the occurrence of electromigration in the direction of the "~electron wind". A proportion of the improvement in the conductor lifetime is attributable to a decrease in the a m o u n t of conductor self-heating, particularly at a current density of 1 × 10" A / c m 2: however, self-heating considerations cannot account for the entire improvement unless unusually large activation energies for grain boundary diffusion are assumed. The cause of the remainder of the improvement Inot accounted for by self-heating) has not been determined: however, excess vacancy concentration, and its dependence on duty factor, may contribute to the lifetime improvement. H - M O S reliability. S. ROSENBERG,D. CROOK and B, E u z E y r . Pr, w. IEEE Reliab. Phys. Syrup., San Diego (18-20 April 1978), p. 19. H - M O S is a new high performance N-channel technology with a 1-picojoule speed power product. This high performance technology is the result of scaling M O S device dimensions. This paper discusses potential failure mechanisms introduced by scaling M O S device dimensions. Experimental data are presented which show H - M O S to be a reliable technology.

Ceramic capacitor insulation resistance failures accelerated by low voltage. THOMAS F. BREN~A~. Proc. IEEE Reli.b. Phys. Syrup., San Diego (18-20 April 1978L p. 68. Ceramic capacitors failed insulation resistance testing at less than 1/10th their rated voltage. Many failures recovered as the voltage was increased. Comprehensive failure analysis techniques, some of which are unprecedented, were used to examine these failures. It was determined that there was more than one failure mechanism, and the results indicate a need for special additional screening, Failure of small thin film conductors due to high currentdensity pulses. E. KINSBRO~. C. M. MELUAR-SMITH. A. T. ENGLISH and T. CHYNOWETH Pr,c. IEEE Re/lab. Phys. Syrup., San Diego (18 20 April 1978). p. 248. Current pulses at high repetition rates and extremely high current density ( > 10 "7 A,'cm 2) were applied to small geometry, thin-tilm aluminum-copper alloy conductors. The conductor lifetirnes were measured as a function of current density and duty cycle. While the observed open circuit failures are evidently related in some way to the temperature excursions produced by Joule heating, the exact mechanismqs) causing failure is not so clear, and probably varies depending on test conditions. A previously described ohmic non-linearity measurement was used to characterize the conductor's ability to dissipate heat, A strong inverse correlation was found between the ohmic non-linearity and time-to-failure. Reliability evaluation program and results for a 4K dynamic RAM. H. A. BaTt)ORI~, D. H. HEY;SLer and R. D. WassoN. Pr,c. IEEE Re/tab. Phys. Syrup., San Diego (18-2(1 April 1978), p. [4. A comprehensive reliability evaluation program for an n-channel silicon gate 4K dynamic RAM is described. The program included dynamic high-temperature accelerated aging f:~r various time periods followed by thorough electrical testing. Results including failure mechanism descriptions, acceleration factors, and projected failure rates during system use arc included. Actual failure rate during system use is under 100 FITs after less than one year of operation. Reliability of dynamic fatigue data for plastic coated fused silica optical waveguide fibers. Jot~N T. KRAt:SE and A. CARNEVAI_E. PPoC. IEEE Reliah. Phrs. Syrup.. San Diego

475

( 18-20 April 1978t, p. 213, The reduction in strength of glass fibers under stress and in the presence of noisture or water follo~s a log stress vs. log time to failure dependence theoretically and experimentally. Errors in the acquisition of fatigue data for plastic coated fibers are minimized when the time dependent parameter in the dynamic case is actual time to failure and not strain rate. Also for those fibers tested in humid or water environments, the transport time of water through the fiber coating must be considered for those systems demonstrating a time and,or temperature dependence of transport. The time dependent reduction in strength b3 slo~ crack growth is fatigue and its rate is given by the slope of the log stress vs. log time to failure curve. The intercept of this curve is the "instantaneous" strength. For plastic coated fibers this intercept shows marked reduction in a water environment as compared to drier ambient conditions. This reduction is attributed to surface energy decrease, but this concept has not been rigorously researched. Slope and intercept data given for a variety of plastic coatings on fused silica fiber and compared statistically in ambient and water environments, enable engineering worst case predictions of lifetime to be made. These predictions, however, are for fibers having high instantaneous strengths in > 20 K m lengths and are therefore not representative of fibers exhibiting low proof-test strength levels. Also. the possibility of interracial coating-glass interactions occurring and having adverse effects on these predicted fiber lifetimes is not considered.

Test chips in LSI reliability assurance. T. W. GRIsWOU~. Proc. IEEE Reliab. Phys. Syrup., San Diego 118 20 April 1978/, p. 88. Reliability evaluation of integrated circuits i,,, founded primarily on the concept of exhaustive exercising and stressing of internal nodes for detection of potential failure conditions. The complexity of LSI circuits makes "'complete" testing a physical impossibility, and even incomplete testing is made expensive by the necessity of treating each circuit as a distinct problem, even if the entire set of circuits is made by the same manufacturing process in the same production line. Effective test programs have to be designed to concentrate on critical areas and seusitixc parameters of the particular chips, and test designers lind themselves" requiring more and more knowledge of chip layout, architecture, design rules, processing steps, and so on. New concerns about integrated circuit reliability. D. S. PECK. Pr,c. IEEE Reliub. Phys. Syrup., San Diego (18-20 April 1978), p. 1. By 1960 it was recognized that the large number of semiconductor devices involved in forthcoming electronic switching systems would require very low device failure rates in order to achieve reasonable maintenance costs or. in fact. reliable operability, It was also recognized that the future failure rate of component parts of a system had to be predicted and guaranteed in order for system development to proceed in an orderly and economical way. Accelerated stress tests were developed attd have since been used to predict or limit the long-term failure rates of semiconductor devices. In recent years a different problem has also become important that of infant mortality. We have trouble defining this early part of the +%athtub'" curve because it typically involves a small percentage of failures and may not show up in small-sample life tests. The large sample required for determining the actual perceutage may be difficult to obtain, particularly if it involves a new device and if available samples are also required lot system development. Typically, we can best identify the extent of infant mortality by observation of early failures in operating systems. In large systems, such failures may be weeded out in the relatively long installation and test period. Medium-size equipments can go into operation, however, directl} from

476

World Abstracts on Microelectronics and Reliability

production and even a small infant-mortality percentage can be amplified by device numbers to a large problem. Attention is directed, therefore, to techniques for identifying the infant-mortality failure rates, failure mechanisms, and associated activation energies, if identifiable. VMOS electrostatic protection. 1. S. BHATTI, E. FULLER and F. B. JENNE. Proc. IEEE Reliab. Phys. Syrup., San Diego ~18-20 April 1978). p. 140. Present state of the art MOS devices with 1000 A thick gate oxides have breakdown voltages in the 60-80 volts range. VMOS devices with the same oxide thickness have lower breakdown voltages ~25-30 volts) due to higher fields in the oxide at the bottom of the V-groove. A VMOS protection device with higher protection capability than conventional MOS protection devices has been designed and tested. It consists of a polyresistor connected to an nipn diode, followed by an implanted n + diffusion which acts as a distributed RC network attenuating the input voltage spikes. The final section consists of a planar NMOS transistor connected between the n + diffusion and the VMOS gate. Tests show that this type of protection device is superior to conventional protection devices.

Failure analysis of passive devices. JOHN E. MANN. Proc. IEEE Reliab. Phys. Syrup., San Diego (18 20 April 1978), p. 89. The failure analysis of passive devices requires all the skills and technology used in the failure analysis of solid state devices. Passive devices use similar manufacturing methods compared to solid state techniques to accomplish the finished device. Thin oxides, used in the manufacturing of tantalum slug capacitors, are subject to current and voltage transients which concern analysts on MOS structures. To create the K factor in the dielectric of ceramic capacitors, ppm's of additives are used. These can be more difficult than diffusions in determining their effect on the device performance Resistors suffer from all the structural effects of moisture, voltage transients, or contamination reported in the studies on integrated circuits or hybrids. Filters and small inductors packaged for circuit application are subject to problems of handling and board insertion as well as the above mentioned failure modes. In the choice of analyzing a passive component over an integrated circuit or LSI circuit, there are times when many analysts would rather accept the more complicated solid state circuit rather than tackle the simple passive unit. Electrical overstress failure analysis in microcircuits. J. S. SMITH. Proc. IEEE Reliah. Phys. Syrup., San Diego 118-20 April 1978), p. 41. A major cause of semiconductor failure is electrical overstress (EOSI. Examination of the failed device will often yield sufficient information to determine the dimensions of the electrical transient causing failure. It is the intent of this paper to identify those clues and pertinent features that will permit the failure analyst to estimate the dimensions of the electrical transient involved. Accelerated reliability evaluation of lrimetal integrated circuit chips in plastic packages. L. J. GALLACE, H. J. KHAJEZADEEI and A. S. RosE. Proc. IEEE Reliab. Phy,s. Syrup., San Diego 118-20 April 1978k p. 224. Accelerated step stress and constant-stress reliability tests have been performed on trimetal MOS and bipolar IC chips wire-andbeam-tape bonded in both plastic and hermetic packages. A failure mechanism related to a high-temperature chemical reaction between the epoxy molding compound and the materials of the device support structure was identified and a solution provided. A reliable dD" ceramic dual in-line package (CERDIP). R. K. LowRy. C. J. VAN LEEUWEX. B. L. KENNIMER and L. A. MILLER. Proc'. IEEE Reliah. Phy.s. St'rap., San Diego (18--20 April 1978t, p. 207. The ceramic DIP package utilizing Iov~ temperature l - 500 (') sealing glasses has been

smmltaneous] 3 widely deployed lot packaging 1( ~ and condemned for many high reliability a.pplications becat£~c of high moisture content in the sealed cavil). This paper describes the construction, characterisnca, and reliability performance of a volume producible, cost-cltecti ~e Cerdip which has a sealed moisture content typical], ies~, than 500 ppmv.

Corrosion ofin-basesolders. RAM KOSSOWSK5,R. C. I::%ARSOX and L. T. CHR1STOVICH. Proc. IEEE Rclial+. t'hv.v S~m,h',.. San Diego (18-20 April 1978). p. 200. Aqueous corrosion of in-base solders attached to Au conductors ~as studied by metallurgical analysesand galvanic cell tests. It gas t;,mnd that the solders, 90 ln-10 Ag, 50,1n-50 Pb. 7(1 In-30 Pb and 50 In-50 Sn, when coupled to Au. became susceptible to galvanic corrosion attack in solutions ~ith pH < 4 lhe mode of corrosion attack and corrosion products ~cre investigated by SEM, microprobe, and x-ra) diffraction analyses. Ways to avert the problem are also discussed Analytical techniques for electronic materials--A comparative evaluation. R. KossowsKY. Pr, c. IEEE Rcliab. Phys. Syrup., San Diego (18-20 April 1978k p. 112 A summary of surface analytical techniques, and the excitation and detection methods are tabulated and the following will be described in this paper: Scanning Electron Microscope (SEM), Electron Microprobe IEMP). Auger Electron Spectroscopy (AES), Seconditry, Ion Mass Spectroscopy (SIMS), X-Ray Fluorescence, and X-Ra', Photoelectron Spectroscopy (XPS). The various techniques are critically compared; advantages and disadvantages are pointed out and discussed. Few examples of actual applications to analysis, relevant to the electronic material engineers, are described. Accelerated life testing for LS! failure mechanisms. C. H

ZIERDT, Jr. Proc. IEEE Reliab. Phys. Syrup., San Diego (18-20 April 1978), p. 76. The attraction of accelerated life testing for LSI devices, as for smaller-scale ones. is its potential for assuring in advance that the failure rates of the devices in service will be initially small and will remain satisfactorily low during their expected useful life. Both 1007 o stress-screening (to remove atypically made devicesl and sampled life testing (to assure low long-term failure rates) benefit from accelerated (higher-than-normal stresst testing. Application of highly-accelerated tests of some types to LSI devices is inhibited by factors related to their complexity: it is usually not possible to accelerate testing of LSI circuits as much as can be done with smaller-scale ones. To be effective for LSI. operating (vs. staticl burn-in and life tests are required, and complex circuits may cease to function properly at relatively low temperatures. High-voltage application is also limited to the +'least common denominator" which any circuit element can withstand. Accelerated testing is not a universal remedy: it cannot be sati~ly applied to screening out of several potential failure mechanisms, and it cannot be effective in those areas of a LSI circuit to which stress or measuring bias is nol applied because of simplified aging or measurement circuits and programs.

Process testing for reliability control. WALLER H. ScnaOl~,X. Proc. IEEE Reliab. Phys. Syrup., San Diego (18 20 April 1978), p. 81. There is a rapidly increasing trend to apply silicon integrated circuits (ICs) in microprocessors to the control of complete systems. A few examples are consumer products, automobiles, and distributed communication. These systems are complex and orders of magnitude more expensive than the microprocessors, necessitating a functional reliability of the microprocessors and l('s much higher than in traditional applications. The need for higher reliability is particularly demanding in applications