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New technique for measuring the threshold voltage in MOS devices
Microelectronic Engineering 60 (2002) 409–413 www.elsevier.com / locate / mee
New technique for measuring the threshold voltage in MOS devices A. Benfdila a , A. Chikouche a , M.S. Khanniche b , * a
Microelectronics and Semiconductor Device Physics Laboratory ( LMPDS), The Engineering Faculty, University M. Mammeri, BP 17 RP, Tizi-ouzou 15000, Algeria b Department of Electrical and Electronic Engineering, The University of Wales Swansea, Singleton Park, Swansea SA2 8 PP, UK Received 18 January 2001
Abstract The present paper describes an experimental method that can be used to measure the threshold voltage in MOS devices in the form of transistors or capacitors. The proposed method is based on the detection of the non-steady-state / steady-state transition of the surface potential at the oxide–semiconductor interface of a MOS device, when it is swept from depletion to inversion regions. This detection is carried out as follows: a set of current versus gate signal frequency measurements, for different voltage amplitudes, is performed. The frequency values corresponding to the maximum measured current (optimum frequency) fm , are read. Several gate voltage versus optimum frequencies ( fm –VG ) curves are plotted for gate voltage values ranging from 0.2 to 3 V with a 0.1 V step increment. The ( fm –VG ) curves are found to undergo an abrupt change of slope at a specific gate voltage value. The value of threshold voltage is extracted from the critical points of the former curves. Experiments have been carried out on different devices. The measured values of threshold voltage are found to be in good agreement to those obtained by the conventional ID –VGS and simulation methods as well as that supplied by the device manufacturer. 2002 Elsevier Science B.V. All rights reserved. Keywords: Threshold voltage; Surface potential; Oxide traps; Interface states; MOSFET; Gate current; Current frequency
1. Introduction The knowledge of the threshold voltage in MOS devices, especially in the case of short channel MOSFETs, is of paramount importance in the monitoring of device functioning and the characterization of the device oxide and oxide–semiconductor interface. The most common techniques used to measure the threshold voltage in MOS transistors are based on static ID –VGS measurements [1,2]. * Corresponding author. 0167-9317 / 02 / $ – see front matter PII: S0167-9317( 01 )00701-8
2002 Elsevier Science B.V. All rights reserved.
410
A. Benfdila et al. / Microelectronic Engineering 60 (2002) 409 – 413
Recently, a few techniques have been developed based on simulation and modeling of the MOS transistor behavior in conjunction with I–V measurements [3–5]. In VLSI / ULSI integrated circuits characterization aimed at higher reliability and lifetime, it has been found that the charge pumping method (CPM) [6] is a powerful tool in the study of short channel MOSFETs and can be used to determine the threshold voltage shifts [7]. During an experimental study undertaken for the purpose of studying the gate current occurring during the charge pumping phenomenon, an unusual current behavior has been observed in the gate circuit of the MOSFET when its drain and source are open and the signal frequency is varied [8]. A thorough experimental investigation has been achieved to exploit the physical behavior of this current. It has been found that it is related to the charging and discharging of the interface states [8] and the oxide traps [9] located in the MOS system. In addition, it has been used to extract the electrical and physical parameters of the MOS system [10]. The current behavior observed in the experimental investigation is discussed for different parameters, i.e. gate voltage value, signal frequency, device structure and technology [11]. It has been found that the gate voltage versus optimum frequency obtained from current frequency curves is of typical behavior and can be used to determine the threshold voltage in MOS devices.
2. Experimental set-up and devices The experimental set-up used in the present method is based on a HP 4140B picoammeter and a function generator connected in series with the MOSFET supplying a square wave signal. The experimental devices under the form of test structures are manufactured using the dry oxidation technology process. Commercial devices of the type 3N17X are also used. The experimental devices are put in a test-fixture HP16055A to avoid external noise. The function generator supplies variable amplitude and frequency signals. The automatic frequency control (AFC) is achieved with the help of the DC programmable source of the HP4140B. A PC computer that also reads and treats the experimental data controls the overall experimental set-up. The experimental part of this method consists of measuring the gate (or substrate) current of the MOSFET, with open drain and source, under varied conditions of signal amplitude and frequency. In the experiments carried out in this work, the gate voltage signal is applied to sweep the surface potential at the silicon / silicon dioxide interface from the intrinsic level to deep inversion level. The pulse base level of the gate signal is set to the intrinsic level of the silicon base material of the transistor. The starting amplitude of the gate voltage signal is set to (0.2 V) for the case of nMOSFET. While measuring the gate current for this voltage value, the voltage signal frequency is varied from 1 to 100 kHz. The maximum value of the current and the corresponding frequency are read. The same procedure is repeated for different values of gate voltage signal amplitude starting from 0.2 to 3.0 V by a step increment of 0.005. The smaller the step increment, the greater is the precision of the measured threshold voltage.
3. Results and discussion During the experiments achieved as described above, a set of voltage versus frequency curves has been obtained. The current frequency curves in the frequency range 1–100 kHz showed a current
A. Benfdila et al. / Microelectronic Engineering 60 (2002) 409 – 413
411
Fig. 1. Typical MOSFET I–f curve.
maximum (peak) as illustrated in Fig. 1. The current peak appears within the range 40–70 kHz, depending on the device structure (oxide thickness, densities of surface states and oxide traps, channel dimensions . . . ) and corresponds to a given frequency called the optimum frequency fm [7]. In order to study the effect of gate voltage on signal frequency, a set of ( fm –VG ) curves has been plotted for different devices. Typical curves are shown in Fig. 2. It may be noted that the ( fm –VG ) curves show in the beginning a decrease in the value of fm with an increase of the amplitude VG in the case of n channel MOSFET. When a certain value of fm is reached, the curves show an abrupt change between points A and B as illustrated in Fig. 2. After this abrupt change that terminates at point B, the value of fm becomes constant and does not show any noticeable change with an increase of the gate voltage signal amplitude. In fact, the total region of abrupt change, which lies between points A and B, is indicative of some change in the physical phenomena governing the MOS structure. However, the region of MOS system, which is most sensitive to the effect of gate voltage signals, is the interface silicon / silicon dioxide and the depletion layer underneath. Hence, the expected physical phenomenon is most likely to be associated with them, since the depletion, called also weak inversion, layer increases with an increase of gate voltage. One such physical phenomenon which is known to occur at the silicon / silicon dioxide, is the switching over of the surface region from depletion to inversion regions, which is known to occur at the appearance of the first inversion layer. This first sheet appears at the application of a gate voltage equal to the threshold voltage of a MOS device. When the gate signal increases towards threshold voltage, the depletion (weak inversion) layer starts decreasing till finally it is supposed to vanish at the gate voltage VG equal to the threshold voltage value VT and this marks the commencement of the inversion layer in the surface region. However, the depletion layer, while decreasing, vanishes abruptly and the first layer made up of
A. Benfdila et al. / Microelectronic Engineering 60 (2002) 409 – 413
412
Fig. 2. Typical I–VG curve of a MOSFET.
opposite carrier type appears also abruptly. Accordingly, the limits, first when the depletion layer vanishes and the other when the inversion layer appears, should correspond to the points A and B on the ( fm –VG ) curves according to our understanding. Based on the above contention the point B must correspond to the true value of threshold voltage VT . The determination of the threshold voltage has been also done by the standard (ID –VGS ) and the simulation techniques. The results obtained on different devices are given in Table 1. The results obtained by the present method show a slight difference compared to that obtained by the (ID –VGS ) method. The observed difference takes into account the error margin which is in the 1–3% range. The numerical accuracy of this method compared to the (ID –VGS ) method is in the 95–98% range. Table 1 Threshold voltages using different techniques Device type
Dev. Dev. Dev. Dev. Dev.
A B C D E
Threshold voltage values obtained by: Simulation method
ID –VGS method
Present method
1.10 1.15 1.50 1.20 1.55
1.15 1.20 1.60 1.25 1.50
1.12 1.18 1.55 1.22 1.60
V V V V V
V V V V V
V V V V V
A. Benfdila et al. / Microelectronic Engineering 60 (2002) 409 – 413
413
4. Conclusion The values of the threshold voltage as obtained by the present technique are close to that obtained by the (ID –VGS ) techniques and some simulation-based techniques. Based on the physical arguments as given earlier, regarding the abrupt change in the ( fm –VG ) curves, the present technique is supposed to give a reliable value of threshold voltage. The (ID –VGS ) technique is accurate. However to measure an appreciable drain current, the inversion layer should be present beforehand. This may little affect the true threshold voltage value. In case of ultra-thin oxide and submicron MOSFETs, SILC (stress induced leakage current) and GIDL (gate induced drain leakage) currents as well as the hot carriers that may appear in the channel under drain biasing may modify the appearance of the inversion layer. The major advantage of the present method is that it can be equally well applied to MOS transistors and MOS diodes without any geometric constraints since the process of switching from depletion to inversion is only voltage level dependent.
References [1] P. Richmand, MOS Field Effect Transistors and Integrated Circuits, John Wiley, New York, 1973. [2] M. Kerber, C. Mazuret, U. Schwalke, Measurement of the threshold voltage in MOS capacitor by the equilibrium controlled C–V method, Solid-State Electron. 35 (3) (1992) 379–385. [3] A. Ortiz-Conde, E.D. Gouveia Fernande, J.J. Liou, Md. Rofiqul Hassan, F.J. Garcia-Sanchez, G. De Mercato, W. Wong, A new approach to extract threshold voltage of MOSFETs, IEEE Trans. Electron Devices 44 (9) (1997) 1523–1528. [4] M. Tsuno, M. Suga, M. Tanaka, K. Shibahara, M. Miura-Mattausch et al., Physically based threshold voltage determination of MOSFETs of all gate lengths, IEEE Trans. Electron Devices 46 (7) (1999) 1429–1433. [5] F.J.G. Sanchez, A. Ortiz-Conde, G. De Mercato, J.A. Salcedo, J.J. Liou, Y. Yue, New simple procedure to determine the threshold voltage of MOSFETs, Solid State Electron. 44 (2000) 673–675. [6] G. Groeseneken, H.E. Maes, N. Beltran, R.F. De Keersmaecker, A reliable approach to charge-pumping measurements in MOS transistors, IEEE Trans. Electron Devices 31 (1) (1984) 42–53. [7] P. Hermans, J. Witters, G. Groeseneken, H.E. Maes, Analysis of charge pumping technique and its application for the evaluation of MOSFET degradation, IEEE Trans. Electron Devices 36 (1989) 1318–1335. [8] V. Mitra, A. Benfdila, R. Bouderbala, H. Bentarzi, Generation of a DC substrate current in MOS devices under oscillating gate voltages, Appl. Phys. Lett. 62 (1) (1993) 69–71. [9] X. Mingzheng, T. Changua, W. Yangyuan, A new technique for determining the capture cross section of the oxide traps in MOS structures, IEEE Electron. Device Lett. 12 (3) (1991) 122–124. [10] A. Benfdila, A. Chikouche, An alternative method for measuring flatband voltage in MOS devices, Microelectron. Eng. 49 (1999) 205–209. [11] A. Benfdila, A. Chikouche, Substrate current model in pulsed MOS devices, Microelectron. J. 31 (2000) 193–197.
New technique for measuring the threshold voltage in MOS devices A. Benfdila a , A. Chikouche a , M.S. Khanniche b , * a
Microelectronics and Semiconductor Device Physics Laboratory ( LMPDS), The Engineering Faculty, University M. Mammeri, BP 17 RP, Tizi-ouzou 15000, Algeria b Department of Electrical and Electronic Engineering, The University of Wales Swansea, Singleton Park, Swansea SA2 8 PP, UK Received 18 January 2001
Abstract The present paper describes an experimental method that can be used to measure the threshold voltage in MOS devices in the form of transistors or capacitors. The proposed method is based on the detection of the non-steady-state / steady-state transition of the surface potential at the oxide–semiconductor interface of a MOS device, when it is swept from depletion to inversion regions. This detection is carried out as follows: a set of current versus gate signal frequency measurements, for different voltage amplitudes, is performed. The frequency values corresponding to the maximum measured current (optimum frequency) fm , are read. Several gate voltage versus optimum frequencies ( fm –VG ) curves are plotted for gate voltage values ranging from 0.2 to 3 V with a 0.1 V step increment. The ( fm –VG ) curves are found to undergo an abrupt change of slope at a specific gate voltage value. The value of threshold voltage is extracted from the critical points of the former curves. Experiments have been carried out on different devices. The measured values of threshold voltage are found to be in good agreement to those obtained by the conventional ID –VGS and simulation methods as well as that supplied by the device manufacturer. 2002 Elsevier Science B.V. All rights reserved. Keywords: Threshold voltage; Surface potential; Oxide traps; Interface states; MOSFET; Gate current; Current frequency
1. Introduction The knowledge of the threshold voltage in MOS devices, especially in the case of short channel MOSFETs, is of paramount importance in the monitoring of device functioning and the characterization of the device oxide and oxide–semiconductor interface. The most common techniques used to measure the threshold voltage in MOS transistors are based on static ID –VGS measurements [1,2]. * Corresponding author. 0167-9317 / 02 / $ – see front matter PII: S0167-9317( 01 )00701-8
2002 Elsevier Science B.V. All rights reserved.
410
A. Benfdila et al. / Microelectronic Engineering 60 (2002) 409 – 413
Recently, a few techniques have been developed based on simulation and modeling of the MOS transistor behavior in conjunction with I–V measurements [3–5]. In VLSI / ULSI integrated circuits characterization aimed at higher reliability and lifetime, it has been found that the charge pumping method (CPM) [6] is a powerful tool in the study of short channel MOSFETs and can be used to determine the threshold voltage shifts [7]. During an experimental study undertaken for the purpose of studying the gate current occurring during the charge pumping phenomenon, an unusual current behavior has been observed in the gate circuit of the MOSFET when its drain and source are open and the signal frequency is varied [8]. A thorough experimental investigation has been achieved to exploit the physical behavior of this current. It has been found that it is related to the charging and discharging of the interface states [8] and the oxide traps [9] located in the MOS system. In addition, it has been used to extract the electrical and physical parameters of the MOS system [10]. The current behavior observed in the experimental investigation is discussed for different parameters, i.e. gate voltage value, signal frequency, device structure and technology [11]. It has been found that the gate voltage versus optimum frequency obtained from current frequency curves is of typical behavior and can be used to determine the threshold voltage in MOS devices.
2. Experimental set-up and devices The experimental set-up used in the present method is based on a HP 4140B picoammeter and a function generator connected in series with the MOSFET supplying a square wave signal. The experimental devices under the form of test structures are manufactured using the dry oxidation technology process. Commercial devices of the type 3N17X are also used. The experimental devices are put in a test-fixture HP16055A to avoid external noise. The function generator supplies variable amplitude and frequency signals. The automatic frequency control (AFC) is achieved with the help of the DC programmable source of the HP4140B. A PC computer that also reads and treats the experimental data controls the overall experimental set-up. The experimental part of this method consists of measuring the gate (or substrate) current of the MOSFET, with open drain and source, under varied conditions of signal amplitude and frequency. In the experiments carried out in this work, the gate voltage signal is applied to sweep the surface potential at the silicon / silicon dioxide interface from the intrinsic level to deep inversion level. The pulse base level of the gate signal is set to the intrinsic level of the silicon base material of the transistor. The starting amplitude of the gate voltage signal is set to (0.2 V) for the case of nMOSFET. While measuring the gate current for this voltage value, the voltage signal frequency is varied from 1 to 100 kHz. The maximum value of the current and the corresponding frequency are read. The same procedure is repeated for different values of gate voltage signal amplitude starting from 0.2 to 3.0 V by a step increment of 0.005. The smaller the step increment, the greater is the precision of the measured threshold voltage.
3. Results and discussion During the experiments achieved as described above, a set of voltage versus frequency curves has been obtained. The current frequency curves in the frequency range 1–100 kHz showed a current
A. Benfdila et al. / Microelectronic Engineering 60 (2002) 409 – 413
411
Fig. 1. Typical MOSFET I–f curve.
maximum (peak) as illustrated in Fig. 1. The current peak appears within the range 40–70 kHz, depending on the device structure (oxide thickness, densities of surface states and oxide traps, channel dimensions . . . ) and corresponds to a given frequency called the optimum frequency fm [7]. In order to study the effect of gate voltage on signal frequency, a set of ( fm –VG ) curves has been plotted for different devices. Typical curves are shown in Fig. 2. It may be noted that the ( fm –VG ) curves show in the beginning a decrease in the value of fm with an increase of the amplitude VG in the case of n channel MOSFET. When a certain value of fm is reached, the curves show an abrupt change between points A and B as illustrated in Fig. 2. After this abrupt change that terminates at point B, the value of fm becomes constant and does not show any noticeable change with an increase of the gate voltage signal amplitude. In fact, the total region of abrupt change, which lies between points A and B, is indicative of some change in the physical phenomena governing the MOS structure. However, the region of MOS system, which is most sensitive to the effect of gate voltage signals, is the interface silicon / silicon dioxide and the depletion layer underneath. Hence, the expected physical phenomenon is most likely to be associated with them, since the depletion, called also weak inversion, layer increases with an increase of gate voltage. One such physical phenomenon which is known to occur at the silicon / silicon dioxide, is the switching over of the surface region from depletion to inversion regions, which is known to occur at the appearance of the first inversion layer. This first sheet appears at the application of a gate voltage equal to the threshold voltage of a MOS device. When the gate signal increases towards threshold voltage, the depletion (weak inversion) layer starts decreasing till finally it is supposed to vanish at the gate voltage VG equal to the threshold voltage value VT and this marks the commencement of the inversion layer in the surface region. However, the depletion layer, while decreasing, vanishes abruptly and the first layer made up of
A. Benfdila et al. / Microelectronic Engineering 60 (2002) 409 – 413
412
Fig. 2. Typical I–VG curve of a MOSFET.
opposite carrier type appears also abruptly. Accordingly, the limits, first when the depletion layer vanishes and the other when the inversion layer appears, should correspond to the points A and B on the ( fm –VG ) curves according to our understanding. Based on the above contention the point B must correspond to the true value of threshold voltage VT . The determination of the threshold voltage has been also done by the standard (ID –VGS ) and the simulation techniques. The results obtained on different devices are given in Table 1. The results obtained by the present method show a slight difference compared to that obtained by the (ID –VGS ) method. The observed difference takes into account the error margin which is in the 1–3% range. The numerical accuracy of this method compared to the (ID –VGS ) method is in the 95–98% range. Table 1 Threshold voltages using different techniques Device type
Dev. Dev. Dev. Dev. Dev.
A B C D E
Threshold voltage values obtained by: Simulation method
ID –VGS method
Present method
1.10 1.15 1.50 1.20 1.55
1.15 1.20 1.60 1.25 1.50
1.12 1.18 1.55 1.22 1.60
V V V V V
V V V V V
V V V V V
A. Benfdila et al. / Microelectronic Engineering 60 (2002) 409 – 413
413
4. Conclusion The values of the threshold voltage as obtained by the present technique are close to that obtained by the (ID –VGS ) techniques and some simulation-based techniques. Based on the physical arguments as given earlier, regarding the abrupt change in the ( fm –VG ) curves, the present technique is supposed to give a reliable value of threshold voltage. The (ID –VGS ) technique is accurate. However to measure an appreciable drain current, the inversion layer should be present beforehand. This may little affect the true threshold voltage value. In case of ultra-thin oxide and submicron MOSFETs, SILC (stress induced leakage current) and GIDL (gate induced drain leakage) currents as well as the hot carriers that may appear in the channel under drain biasing may modify the appearance of the inversion layer. The major advantage of the present method is that it can be equally well applied to MOS transistors and MOS diodes without any geometric constraints since the process of switching from depletion to inversion is only voltage level dependent.
References [1] P. Richmand, MOS Field Effect Transistors and Integrated Circuits, John Wiley, New York, 1973. [2] M. Kerber, C. Mazuret, U. Schwalke, Measurement of the threshold voltage in MOS capacitor by the equilibrium controlled C–V method, Solid-State Electron. 35 (3) (1992) 379–385. [3] A. Ortiz-Conde, E.D. Gouveia Fernande, J.J. Liou, Md. Rofiqul Hassan, F.J. Garcia-Sanchez, G. De Mercato, W. Wong, A new approach to extract threshold voltage of MOSFETs, IEEE Trans. Electron Devices 44 (9) (1997) 1523–1528. [4] M. Tsuno, M. Suga, M. Tanaka, K. Shibahara, M. Miura-Mattausch et al., Physically based threshold voltage determination of MOSFETs of all gate lengths, IEEE Trans. Electron Devices 46 (7) (1999) 1429–1433. [5] F.J.G. Sanchez, A. Ortiz-Conde, G. De Mercato, J.A. Salcedo, J.J. Liou, Y. Yue, New simple procedure to determine the threshold voltage of MOSFETs, Solid State Electron. 44 (2000) 673–675. [6] G. Groeseneken, H.E. Maes, N. Beltran, R.F. De Keersmaecker, A reliable approach to charge-pumping measurements in MOS transistors, IEEE Trans. Electron Devices 31 (1) (1984) 42–53. [7] P. Hermans, J. Witters, G. Groeseneken, H.E. Maes, Analysis of charge pumping technique and its application for the evaluation of MOSFET degradation, IEEE Trans. Electron Devices 36 (1989) 1318–1335. [8] V. Mitra, A. Benfdila, R. Bouderbala, H. Bentarzi, Generation of a DC substrate current in MOS devices under oscillating gate voltages, Appl. Phys. Lett. 62 (1) (1993) 69–71. [9] X. Mingzheng, T. Changua, W. Yangyuan, A new technique for determining the capture cross section of the oxide traps in MOS structures, IEEE Electron. Device Lett. 12 (3) (1991) 122–124. [10] A. Benfdila, A. Chikouche, An alternative method for measuring flatband voltage in MOS devices, Microelectron. Eng. 49 (1999) 205–209. [11] A. Benfdila, A. Chikouche, Substrate current model in pulsed MOS devices, Microelectron. J. 31 (2000) 193–197.