New voltage-mode high-pass, band-pass and low-pass filter using DDCC and OTAs

Int. J. Electron. Commun. (AEÜ) 62 (2008) 701 – 704 www.elsevier.de/aeue

LETTER

New voltage-mode high-pass, band-pass and low-pass filter using DDCC and OTAs Wen-Ta Lee∗ , Yi-Zhen Liao Graduate Institute of Computer and Communication, National Taipei University of Technology, Taipei, Taiwan, ROC Received 31 July 2006; accepted 29 August 2007

Abstract The voltage-mode (VM) biquad filter is presented, which employs one differential difference current conveyor (DDCC), two single-ended operational transconductance amplifiers (OTAs) and two grounded capacitors. The proposed circuit can realize three kinds of filter response that is low-pass, high-pass and band-pass filters from the same configuration. The proposed circuit has no requirements for component-matching conditions and all of elements have no floating effects and any resistances. The proposed circuit has been confirmed by HSPICE simulations and compared with theoretical functions by MATLAB. Finally, to verify our architecture, we have designed this analog filter chip with TSMC 0.35 m 2P4M CMOS technology. This chip contains 129 transistors, operates to 2.18 MHz and consumes 83 mW. The chip area of the analog filter is 0.822 mm2 . 䉷 2007 Elsevier GmbH. All rights reserved. Keywords: Voltage-mode biquad filter; Differential difference current conveyors; Operational transconductance amplifiers

1. Introduction Second-order active filters with high-input impedance are of great interest because several cells of this kind can be directly connected in cascade to implement higher order filters [1]. Recently, several voltage-mode multi-function filters are proposed. Some multi-function filters with single input and three outputs that can realize high-pass, band-pass and low-pass filters, simultaneously, were proposed by Soliman [2,3], Senani [4] and Abdhesh et al. [5]. However these configurations required at least three active components. In 2004, Horng et al. proposed a voltage-mode multifunction filters that can realize high-pass, band-pass and low-pass filter by using two differential difference current

∗ Corresponding author. Tel.: +886 2 27712171x2229;

fax: +886 2 27317120. E-mail addresses: [email protected] (W.-T. Lee), [email protected] (Y.-Z. Liao). 1434-8411/$ - see front matter 䉷 2007 Elsevier GmbH. All rights reserved. doi:10.1016/j.aeue.2007.08.007

conveyors (DDCCs), two grounded capacitors and two ground resistors [6]. However the elements used by these filters were not minimum. In this paper, a new high input impedance filter which can provide high-pass, band-pass, and low-pass responses simultaneously is presented. By using one differential difference current conveyor, two grounded capacitors and two operational transconductance amplifiers (OTAs), we can adjust transconductance ranges easily and widely. Meanwhile, using OTA to replace resistor, we can reduce the chip area effectively. This new architecture cannot only match any passive element conditions, but also employs fewer active or passive components to realize high-pass, band-pass, and low-pass filters, simultaneously.

2. Circuit description The proposed biquad filter using DDCC [7] and OTA [8] is shown in Fig. 1. Circuit analysis yields the following

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W.-T. Lee, Y.-Z. Liao / Int. J. Electron. Commun. (AEÜ) 62 (2008) 701 – 704

Vout2 Vout1 Vin

1

2

3

1

Fig. 2. Nonideal structure of the OTA.

Vout3

output have input parasitical capacitance (Cip ), output parasitical capacitance (Cop ) and output parasitical conductance (Gop ), respectively. The nonideal equation [9] is given by

2

gm

gm (1 − sT ). 1 + sT

Fig. 1. The voltage-mode biquad filter using DDCC and OTAs.

A(s) =

transfer functions:

The parameter of s is operational frequency. The parameter of T is parasitic pole which is produced by inner circuit. The denominator of the nonideal biquad is shown as

Vout1 =

s2C

gm1 gm2 , 1 C2 + sC 1 gm2 + gm1 gm2

(1)

(8)

−sC 1 gm2 Vout2 = 2 , s C1 C2 + sC 1 gm2 + gm1 gm2

(2)

s 2 C1 C2 . 1 C2 + sC 1 gm2 + gm1 gm2

D(s) = s 2 (C1 C2 − C1 T1 1 gm2 + 2 gm1 gm2 T1 T2 ) + s(C1 1 gm2 − 2 gm1 gm2 T2 − 2 gm1 gm2 T1 ) (9) + 2 gm1 gm2 .

(3)

The 0 and Q of the nonideal biquad are

Vout3 =

s2C

It can be seen from Eqs. (1) to (3) that a low-pass response is obtained from Vout1 , a negative band-pass response is obtained from Vout2 and a high-pass response is obtained from Vout3 . In all response, the resonance angular frequency 0 and the quality factor Q are given by  gm1 gm2 0 = , (4) C 1 C2 and



Q=

(5)

Q Sgm1 ,C2

Q = −SC1 ,gm1

0 (C1 1 gm2 − 2 gm1 gm2 T2 − 2 gm1 gm2 T1 )

, Q (C1 C2 − C1 T1 1 gm2 + 2 gm1 gm2 T1 T2 ) Q

[2 G2m (C 2 − C1 T2 1 gm2 + 2 G2m T 2 )]1/2 , (C1 1 gm2 − 2 G2m T2 − 2 G2m T1 )

=

1 2,

(6)

=

1 2.

(7)

(10) (11) (12)

where C 2 = C1 C2 , G2m = gm1 gm2 , T 2 = T1 T2 . The sensitivities of 0 and Q are: 1 0 0 Sgm1 ,gm2 − SC1 ,C2 2 , Q

Q

SC2 ,T1 − SC

The 0 and Q sensitivities are given by  = −SC10,C2

2 gm1 gm2 , (C1 C2 − C1 T1 1 gm2 + 2 gm1 gm2 T1 T2 )



C2 gm1 . C1 gm2

0 Sgm1 ,gm2

20

1 ,T2 ,1 ,2 ,gm1

(13)

21 ,

SgQm2 − 1.

(14) (15)

All of the parameter sensitivities are small in magnitude. Thus, the proposed circuit exhibits a low sensitivity performance.

All active and passive sensitivities are small, and is 0.5.

4. Simulation results 3. Nonideal analysis Taking into account the nonidealities of the eight-terminal DDCC, we obtain IY 1 =IY 2 =IY 3 =0, VX+ =1 VY 1 −2 VY 2 + 3 VY 3 , IZ+ =IX where =1−i and i (i >1) denotes the current tracking error and  = 1 − v and v (v >1) denotes the voltage tacking error. The nonideal model of the OTA is shown in Fig. 2. OTA’s transconductance is not constant that reducing follows frequency increase and the OTA input and

In order to confirm the theoretical validity of the proposed filter configurations given in Fig. 1, they are simulated with HSPICE simulation program. The DDCC + CMOS structure and the OTA CMOS structure are shown in Figs. 3 and 4, respectively. The aspect ratios of the MOS transistors are given in Tables 1 and 2 . The device model parameters used for the HSPICE simulations are taken from TSMC 0.35 m CMOS 2P4M process. The supply voltages

W.-T. Lee, Y.-Z. Liao / Int. J. Electron. Commun. (AEÜ) 62 (2008) 701 – 704

Table 2. Transistor aspect ratios of Fig. 4

Vdd M3

M4

M5

Y1

M1

M2

Y2

M9

M10

M11

M12

M6

M7

M8

Y3

X

703

MOS transistors

Aspect ratio (W/L)

M1, M2 M3, M4, M5, M8 M6, M7 M9

8/1 4/1 8/1 12/1

Z

10 Vbias1

M13

M15

M17

M19

Vbias2

M14

M16

M18

M20

Low-pass

High-pass

0

Vss

Fig. 3. CMOS implementation of the DDCC.

Magnitude (dB)

-10

Band-pass

-20 -30 : theoretical

-40

: high-pass simulation

-50

: band-pass simulation : low-pass simulation

-60 -70 105

o

106 Frequency (Hz)

107

Fig. 5. Amplitude-frequency responses of the biquad.

Fig. 4. CMOS implementation of the OTA.

Table 1. Transistor aspect ratios of Fig. 3 MOS transistors

Aspect ratio (W/L)

M1, M2, M7, M8 M3, M4 M5, M6 M9, M10, M11, M12 M13, M14, M15, M16 M17, M18, M19, M20

10/1 40/1 20/1 400/0.35 120/0.35 240/0.35

are selected as VDD = −VSS = 1.65 V. The filter is designed to realize Butterworth type filter responses (Q = 0.707). The following settings are selected to obtain the low-pass, high-pass, band-pass filters with unity gain at resonance frequency f0 = 2.18 MHz, and C1 = 27 pF, C2 = 13.5 pF, gm1 = gm2 = 261 S. We use MATLAB to verify circuit con-

Fig. 6. The layout of voltage-mode biquad filter.

figuration correctness and the compared results are shown in Fig. 5. Then we can find circuit simulation is matched with the theoretical analysis. All of the OTAs are using singleended structure in the circuit. Finally the chip layout of a new biquad filter chip is shown in Fig. 6. Then the layout floorplan is shown in Fig. 7. The specifications of our analog filter chip are summarized in Table 3 .

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W.-T. Lee, Y.-Z. Liao / Int. J. Electron. Commun. (AEÜ) 62 (2008) 701 – 704

[2] [3] [4]

[5]

[6]

Fig. 7. The layout floorplan.

Table 3. Summary of performance Filter

Voltage-mode biquad filter

Process technology Power supply Filter mode Filter responses Operation frequency Power dissipation Number of transistors Core area include PADs

TSMC 0.35 m CMOS 2P4M ±1.65 V Voltage mode High-pass, Band-pass and Low-pass 2.18 MHz 83 mW 129 0.822 mm2

5. Conclusion A new voltage-mode biquad filter with one input and three outputs using two single-ended OTAs, one DDCC and two grounded capacitors has been presented. This filter circuit has several advantages, such as very low filter sensitivities to passive and active components, the use of grounded capacitors, and the use of single-ended OTA. The proposed configuration employs fewer active or passive components and can realize high-pass, low-pass and band-pass, simultaneously. Finally a chip can achieve voltage mode low-pass, high-pass and band-pass responses in the same configuration is presented.

Acknowledgements The authors would like to thanks the National Science Council and Chip Implementation Center of Taiwan, ROC, for financial and technical supporting.

References [1] Fabre A, Dauoub F, Duruisseau L, Kamoun M. High input impedance insensitive second-order filters implemented from

[7]

[8]

[9]

current conveyors. IEEE Trans Circ Syst-I: Fund Theory Appl 1994;41:918–21. Soliman AM. Current conveyors steer universal filter. IEEE Circ Dev Mag 1995;11:45–6. Soliman AM. Applications of the current feedback operational amplifiers. Analog Integ Circ Sig Process 1996;11:265–302. Senani R. Realization of a class of analog signal processing/signal generation circuits: Novel configurations using current feedback Op-Amps. Frequenz 1998;52:196–206. Singh AK, Senani R. A new four-CC-based configuration for realizing a voltage-mode biquad filter. J Circ Syst Comput 2002;11:213–8. Horng JW, Chiu WY, Wei HY. Voltage-mode high-pass, bandpass and low-pass filter using two DDCCs. Int J Electron 2004;91:461–4. Chiu W, Liu SI, Tsao HW, Chen JJ. CMOS differential difference current conveyors and their applications. IEE ProcCirc Dev Syst 1996;143:91–6. Bhaskar DR, Singh AK, Sharna RK, Senani R. New OTA-C universal current-mode/trans-admittance biquads. IEICE Electron Exp 2005;22:8–13. Sun Y, Fidler JK. Synthesis and performance analysis of universal minimum component integrator-based IFLF OTA-grounded capacitor filter. IEE Proc-Circ Dev Syst 1996;143:107–14.

Wen-Ta Lee was born in Taipei, Taiwan, R.O.C., in 1962. He received the B.S. and M.S. degree in Department of Electrical Engineering from National Cheng Kung University, in 1985 and 1989, respectively. He also received the Ph.D. degree in Department of Electrical Engineering from National Taiwan University, in 1995. He is now an Associate Professor in the Department of Electronic Engineering, National Taipei University of Technology. His research interests are in the areas of VLSI architectures for digital/analog communications, coding theory and signal processing. Yi-Zhen Liao was born in Taichung, Taiwan, R.O.C., in 1981. He received the B.S. degree from the Department of Electrical Engineering at Minghsin University of Science and Technology, Hsin Chu, in 2003 and M.S. degree from the Department of Electrical Engineering at Chung Yuan Christian University, Chung Li, in 2005. Since 2005, he has been working toward Ph.D. at the Graduate Institute of Computer and Communication, National Taipei University of Technology, Taipei, Taiwan. His research areas include active filter design for analog signal-processing applications and communication circuits design.