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Nickel nanoparticle deposition at room temperature for memory applications
Microelectronic Engineering 84 (2007) 1994–1997 www.elsevier.com/locate/mee
Nickel nanoparticle deposition at room temperature for memory applications E. Verrelli a, D. Tsoukalas a, K. Giannakopoulos b, D. Kouvatsos c, P. Normand c, D. E. Ioannou d a
National Technical University of Athens School of Applied Sciences, 15780 Zografou, Greece Inst. of Materials Science, NCSR Demokritos, NCSR Demokritos, 153 10, Aghia Paraskevi, Greece c Institute of Microelectronics, NCSR Demokritos d George Mason Univ., Fairfax VA 22030, USA
b
Abstract In this work we investigate the non-volatile memory behavior of Ni nanoparticles embedded within an insulating matrix. Nickel nanoparticles are deposited at room temperature by a new high-vacuum technique over a 4 nm tunneling thermal SiO2 layer followed by the deposition of HfO2 as a control insulator. Memory windows of ~1.5V are observed in MOS capacitors at gate pulse voltages of 8V. Charge retention for write and erase state clearly indicate long time charge storage behavior. Keywords: metallic nanoparticles; non volatile memory; PVD
1. Introduction Nanoparticle memories have made their point during last years as a possible solution to overcome the scaling issue of non-volatile memories (NVM). Metallic nanoparticles have been less explored than semiconductor nanoparticles as charge storage elements [1, 2]. In principle metal nanoparticles should present advantages over silicon nanocrystal memories. The higher electron affinity of several
Corresponding author. Tel.:+ 30 210 7721679; fax: +30 210 7723338. E-mail address:[email protected] (E.Verrelli)
0167-9317/$ - see front matter Ó 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2007.04.078
metals as compared with Si allows for engineering the potential well of the storage nodes in order to create an asymmetric barrier between Si channel and the storage nodes. The usual method to form metallic nanoparticles is based on the deposition of thin metallic films using evaporation on top of a tunneling thermal oxide followed by thermal annealing resulting in the formation of metallic nanoparticles. The density and size distributions of the nanoparticles depend on annealing conditions and the thickness of the deposited thin film [3]. The drawback of this technique is the need for relatively high temperature treatment that involves the risk for contamination of the silicon substrate. It also results
E. Verrelli et al. / Microelectronic Engineering 84 (2007) 1994–1997
in uncontrolled size distribution of the nanoparticles. In this work we are presenting results on the formation of nickel nanoparticles on a thin tunneling thermal SiO2 layer using a new room temperature nanoparticle manufacturing technique. 2. Experimental The nanoparticle deposition technique is based on a physical vacuum deposition (PVD) process. Particles are generated using a high-pressure magnetron sputtering device and carried away from the target area by the discharge gas into a condensation zone where nanoparticles are grown (fig. 1). The nanoparticles after being swept through this zone enter the chamber through a final aperture and they are soft-landed on the oxide surface [4].
1995
4 nm formed after dry oxidation of p-type silicon wafers at 850 ˚C. Then a layer consisting of nickel nanoparticles was deposited followed by the deposition of an insulating layer of HfO2 by RF reactive sputtering. High purity HfO2 target was used and deposition was performed either at room temperature or 300 ˚C under either argon flow or a mixture of argon/oxygen flow to a ratio 1:6. Deposition was performed at a pressure 8u10-3 mbar using an r.f. power of 200 W. Aluminum metal contacts were e-beam evaporated onto the backside of the silicon substrates and on the top of the deposited layers through a shadow mask to form MIS capacitors. An annealing step at 320 ˚C for 20 min in N2 was performed after finalizing fabrication for all samples. For each sample containing nanoparticles a reference sample with the same SiO2/HfO2 gate dielectric stack but without the nanoparticle layer was also fabricated. Characterization of charge storage within the layers was subsequently performed by C-V sweeps at 1 MHz using an Agilent 4284A capacitance meter.
Fig. 1. Diagram of the nanoparticle source.
(a)
Fig. 2. TEM plane view images of as deposited nanoparticles in two different conditions. The bar corresponds to 20 nm.
Using such a technique room temperature formation of nanoparticles becomes possible under high purity vacuum conditions. The tunneling oxide used in the present experiment is a thermal oxide of
(b) Fig. 3. (a) C-V characteristics for 10nm-thick HfO2 memory device. In the inset the C-V curves for the reference sample are shown. (b) Flat-band voltage shifts for 10nm thick HfO2 memory device under sweep bias operation.
1996
E. Verrelli et al. / Microelectronic Engineering 84 (2007) 1994–1997
3. Results and discussion Nanoparticles with size distributions of ± 20% and density distributions that can vary between 1010 cm-2 and 1012 cm-2 are formed. Minimum achieved size of the nanoparticles is 2 nm and maximum size 14 nm by proper variation of process parameters. These results have been obtained by Transmission Electron Microscopy imaging. Representative plane view images of deposited nickel nanoparticles with different size and density distributions are shown in Fig. 2. For our present experiments of MOS structures we have used Ni nanoparticles with average size 8 nm and density 5u1011 cm-2.
deposited HfO2 without any O2 flow during sputtering exhibit strong hysteresis and cannot be used efficiently as control dielectrics. On fig.3a and fig.4a we present C-V measurements obtained using the same tunneling oxide (4 nm thickness) and nanoparticle layer but with different thickness of HfO2 (10 nm and 25 nm respectively) deposited at 300 ˚C under Ar/O2 flow. In each of these figures the corresponding reference sample is presented for comparison. A clear effect resulting from the presence of nanoparticles is observed in both figures and should be noted that the hysteresis is counter clockwise indicating charging from the Si-substrate. No hysteresis is detected in the reference samples. From these data the corresponding memory windows are estimated and drawn in figures 3b and 4b as a function of voltage sweeps. As it can be seen the 25 nm thick HfO2 sample shows a larger and more symmetric window compared to the 10 nm HfO2 sample as a result of less leakage current from nanoparticles to the gate electrode. This is also confirmed by I-V measurements.
(a)
(b) Fig. 4. (a) C-V characteristics for 25nm thick HfO2 memory device. In the inset the C-V curves for the reference sample are shown. (b) Flat-band voltage shifts for 25nm thick HfO2 memory device under sweep bias operation.
Capacitance-voltage measurements of reference samples -not shown here- demonstrate that sputtering conditions at 300 ˚C under oxygen flow induce negligible hysteresis. Room- temperature or 300 ˚C
Fig. 5. Memory behavior for 25nm thick HfO2 memory device after application of positive and negative pulses of heights from 1V to 10V. pulse duration was set to 1s.
Memory behavior under pulse regime was also investigated for the 25nm thick HfO2 sample. In Fig. 5 the flat-band voltage shifts under program/erase (P/E) pulses (1s duration) is presented. For positive pulses (write state) and negative pulses (erase state) carrier injection (electrons and holes respectively) into the NCs from the Si-substrate takes place trough the SiO2 tunneling oxide. For electrons and holes a clear plateau is
E. Verrelli et al. / Microelectronic Engineering 84 (2007) 1994–1997
found above +8V or -6V respectively. The observed saturation is attributed to the coulomb blockade effect taking place while Ni nanoparticles are charged. Holes charging is much more abrupt than electrons.
Fig. 6. Charging behavior with pulse duration for the 25nm thick HfO2 memory device. Pulse widths from 10ms to 3s and height 8V for both positive and negative pulses.
and the pulse width was observed. The latter should suggest a slower charging of the write state with respect to the erase state. However, interface state densities and I-V measurements, not shown here, reveal the presence of a broad electron state around +0.2eV from mid-gap energy and relatively high leakage currents that may contribute to the observed lowering of electrons charging speed. In Fig. 7 the charge retention characteristic at room temperature is shown. The device was programmed in the write or erase state and then the flat-band voltage shift was monitored for at least 12h. An abrupt loss of charges that correspond to 0.2-0.3V was observed in the very first seconds of the measurements and can be ascribed to interface states and/or presence of leakage paths. In any case, extrapolating, the 2 states remain distinguished for 10 years time period as requested for non-volatile memory devices. 4. Conclusions We have demonstrated charge storage in nickel nanoparticles deposited on thin SiO2 films at room temperature by a PVD technique through the fabrication and electrical measurements of MIS structures in which HfO2 is used as the control insulator. Memory windows of ~1.5 V for applied gate voltages less than 8 V have been measured. The results reported herein show the potential of the PVD technique for controlled growth of nanoparticles for use in non-volatile memory applications. Acknowledgements We acknowledge financial support by the Greek GSRT. References
Fig. 7. Charge retention characteristics at room temperature for the 25nm thick HfO2 memory device.
In Fig. 6 the P/E characteristics for pulses of ±8V and width ranging from 10ms to 3s is presented. It was found that the erase state reaches a plateau for pulses widths above 10ms while for the write state a linear dependence between the flat-band voltage shift
[1] C. H. Lee, J. Meteer, V. Narayanan, E. C. Kan, J. Electronic Mater. 34 (2005) 1. [2] J. J. Lee, Y. Harada, J. W. Pyun, D. L. Kwong, Appl. Phys. Lett. 86 (2005) 103505. [3] J. Dufourcq, P. Mur, M. J. Gordon, S. Minoret, R. Coppard, T. Baron, Materials Science and Engineering: C, in press (available in sciencedirect). [4] A. H. Kean and L. Allers, NSTI Nanotech Conference Proceedings, Boston, May 2006.
1997
Nickel nanoparticle deposition at room temperature for memory applications E. Verrelli a, D. Tsoukalas a, K. Giannakopoulos b, D. Kouvatsos c, P. Normand c, D. E. Ioannou d a
National Technical University of Athens School of Applied Sciences, 15780 Zografou, Greece Inst. of Materials Science, NCSR Demokritos, NCSR Demokritos, 153 10, Aghia Paraskevi, Greece c Institute of Microelectronics, NCSR Demokritos d George Mason Univ., Fairfax VA 22030, USA
b
Abstract In this work we investigate the non-volatile memory behavior of Ni nanoparticles embedded within an insulating matrix. Nickel nanoparticles are deposited at room temperature by a new high-vacuum technique over a 4 nm tunneling thermal SiO2 layer followed by the deposition of HfO2 as a control insulator. Memory windows of ~1.5V are observed in MOS capacitors at gate pulse voltages of 8V. Charge retention for write and erase state clearly indicate long time charge storage behavior. Keywords: metallic nanoparticles; non volatile memory; PVD
1. Introduction Nanoparticle memories have made their point during last years as a possible solution to overcome the scaling issue of non-volatile memories (NVM). Metallic nanoparticles have been less explored than semiconductor nanoparticles as charge storage elements [1, 2]. In principle metal nanoparticles should present advantages over silicon nanocrystal memories. The higher electron affinity of several
Corresponding author. Tel.:+ 30 210 7721679; fax: +30 210 7723338. E-mail address:[email protected] (E.Verrelli)
0167-9317/$ - see front matter Ó 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2007.04.078
metals as compared with Si allows for engineering the potential well of the storage nodes in order to create an asymmetric barrier between Si channel and the storage nodes. The usual method to form metallic nanoparticles is based on the deposition of thin metallic films using evaporation on top of a tunneling thermal oxide followed by thermal annealing resulting in the formation of metallic nanoparticles. The density and size distributions of the nanoparticles depend on annealing conditions and the thickness of the deposited thin film [3]. The drawback of this technique is the need for relatively high temperature treatment that involves the risk for contamination of the silicon substrate. It also results
E. Verrelli et al. / Microelectronic Engineering 84 (2007) 1994–1997
in uncontrolled size distribution of the nanoparticles. In this work we are presenting results on the formation of nickel nanoparticles on a thin tunneling thermal SiO2 layer using a new room temperature nanoparticle manufacturing technique. 2. Experimental The nanoparticle deposition technique is based on a physical vacuum deposition (PVD) process. Particles are generated using a high-pressure magnetron sputtering device and carried away from the target area by the discharge gas into a condensation zone where nanoparticles are grown (fig. 1). The nanoparticles after being swept through this zone enter the chamber through a final aperture and they are soft-landed on the oxide surface [4].
1995
4 nm formed after dry oxidation of p-type silicon wafers at 850 ˚C. Then a layer consisting of nickel nanoparticles was deposited followed by the deposition of an insulating layer of HfO2 by RF reactive sputtering. High purity HfO2 target was used and deposition was performed either at room temperature or 300 ˚C under either argon flow or a mixture of argon/oxygen flow to a ratio 1:6. Deposition was performed at a pressure 8u10-3 mbar using an r.f. power of 200 W. Aluminum metal contacts were e-beam evaporated onto the backside of the silicon substrates and on the top of the deposited layers through a shadow mask to form MIS capacitors. An annealing step at 320 ˚C for 20 min in N2 was performed after finalizing fabrication for all samples. For each sample containing nanoparticles a reference sample with the same SiO2/HfO2 gate dielectric stack but without the nanoparticle layer was also fabricated. Characterization of charge storage within the layers was subsequently performed by C-V sweeps at 1 MHz using an Agilent 4284A capacitance meter.
Fig. 1. Diagram of the nanoparticle source.
(a)
Fig. 2. TEM plane view images of as deposited nanoparticles in two different conditions. The bar corresponds to 20 nm.
Using such a technique room temperature formation of nanoparticles becomes possible under high purity vacuum conditions. The tunneling oxide used in the present experiment is a thermal oxide of
(b) Fig. 3. (a) C-V characteristics for 10nm-thick HfO2 memory device. In the inset the C-V curves for the reference sample are shown. (b) Flat-band voltage shifts for 10nm thick HfO2 memory device under sweep bias operation.
1996
E. Verrelli et al. / Microelectronic Engineering 84 (2007) 1994–1997
3. Results and discussion Nanoparticles with size distributions of ± 20% and density distributions that can vary between 1010 cm-2 and 1012 cm-2 are formed. Minimum achieved size of the nanoparticles is 2 nm and maximum size 14 nm by proper variation of process parameters. These results have been obtained by Transmission Electron Microscopy imaging. Representative plane view images of deposited nickel nanoparticles with different size and density distributions are shown in Fig. 2. For our present experiments of MOS structures we have used Ni nanoparticles with average size 8 nm and density 5u1011 cm-2.
deposited HfO2 without any O2 flow during sputtering exhibit strong hysteresis and cannot be used efficiently as control dielectrics. On fig.3a and fig.4a we present C-V measurements obtained using the same tunneling oxide (4 nm thickness) and nanoparticle layer but with different thickness of HfO2 (10 nm and 25 nm respectively) deposited at 300 ˚C under Ar/O2 flow. In each of these figures the corresponding reference sample is presented for comparison. A clear effect resulting from the presence of nanoparticles is observed in both figures and should be noted that the hysteresis is counter clockwise indicating charging from the Si-substrate. No hysteresis is detected in the reference samples. From these data the corresponding memory windows are estimated and drawn in figures 3b and 4b as a function of voltage sweeps. As it can be seen the 25 nm thick HfO2 sample shows a larger and more symmetric window compared to the 10 nm HfO2 sample as a result of less leakage current from nanoparticles to the gate electrode. This is also confirmed by I-V measurements.
(a)
(b) Fig. 4. (a) C-V characteristics for 25nm thick HfO2 memory device. In the inset the C-V curves for the reference sample are shown. (b) Flat-band voltage shifts for 25nm thick HfO2 memory device under sweep bias operation.
Capacitance-voltage measurements of reference samples -not shown here- demonstrate that sputtering conditions at 300 ˚C under oxygen flow induce negligible hysteresis. Room- temperature or 300 ˚C
Fig. 5. Memory behavior for 25nm thick HfO2 memory device after application of positive and negative pulses of heights from 1V to 10V. pulse duration was set to 1s.
Memory behavior under pulse regime was also investigated for the 25nm thick HfO2 sample. In Fig. 5 the flat-band voltage shifts under program/erase (P/E) pulses (1s duration) is presented. For positive pulses (write state) and negative pulses (erase state) carrier injection (electrons and holes respectively) into the NCs from the Si-substrate takes place trough the SiO2 tunneling oxide. For electrons and holes a clear plateau is
E. Verrelli et al. / Microelectronic Engineering 84 (2007) 1994–1997
found above +8V or -6V respectively. The observed saturation is attributed to the coulomb blockade effect taking place while Ni nanoparticles are charged. Holes charging is much more abrupt than electrons.
Fig. 6. Charging behavior with pulse duration for the 25nm thick HfO2 memory device. Pulse widths from 10ms to 3s and height 8V for both positive and negative pulses.
and the pulse width was observed. The latter should suggest a slower charging of the write state with respect to the erase state. However, interface state densities and I-V measurements, not shown here, reveal the presence of a broad electron state around +0.2eV from mid-gap energy and relatively high leakage currents that may contribute to the observed lowering of electrons charging speed. In Fig. 7 the charge retention characteristic at room temperature is shown. The device was programmed in the write or erase state and then the flat-band voltage shift was monitored for at least 12h. An abrupt loss of charges that correspond to 0.2-0.3V was observed in the very first seconds of the measurements and can be ascribed to interface states and/or presence of leakage paths. In any case, extrapolating, the 2 states remain distinguished for 10 years time period as requested for non-volatile memory devices. 4. Conclusions We have demonstrated charge storage in nickel nanoparticles deposited on thin SiO2 films at room temperature by a PVD technique through the fabrication and electrical measurements of MIS structures in which HfO2 is used as the control insulator. Memory windows of ~1.5 V for applied gate voltages less than 8 V have been measured. The results reported herein show the potential of the PVD technique for controlled growth of nanoparticles for use in non-volatile memory applications. Acknowledgements We acknowledge financial support by the Greek GSRT. References
Fig. 7. Charge retention characteristics at room temperature for the 25nm thick HfO2 memory device.
In Fig. 6 the P/E characteristics for pulses of ±8V and width ranging from 10ms to 3s is presented. It was found that the erase state reaches a plateau for pulses widths above 10ms while for the write state a linear dependence between the flat-band voltage shift
[1] C. H. Lee, J. Meteer, V. Narayanan, E. C. Kan, J. Electronic Mater. 34 (2005) 1. [2] J. J. Lee, Y. Harada, J. W. Pyun, D. L. Kwong, Appl. Phys. Lett. 86 (2005) 103505. [3] J. Dufourcq, P. Mur, M. J. Gordon, S. Minoret, R. Coppard, T. Baron, Materials Science and Engineering: C, in press (available in sciencedirect). [4] A. H. Kean and L. Allers, NSTI Nanotech Conference Proceedings, Boston, May 2006.
1997