Nitride Makes its mark

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World Abstracts on Microelectronics and Reliability

PLAs replace R O M s for logic designs. D. MRAZEK and M. MORmS. Electronic Design 66 (Oct. 1973L The availability of IC programmable logic arrays (PLA), in both MOS and bipolar versions, offers designers an alternative to the use of R O M s for complex decoding of control functions. Compared to other types of logic, the use o f a PLA requires fewer levels of logic to provide the same functions. The PLA can handle large memory arrays easily and more efficiently. More-over, the LSI circuit cuts costs associated with component assemblies, PC boards and connectors. Application of Low-Power current mode logic. G. D. M. VERMEIRE. Philips Telecomm. Rev. 31, 188 (Dec. 1973). LowPower C M L , a family of high-speed low-dissipation digital elements, features high relative noise margins, impedance levels which are well matched to external wiring, and low signal levels which are favourable situated with respect to earth, thereby allowing fast signal transmission with simple wiring. Because the ICs take a constant supply current, power distribution is straightforward. This combination of favourable properties keeps the assembly cost per IC low, which is of particular value for large digital systems. Low-power current mode logic. R. J. M. VERBEEK. Philips Telecomm. Rev. 31, 180 (Dec. 1973). The low-power current mode logic developed by Philips offers components which are eminently suitable for large systems such as the new generation of digital telephone exchanges now under development. It features low energy consumption and a high relative noise margin: an output impedance well suited to match external cabling: and it permits the same technique to be used for small-scale as well as large-scale integration. First oxide-isolated C - M O S circuits cut chip area by onethird. Electronics 33 (10 Jan. 1974). The benefits of passive isolation, previously available only in memory circuits, are now being offered in logic circuits as well. Fairchild Semiconductor's Isoplanar C - M O S standard logic family provides pin-to-pin compatible with the standard 4000 series but in a format almost one-third the size of conventional 4000 C-MOS. This cuts the chip size of a typical C - M O S logic chip a quad gate down from about 3000 2000 square mils. Silicon wafer processing by application of spun-on doped and undoped silica layers. J. A. BECKER. Solid St. Electron. 17, 87 (1974). Doped and undoped silicafilms applied in liquid form have been used as diffusion sources for IC wafer processing. Data of diffusions are presented which were carried out on unmasked wafers to find out the appropriate diffusion conditions for isolation, base and emitter diffusion. 6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S , Effects of bulk trapping on the memory characteristics of thick-oxide M N O S variable-threshold capacitors. G. W. TAYLOR and J. G. SIMMONS. Solid St. Electron. 17, 1 (1974). Charge-storage measurements have been performed at room temperature on thick-oxide M N O S structures using an automatic measuring system which allows a detailed and quite accurate investigation of the hysteresis loops (flat-band voltage versus stress voltage characteristics) of such devices. The experimental data have revealed several anomalous features, previously unreported in the literature, which are

Emphasis is placed on the cost reduction in circuit production which is possible when using doped and undoped spun-on diffusion sources. This is achieved by the possibility of drastically reducing the a m o u n t of high temperature processes necessary for bipolar circuits. The simplified diffusion processes have been used to produce various integrated circuits where all diffusions necessary were carried out with doped and undoped silicafilm. A production reactor for continuous deposition of silicon dioxide. W. C. BENZING, R. S. ROSLER and R. W. EAST. Solid St. Technol. 37 (Nov. 1973). A new continuous processor for the deposition of silicon dioxide films by chemical vapor deposition is discussed. The equipment and technique are described in detail. Data is presented on the uniformity of sheet resistivity, defect density, and economics. Advantages claimed for the system include high throughput, low cost, excellent film uniformity, low defect density, and ease of automation. Deionized Water for Integrated Circuit Fabrication. W. G. SAVOLA. Solid St. Technol. 47 (Nov. 1973). The fabrication of integrated circuits is highly dependent on ultra-pure deionized water to remove ionic and physical particulate contamination. The criteria for high purity water are defined in terms of resistivity, particle size, and bacteria count. The production of high purity water is discussed with particular emphasis on reverse osmosis and mixed bed deionizers. Other elements of a high purity deionized water system are discussed and specific design recommendations are made. A test structure for controlling the process of manufacturing M O S circuits. M. HAPKE and G. HELMS. NachrichtentechnikElektronik 23 (1973) 10, pp. 393,394, 1 fig. (in German). in addition to the measurement of component parameters basic quantities immediately reacting on technological variations can be determined by the structure, such as density of the state of surface, path resistances, breakdown voltages of diode structures, contact resistances, field threshold voltages, etc. Thus causes can to a certain degree be determined. Experiences with the use of the structure are mentioned. Nitride makes its mark. J. GOSCH. Electronics 72 (24 Jan. 1974). Although the promise of nitride-doped M O S devices (MNOS) has yet to be realized in the form of M N O S products, nitride technology is finding its way into an assortment of devices. What semiconductor designers are doing is taking advantage of the reprogramable and nonvolatile properties of the technology in conjunction with well established product technology. SYSTEMS

AND EQUIPMENTS

very general properties of double-layer devices. It is found that the initial hysteresis loop of a virgin device is very similar to the "conventional'" hysteresis loop, with flat bottoms and tops and steeply-rising sides. However, the second and subsequent hysteresis loops show dramatic changes in the flat-band voltage in the formerly flat regions. The results are interpreted in a selfconsistent manner, in terms of trapping p h e n o m e n a throughout the bulk of both insulator regions. The trapped charge is found to produce strong internal fields that cause redistribution of the trapped charge in both the