Non volatile memories-status and emerging trends

Microelectronic Engineering 15 (1991) 603-612 Elsevier

NON

VOLATILE

603

MEMOR1F~S-STATUS

AND

EMERGING

TRENDS

M.Melanotte, R.Bez and G.Crisenza SGS-THOMSON Microelectronics, Central R&D Technology, via C.Olivetti 2, 20041 Agrate Brianza (MI), Italy Abstract Actual scenario and new trends in non volatile memories are presented, considering market, applications, scaling requirements, reliability and manufacturability constrains. EPROM and Flash-EEPROM are particularly reviewed, as the devices better representing speed and density progress, the two leading aspects along non volatile memories (NVM) evolution.

1. NVM SCENARIO After a critcal year in 1990, MOS memories are expected to increase constantly in the near future. Their total market is forecasted tripling from 1991 to 1996 (fig.l). More than half of this market is covered by DRAM, and this situation will not change in the future. NVM market represents however a relevant part, with an expected growth rate similar to the total. Considering only NVM, EPROM are today the most diffused (fig.2). Together with OTP (One Time Programmable) they actually account for more than 65 % of the NVM market. This dominant position will be severely threatened by flash EEPROM, which are expected to have an important rise in the next five years.

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Fig.2: actual and forecasted (1995) NVM market shares

0167-9317/91/$3.50 © 1991 - Elsevier Science Publishers B.V. All rights reserved.

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Non volatile memories

NVM main applications are reviewed in fig.3 together with their key requirements. Laser printer high density I speed Computer segment is the most important, Dtek D r i e r s low ooet PC (286/:1861446) It~:ro~ing t p l t d I den'Jty (:XWPUTER followed by consumer and telecom (fig.4). Work Btatlonl ~ r y high speed (DOg-bit -qae) Note-book ¢olaputere 6 V only / lOW pOV~t To satisfy such a broad range of utilizations Disk repteoement high density / endurm~oe and needs, the NVM products (fig.5) spread [ m~imilo high denalty / speed from the low cost R I M to the high Mo'lema ~ t y high speed TELEGOM Cellutlw Phones extended temperature tinge functionality ASM (Application Specific Memories), offering the best trade off high dentally Prig. Controllers field progrlum INDUSTRIAL Gopy maohlnee Melmuf. ineL low power between cost and performances. R I M is a transistor array in which the program Auto tuning extended temperature range AUl10MOllVE[ MSl) display high density code is set in wafer processing. R I M is less expensive in manufacture than any other l low coet VCR " CD h4oh density High end TV NVM, but is not flexible (not reprogrammable). These considerations focus R I M to low cost volume Fig.3:NVM applications and requirements applications, where design is definitively set. R I M density evolution typically follows technological scaling trends, and will not be treated in this paper. At the high functionality end of NVM category, EEPROM did not confirm the large growth foreseen in the past, due to their intrinsic difficulty in achieving high density and good manufacturability. Their market is not expected to grow with the same rate of the other NVM products, and will remain restricted to applications requiring low density and high flexibility (thousands of cycles on board reprogrammability, byte erasing, low power consumption), compatibles with their higher cost. HIGH EUNCTIONALITY ASM 50

EEPROM

3O

FLASH-EEPBOM

BYTE REWRITE CAPABILITY L O W E R DENSITY

ELECTRICALLY ERASABLE NEAR EPROM COST HIGH DENSITY

2O

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10

0 COMPUTER

TELECOM

CONOUMERAUTOMOTIVEINDUIrrRIAL

F~t1~1

MILITARY

1~1~8

NOT ELECTRICALLY ERASABLE

OTP

NOT ERASABLE

ROM

NOT REPROGRAMMAflLE

COST

Fig.4: segment of application (% of total NVM market)

Fig.5: flexibility and cost classification of NVM devices

Before considering new cell concepts, the stacked gate cell (SGC) is reviewed in details, as being the most commonly used in EPROM and flash products.

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M. Melanotte et a L / Non volatile memories

contact metal Iloa!inggnte

controlgateI

,oteroo,y dielectric

gateoxide~ [

floating gate

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Fig.6: layout of a T-shaped SGC (a), vertical cross-section along (b) and perpendicular (c) to the channel; equivalent capacitive circuit (d)

2. THE STACKED GATE CELL EPROM and flash EEPROM SGC are n-channel MOS transistors with an additional floating gate (FG). Both are programmed by channel hot electron injection, but are erased by different physical mechanisms: photoelectric effect the first and FowlerNordheim tunneling through a thin gate oxide the latter. Before analyzing in details writing operations, the conventional T-shaped layout (fig.6a) and the architecture (fig.6b and fig.6c) of the SGC will be briefly described. Fig.6a shows the smallest unit repeated in the array, defined by: in the x direction the metal pitch (contact size and enclosure by metal, metal to metal space); in the y direction the source line width, source line to word line space, gate length, gate to contact distance, contact size. Fig.6b and fig.6c sketch the vertical cross-sections along and perpendicular to the channel. The FG and surrounding dielectrics (thermal oxides or ONO) are clearly shown. The arsenic source/drain junctions are self-aligned to the gate and symmetric in the EPROM ceil, while a phosphorous diffusion is added to the source in the flash cell, to allow high voltage during erasing. Usually a boron dose, higher than in transistors, is implanted in the channel to prevent punch through and to increase programming efficiency, enhancing multiplication. A complete study of the SGC is based on the exact knowledge of the FG potential, VFO. Considering the SGC as a simple equivalent capacitive circuit (fig.6d), it is quite easy to calculate VFG as a function of the bias conditions at the other nodes. Defining the total FG capacitance CT as CT = Cpp + CD + Cs + CB, where ~ is the capacitance of

606

M. Melanotte et aL / Non volatile memories

FG to the j-electrode and Cpp is the interpoly capacitance, it can be shown by trivial considerations that:

VFG=~tGVcG+aDVD+asVs+OtBVB+~T;

A VT=VT-VTo =-

(1);(2)

Q

Cep

being the coupling ratio a-j = C:/C.~, l Q the charge stored in the FG, VT and VT0 the programmed and virgin thresholdj voltages. Once the coupling ratios are known, the SGC electrical characteristics are those of a conventional MOS transistor, whose gate voltage is given by eq.(1). The precise experimental determination of aj is not easy, and only indirect measurement methods are feasible [1-5]. ,

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2.1 Programming

Channel hot electron injection [6-7], which is a degrading effect in transistors [8-10], must be enhanced in the cell to improve gate current IG, i.e. programming efficiency [1112]. In fig.7 the SGC programming curves are reported in a log-lin scale. The cell is programmed applying positive pulses to the control gate (CG) and the drain. From the programming curve it is possible to derive the IG-VFG plot (fig.8), which allows a better understanding of the transient behavior of the cell. As explained in [11], two separate regions are present in the IG-VFG plane. For VFG> I'D, the injection limited region, the energy distribution of hot electrons is reduced by the low lateral electric field, even if the vertical electric field is favorable to injection. For VFG< I'D, the electrode limited region, the hot electron distribution is confined in the lateral field region, where the potential barrier is higher. An important point in fig.8 is defined by VFG= VD. From eq. (1) and (2) follows that:

VF~=~V c6÷.DVD-,~oA V~=VD

(3)

where A VT*= A VT(t*) is a critical parameter for the cell [4]. t* can be considered as representative of the programming speed of the cell. The effects of device parameters and applied voltages can be easily analyzed considering their impact on the coupling

M. Melanotte et al. / Non volatile memories

607

ratios and consequently on eq.(3). As the programming speed is a key issue for the device, all the effects depending from the array organization must be carefully considered. As shown in fig.7, series resistances on source and drain can dramatically affect programming [13]. 2.2 Erasing

EPROM cell erasing is obtained by UV light irradiation. The electrons stored into the FG are excited by incident photons and can escape from the potential well [14]. Erasing time depends also on the transmittance of the used dielectrics, and ranges in the order of minutes. Flash cell erasing is achieved applying a high positive pulse to the source. Because of the high electric field across the thin gate oxide, electrons can tunnel from the FG to the source. During erasing operation the drain is kept floating, to prevent large channel current. Nevertheless substrate current arises due to band-to-band tunneling generation [15-19], because of the large electric field induced in the silicon surface. This leakage current could limit erasing speed and endurance reliability, and must be accurately faced by design organization. Flash erasing time ranges between milliseconds and seconds. 2.3 Cell working area

The functionality of a cell is based not only on writing efficiency, but on the robustness 4 to parasitic effects (drain turn-on, snap. . . . . . . -? . . . . . . 7~ ~-. . . . . . . . . back) and disturbs (soft-programming 8 t / ~" i / /g" during reading or soft-erasing during t / .= , ?" writing [20]). A convenient ambient to e ,, 2 compare positive performances (like programming speed and reading current) 40.4 0.6 0.8 1.0 1.2 and disturbs, is the gate length drain Gate length (/~m) voltage plane [21](fig.9), as these are the Fig.9: working area of a 0.8 ttm technology SGC main variables determining cell electric (rectangle). 1-programming speed, 2-reading current, 3-snap back, 4-drain turn on, 5-soft fields. The cell working area is confined by programming, 6-soft erasing the forbidden regions of active and parasitic effects, thus defining the maximum admitted latitude for the considered parameters. The same picture can be drawn also for a flash, considering that the writing disturbs are enhanced, as the gate oxide is thinner. Furthermore for a flash cell many programming/erasing cycles (up to 104-105) must be guaranteed without degrading the electrical characteristics. ~" zo

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3. SCALING DOWN In the semiconductor memory technology there has always been a constant effort to accommodate more cells per unit of wafer area. EPROM density in the last decade has quadrupled every three years (fig.10). In developing high densities, requiring high performance dielectrics and high voltage architectures, EPROM have been technology drivers. These technologies have been adopted by many other products, like microprocessors with memories embedded on chip. To give an idea of what reducing cell

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M. Melanotte et al. / Non volatile memories

area means, it can be observed that every three generations the EPROM cell fits into the contact hole area of its progenitor. As process complexity increases, equipment requirements in terms of process control become more severe, due also to the adoption of larger wafer size. From an economical point of view, scaling down allows redesign in a new technology of previous memory sizes, reducing costs and increasing profitability of products that have already reached maturity in the market. 3.1 Sealing down rules The practical constrain of keeping 10OO the same 5 V power supply, while scaling transistor sizes, stresses the materials constituting the devices. The high voltage required for programming the cells further complicates the situation. Actually, cell scaling down methodology [2226] is between the constant field [27] 10 tO 1;976 1976 1981 11964 1987 1990 1993 1996 and the constant voltage [28] scaling I I t YEAR I I I . MEMORY CAPACITY 16K 84K 260K 1M 4M 116M 04M (bit) down rules. As reported in [22-23], Fig. 10:EPROM evolution:density,chip sizeand access time device dimensions and writing voltage essentially follow the constant field scheme, while reading voltage follows the constant voltage one. With programming voltages properly scaled and oxides fabricated with the requisite integrity, the reading voltage is not particularly critical. Furthermore avoiding to scale reading voltage substantially increases reading current and speeds up access time. The more stressed components in terms of electric field across gate oxide are row decoder transistors, switching the high voltage during writing. In the flash cell, gate oxide scaling is limited, besides direct tunneling, by high temperature bake retention degradation and by stress induced leakage current increase after repeated program/erase cycles. Practically the erase voltage scaling must insure a constant electrical field across the gate oxide. GHIP I I Z E ( m m ~ )

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3.2 Maintaining reliability Data retention for typically 20 years is a basic requirement for NVM [29-33]. A programmed cell has only some tenths of thousands of electrons in the FG. Thus the surrounding oxides must guarantee a leakage current of a few electrons per day. Considering data retention, electronic and ionic processes must be distinguished. Electronic processes indicate the escape of the electrons, stored in the FG, through oxide defects. This failure mechanism typically affects single bits, randomly located in the memory array. Dependence on temperature shows activation energy of few tenths ofeV, while leakage current is an exponential function of the electric field. Ionic processes affect data retention by screening and compensating the FG stored charge. Charge loss has been associated with alkali metals contamination. Activation energies higher than 1 eV are typically found, while drift diffusion transport mechanism rules mobile ions current. Scaling down allows to achieve the same AVT reducing the FG stored charge (due to the decrease of Cpp in eq.(2)). This will make NVM more sensible to ion

609

M. Melanotte et al. / Non volatile memories

contamination. Fig. 11 shows charge loss as a function of CG-FG overlap area, with same interpoly and gate oxides. Charge loss scales up with dimensions and with decrease of the phosphorous content of the interlevel dielectric [34]. As device geometries scale defectivity becomes a dramatic issue [35-36]. As an example fig. 12 reports defectivity targets for the main critical layers. Technology has to be tuned to meet specifications, and a continuous tightening of process control is mandatory. lOOO II

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Mblt

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Fig.12: defectivity targets for the main critical layers

Finally usual reliability failure modes (electromigration, hot electrons, etc.) must be considered in a more severe environment, due to high voltage programming and high temperature (250"C) bake test for data retention.

3.3 Improving speed As memory density rises, the increase in bit line and word line parasitic capacitance and resistance affects speed. Significant delay times offset the improvement in transistors driving capability and cell reading current. Therefore an important issue is array partitioning, which means reducing the minimum decoded array and consequently parasitic effects. Of course array partitioning is paid in terms of chip size, so that the best trade off between performance, cost and application must be carefully evaluated. As an example two state of the art NVM arrays realized with the same technology are shown in fig. 13, one emphasizing speed and the other the chip size. In the future it is likely that NVM technology will split in high density oriented architectures, and in high speed oriented devices. 4. ALTERNATIVE CELLS AND TECHNOLOGIES As discussed in previous sections design rules shrink enhances reliability problems and reduces manufacturability latitude. Thus efforts are dedicated in finding new solutions to contain chip size increase and keep it compatible with manufacturability limits. Basically this goal can be achieved following two lines (in many cases both contemporary): a) innovative technologies; b) alternative cells architectures. Improved SGC configurations have been proposed, selfaligning either the source line [37], or the drain contact [38] to the gate (fig. 14). Double metal use is also beginning to

610

M. Melanotte et aL / Non volatile memories

IE:E Fig. 13: same capacity memory arrays with different organizations: impact on Chip size

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Fig.14: SGC cell with drain contact selfaligned to the drain [38]

appear on EPROM and flash devices[39], allowing a consistent chip size reduction in periphery, and a decrease of parasitic RC if used in the array to shunt bit lines or word lines. Solutions have been alsO proposed to utilize refractory materials as local interconnections [38]. DrawbacKs of following this line are the cost and the risk of affording new complex process steps. The advantage is that, as the cell concept remains unchanged, once technological difficulties are overcome, cell implementation in the array and design organization are straigthforward, keeping the same logic of previous generation products.

control gate

floating gate

Floating Poly

W

I.-/ Source

Bit Line

bur~ed n+ hne

Fig.15:buried bit line cell [42]

Fig.16:split-gate cell [45]

A different approach has been also verified, essentially consisting in a different cell organization in the army. The purpose is to save space, not only by shrinking design rules, but also eliminating as far as possible contacts and alignment tolerances. These army configurations are generally referred to as virtual ground (VG) because the source is not fixed and connected to ground like in the classical organization, or as "contactless", due to their great reduction in contact number. Among these configurations are the ACE cell [40], the buried bit line cell [41] (fig.15), the SFOX cell [42], the FACE flash cell [43]. All these approaches offer the advantage of realizing a small cell with more relaxed design rules than would be needed by a SGC of the same size. As a drawback must be

M. Melanotte et al. / Non volatile memories

611

considered the impact on circuit design, due to the necessity of decoding or at least precharging the source, and the increased RC of the bitlines, due to longer n + diffusions. Design modifications can impact on array efficiency. Moreover these VG approaches usually result in a more rectangular cell shape compared to SGC. Decoder insertion in the cell pitch becomes more critical, so that more aggressive design rules are necessary in the periphery, unless decoder stretch is accepted, again loosing in area. A somewhat different solution is that of asymmetric cells, like the ALDS [44] and the split gate [45] (fig. 16). Their built-in asymmetry allows the use of a less complex decoding organization even if the cells are arranged in a contactless army. It must be noted however that such cells are not flash compatible if no additional complexity is added, as the source is not coupled to the FG (split-gate cell), or is coupled by a low doped region (ALDS) which would induce voltage drop during erase. To conclude, up to now many alternative cell architectures have been proposed, but few have been transferred to real production. Considering speed, cost per bit and flash compatibility, the SGC with some innovative steps and with use of double metal is likely to remain the best candidate for the near future. Contact technology and multiple interconnections will set the pace of this evolution. Technological development is a challenge which cannot be avoided, if a broad range leading position in the semiconductor market, and not only some niche sectors, has to be reached and maintained. 5. FUTURE EMERGING TRENDS Flash high versatility raises the question if this device will substitute actual EPROM dominant position in the NVM market. As EPROM combines ROM density and program flexibility, flash links electrical erase capability with EPROM-like density. This in-system reprogrammability shortens the time to market: code changes in prototypes can be made in short time and board updates can be done without disassembly. A large number of applications can be foreseen in automotive, telecom and industrial sectors. Particularly the growth in the segment of portable, lap top and palm-size computers is likely to become a great opportunity for flash. Disks require volatile memory download for program execution. Flash could replace both the mass storage and this redundant volatile memory. Few years ago it seemed that EEPROM higher versatility would have greatly reduced EPROM market. Tunnel oxide defectivity, manufacturability and larger cell size precluded this success, as EEPROM contended to EPROM same application field with higher cost per bit. Flash are now in a better position, as high density is achievable, and compared to EPROM a cheaper (plastic) package is used. This optimistic forecast must be balanced with the actual higher process and testing costs. Especially this last issue is becoming more relevant as memory capacity increases. Another constrain could arise from power supply reduction. Tunneling electric field does not scale and direct tunneling limits further thin oxide scaling. Youth problems have still to be solved and easy manufacturability demonstrated, before flash achieves its challenging goal. The more likely scenario is anyway that EPROM will not be cancelled, even if their field will be partially eroded, as they will conserve a lower cost per bit, and that the SGC

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will remain the most used structure. A unique technological development will result in both flash and EPROM future high density products. ACKNOWLEDGEMENTS The authors are grateful to B.Beverina for helpful support and advise. REFERENCES [I ] M.Wada, S.Mimura, H.Nihira, H.Iiuza, IEDM Tech. Dig.,2.5,38, 1980 [2 ] A.Kolodny, S.T.Nieh, B.Eitan, J.Shappir, IEEE Trans. El. Dev., 33,835, 1986 [3 ] K.Prall, W.I.Kinney,J.Macro, IEEE Trans. El. Dev., 34, 2463, 1987 [4 ] R.Bez, E.Camerlenghi, D.Cantarelli, L.l~vazzi, G.Criseaza, IEDM Tech.Dig.,5.3.1,991990 [5 ] A.Roy, R.Kazerounian, B.Eitan, llth NVM Workshop, Monterey (CA) 1991 [6 ] C.Hu, IEDM Tech. Dig, 2.4,22, 1979 [7 ] P.K.Ko, R.S.MulIer, C.Hu, IEDM Tech. Dig.,26.3,600, 1981 [8 ] K.K.Ng,J.W.Taylor, IEEE Trans. El. Dec., 30, 871, 1983 [9 ] B.Doyle, M.Bourc~rie, C.Bergonzoni, R.Benecchi, et aI.,IEEE Trans. El. Dev., 37, 1969,1990 [I0] C.Bergonzoni, G.Dalla Libera, A.Nannini, ESSDERC 90, 3CI, 245, 1990 [11] B.Eitan, D.Frohman-Bentchkowsky, IEEE Trans. El Dev., 28, 328, 1981 [12] C.Fiegna, F.Venturi, M.Melanotte, E.Sangiorgi, B.Ricco', IEEE Trans. El. Dec. 38,603, 1991 [13] R.Bez, D.CantareUi, P.Cappelletti, A.ManreUi, L.Ravazzi, ESSDERC 90, 2C8, 165, 1990 [14] R.Katznelson, D.Frohman-Bentchkowsky, IEEE Trans. El. Dev., 27, 1744, ,1980 [15] T.Y.Chan, J.Chen, P.K.Ko, C.Hu, IEDM Tech. Dig., 31.3,1987 [16] E.Takeda, H.Matsuoka, Y.Igura, S.Asai, IEDM Tech. Deg., 402, 1988 [17] S.Haddad, C.Chang, B.Swamlnathan, IEEE El. Dev. Lett., 10, 117, 1989 [18] L.Ravazzi, R.Bez, D.Cantarelli, P.Cappelletti, S.Serra, ESREF 90 Proc., 305 1990 [19] H.Kume, H.Yamamoto, T.Adachi, T.Hagiwara, K.Komori et al., IEDM Tech. Dig., 25.8,560, 1987 [20] G.Verma, N.Mielke, IEEE IRPS, 158, 1988 [21] E.Camerlenghi, P.Caprara, G.Crisenza, Solid State Dec., 177, 1988 [22] K.Yoshikawa, S.Mori, Y.Kaneko, Y Ohshima, N. Arai, E.Sakagami, IEDM Tech. Dig.,25.3.1,587, 1989 [23] K.Yoshikawa, S.Mori, Y.Kaneko, Y Ohshima, N. Arai, E.Sakagami, ESSDERC 90, 2C9, 170, 1990 [24] S.Keeney, R.Bez, L.Ravazzi, A.Mathewson, C.Lombardi, NVM Workshop, Monterey (CA), 1991 [25] M.Van Burskik, M.Holler, G.Korsh, B.Lee, S.Lee, Electronics, 89, 1983 [26] C.Bergonzoni, E.Cameflenghi, P.Caprazzi, ESSDERC 91, 1991 [27] G.Baccarani, M.Wordeman, R.H.Dennard, IEEE Trans. El. Dev.,31,452, 1984 [28] P.K.Chatterjee, W.R.Hunter, T.C.Halloway, Y.T.Lin,IEEE El. Dev. Lett., 1,220, 1980 [29] N.Mielke, IEEE IRPS, 106, 1983 [30] R.Shiner, J.Claywood, B.Euzent, IEEE IRPS, 238, 1980 [31] P.L.Hefley,J.W.McPherson, IEEE IRPS, 167, 1988 [32] C.Pan, K.Wu, P.Freiberger, A.Chatterjee, G.Sery, IEEE Trans. El. Dev., 37, 1439, 1990 [33] D.A.Baglee, L.Nannemann, C.Huang, IEEE IRPS, 12,1990 [34] G.Crisenza, G.Ghidini, S.Manzini, A.Modelli, M.Tosi, IEDM Tech. Dig., 5.5.1,107, 1990 [35] D.L.Crook, IEEE IRPS 1990,2,1990 [36] H.A.Schafft, D.A.Baglee, P.E.Kennedy, IEEE IRPS, 1,1990 [37] Y.Ohshima, S.Mori, Y.Kaneko, E.Sakagami, N.Arai, IEDM Tech. Dig., 5.2.1,95, 1990 [38] Y.Hisamune, N.Kodama, K.Saitoh, T.Okazawa, IEDM Tech. Dig.,25.2.1,583,1989 [39] N.Ajika, M.Ohi, H.Arima, T.Matzukawa, N.Tsubouchi,IEDM Tech. Dig., 5.7.1,115,1990 [40] A'Esqnivel'B'Riemenschaneider'J'Paters°n et aI.,IEDM Tech.Dig.,5.9,859,1987 [41] A.Mitchell, C.Huffman, A.Esquivel,IEDM Tech. Dig.,25.5,548,1987 [42] O.Bellezza, D.Lanrenzi, M.Melanotte, IEDM Tech.Dig.,25.1.1,579,1989 [43] B.J.Woo, T.C.Hong, A.Fazio, C.Park, G.Atwood, M.Holler, et al., IEDM Tech.Dig.,5.1.1,91,1990 [44] K. Yoshikawa, S.Mori, K.Narita, N.Arai, Y.Ohshima, Y.Kaneko, H.Araki, IEDM Tech.Dig.,432,1988 [45] S. All, B.Sani, A.Shubat, et aI.,IEEE SSC, vol. 23,1,1988