Non volatile memory reliability evaluation based on oxide defect generation rate during stress and retention test

Non volatile memory reliability evaluation based on oxide defect generation rate during stress and retention test

Solid-State Electronics 78 (2012) 151–155 Contents lists available at SciVerse ScienceDirect Solid-State Electronics journal homepage: www.elsevier...

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Solid-State Electronics 78 (2012) 151–155

Contents lists available at SciVerse ScienceDirect

Solid-State Electronics journal homepage: www.elsevier.com/locate/sse

Non volatile memory reliability evaluation based on oxide defect generation rate during stress and retention test H. Aziza b,⇑, J.M. Portal b, J. Plantier a,b, C. Reliaud a, A. Regnier a, J.L. Ogier a a b

IM2NP, Aix-Marseille University, 38, Rue Frédéric Joliot-Curie, 13451 Marseille, France ST-Microelectronics, ZI de Rousset, BP 2, F-13106 Rousset Cedex, France

a r t i c l e

i n f o

Article history: Available online 26 June 2012 The review of this paper was arranged by Prof. A. Zaslavsky Keywords: EEPROM SILC Reliability Oxide degradation Endurance and retention tests

a b s t r a c t This paper shows how floating gate (FG) memory cells behavior during retention tests can be predicted relying on static electrical stress tests. Retention tests are usually performed at High or Low Temperature Bake (HTB or LTB respectively) to provide warning of an impending failure of the memory cell capability to store data. Retention tests are very useful to screen out defective cell populations but induce significant test time overhead. To overcome this limitation, a correlation between stress time and retention time is established to anticipate retention test results. Moreover, further investigations are made to provide a physical explanation for the correlation. Indeed, it is shown that the same FG memory tunnel oxide traps are activated during electrical stress tests (high electric field) and retention tests (low electric field). Ó 2012 Elsevier Ltd. All rights reserved.

1. Introduction Reliability of EEPROM memory has grown with the understanding of memory cell failure mechanisms [1]. Two important parameters are used to evaluate EEPROM reliability: endurance and retention. Endurance defines the number of write/erase cycles an EEPROM can withstand before a memory bit fails. Retention is the length of time an EEPROM can reliably retain data. In the EEPROM industry-standard ‘‘Flotox’’, the charge transfer from the drain node to the floating gate node is due to Fowler–Nordheim tunneling [2]. The electric high-field induced during write/erase cycles is mainly responsible for the retention time degradation. It creates intrinsic failures or traps in the EEPROM tunnel oxide [3,4]. EEPROM retention degradation due to the tunnel oxide quality impacts directly the EEPROM threshold voltage (VT) distribution by creating extrinsic populations. Indeed, post cycling retention tests show a large tail of bits which are programmed faster than typical ones. Additionally, static and dynamic electrical stress tests are used to accelerate VT degradation of the weakest cells of the memory array. These tests are used to generate constant or variable electrical stresses throw the EEPROM tunnel oxide [5]. EEPROM reliability is highly dependent of the tunnel oxide quality and thickness. It has been observed that Fowler–Nordheim ⇑ Corresponding author. Address: IM2NP, Technopôle de Château-Gombert 38, Rue Frédéric Joliot-Curie, 13451 Marseille Cedex 20, France. Tel.: +33 491 054 784; fax: +33 491 054 782. E-mail address: [email protected] (H. Aziza). 0038-1101/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2012.05.069

tunneling injection through thin SiO2 oxide layers (5–10 nm) induces leakage currents called Stress-Induced Leakage Currents (SILCs) [6]. It is now generally accepted that this SILC is caused by inelastic Trap-Assisted Tunneling (TAT) transitions and that these traps are created by the electric high-field during the writing and erasing process [7]. Fig. 1 gives an illustration of a VT distribution obtained after a post cycling retention test (100 K write/erase cycles) for a programmed memory array (high VT values). Fig. 1a is a classical representation of the VT distribution (Gaussian curve). Fig. 1b is the cumulative representation of the same distribution in a logarithmic scale. This last representation allows evaluating more accurately marginal cell populations. Based on the particular shape of the cumulative distribution, different areas can be extracted. The area made of marginal cells is the main concern because it is responsible of the memory programming window closure (it can lead to an overlap between write and erase distributions). In this work, an experimental study based on a 0.18 lm EEPROM technology test chip (the cell area is 3.8 lm2 with a tunnel oxide ranging from 57 Å to 68 Å) is presented to show the correlation between retention tests and electrical stress tests. This correlation maintains that stress tests could potentially replace the standard Non-Volatile Memory (NVM) Low-Temperature Retention and Read Disturb (LTDR) test, which currently relies on 500 h storage at room temperature and requires a mathematical extrapolation of the bit error rate to 10 years [8]. Section 2 presents retention and stress tests experimental results. Section 3 focuses on correlation between stress and retention

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Fig. 3. Memory array VT distributions versus Control Gate voltage (VCG) after retention tests.

Fig. 1. Memory array VT distribution in linear (a) and logarithmic (b) scale.

tests. In Section 4, further investigations, based on an EEPROM model with SILC capabilities, reveal that the same oxide traps are responsible of low field leakage currents generated after retention tests and high field leakage currents generated after stress tests. Finally, Section 5 gives some concluding remarks. 2. Experimental results The EEPROM test chip used for this study is made of 38 bit memory words (32 bits word +6 ECC bits). The memory array is organized in 576 rows and 1216 bit lines. Main test chip characteristics are page programming and erasing in one cycle, internal high voltage generation and programming and erasing time lower than 2 ms. The experimental plan is presented in Fig. 2. After a 100 KCycles endurance test, retention and stress tests are performed while extracting VT distributions (‘‘Read’’ phase). Post cycling data retention tests consist of low temperature storage to examine the data stability of the memory array. Fig. 3 presents VT distributions extracted on an programmed memory array after 0, 24, 168, 500, 1000, 2000, 3000 and 6000 h, at room temperature. The first phase of the data retention degradation shows a fast shift rate of the VT distribution while the second phase presents a slow shift rate. VT distributions give information about tail bits. Tail bits are so called because they form a typical ‘‘tail’’ in the distribution; and on that account show anomalous cells populations. Static stress tests consist in constant electrical field stress to accelerate VT degradation of the weakest cells of the memory array. The electrical field value is controlled externally by biasing the drain node (drain stress) of each memory cell to stress the EEPROM tunnel oxide (the drain stress results in a floating gate voltage

Fig. 4. Memory array VT distributions versus Control Gate voltage (VCG) after static stress tests.

VFG  1.9 V and an electric field throw the tunnel oxide EOX  2.8 MV/cm). After a limited period of time, VT distributions are recorded. Fig. 4 presents VT distributions extracted every second within a period of time of 30 s, at room temperature. Post cycling stress induces VT distribution degradation. The resulting VT degradation curves exhibit the same shape as that obtained after retention tests for the same dies. 3. Electrical stress tests and retention tests correlation To compare stress and retention test results, stress tests obtained after 2–10 s and retention tests obtained from 168 h to 6000 h are considered for a same die. Moreover, as illustrated in Fig. 5, the study of marginal cell populations is restricted to tail bits located between 0.4 V and 0.8 V. This voltage window is representative of marginal populations and provides enough memory cells to perform a statistical study. In Fig. 5, DVT (VT (t)VT(t = 0)) is reported on the X-axis to focus on memory cells showing the most important VT shift (i.e. more impacted by leakage currents).

Retention Tests Endurance Tests

100Kcycles 700Kbits EEPROM test chip, 48 dies

0h+R, 168h+R, 500h+R, 1000h+R, 2000h+R, 3000h+R, 6000h+R R : Read phase, i.e. V T distribution extraction

Stress Tests

[email protected] + R, [email protected]+ R,……[email protected]+ R, [email protected] + R Fig. 2. Experimental plan.

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4. Results analysis and discussion In this section, the matching between oxide traps activated during retention tests and oxide traps activated during stress tests is highlighted based on the extraction of leakage currents from VT distributions. These currents are compared to simulated leakage currents provided by an EEPROM model with SILC capabilities, calibrated on silicon. Leakage currents extracted from measurements versus simulated leakage currents provide a physical explanation for the correlation between retention and stress tests. 4.1. EEPROM model with SILC capabilities

Fig. 5. Stress versus retention marginal population matching. Parts Per Million unit (PPM) is used to evaluate the marginal cell population evolution. DVT (VT (t)VT (t=0)) is reported on the X-axis for stress and retention.

The basic principle of TAT current, responsible of electron leakage is shown in Fig. 7a. Stress-induced leakage effects in NVM memories have been investigated in [9–11] where a statistical reliability model is proposed. In EEPROM memories (Flotox technology), a trap can be characterized by its spatial position Xnt, its energy level Ent and its capture cross-section rnt. Under the hypothesis of current mode using a single trap, the energy band diagram shows that an electron does not cross the tunnel oxide in a single step but through a defect, which is ideally located in the middle of the tunnel oxide. The statistical Shockley Read Hall approach is used to calculate the trap assisted current ITAT [4]. The current density JTAT, made of the catching and relaxing currents Jn1 and Jn2 is given by Eq. (2). In this equation NiT is the trap density, Qn the surface charge density, fn the impact frequency, fp the trap occupation function, Tr1 the transparency and Tox the tunnel oxide thickness.

J TAT ¼ J n1 ¼ J n2 ¼ Q n  fn  T r1 ðT ox ; Ent ; X nt Þ  rnt  NiT ð1  fp Þ

Fig. 6. Stress versus retention correlation function.

Based on this representation, Fig. 6 chart is plotted in order to find a correlation function between stress and retention tests. In this chart, each point is related to a common couple of ppm (parts per million) and DVT values, for stress and retention tests. These common values are extracted from Fig. 5 and correspond to an overlap between stress and retention curves for DVT varying from 0.4 V to 0.8 V. The correlation function between stress and retention tests is extrapolated with a good correlation factor equals to 0.986. The extrapolated function, presented in Eq. (1) exhibits à power law:

t ret ¼ a  tstressb

with a ¼ 147840 and b ¼ 2:170

ð1Þ

In this equation, a and b represent the parameters used to express stress time versus retention time, for a given technology and retention temperature. According to Eq. (1), a 10 s electrical stress test can be associated with a 2.19  107 s retention test (which represents a 6074 h retention test). Thus, retention reliability test results, which are time consuming, can be quickly predicted based on stress test results. This feature dramatically reduces reliability test time and can be very useful during a new process technology introduction where reliability estimation feedbacks are needed in a very short time, to adjust the fabrication process. As retention tests are achieved at room temperature (LTB) in this study, further investigation are planned to extract the evolution of a and b versus temperature and stress voltage.

ð2Þ

During reliability tests, JTAT current impacts directly the charge loss of EEPROM memory cells, resulting in a variation of EEPROM cells VT. This phenomenon was implemented in an EEPROM model [12] depicted in Fig. 7b. The main device of the model is based on a single MOS charge sheet model with two additional capacitors CPP and CTUN. These capacitors are used to model respectively the FG and the injection area of the EEPROM cell. The SILC mechanism is modeled by a Fowler–Nordheim current source coupled with a TAT current source. The model is able to extract the classical Fowler–Nordheim current density (JFN) and the SILC current density (JTAT) from VT degradation measurements (i.e. marginal cell populations) [12]. More precisely, from the marginal cell population VT evolution, the model is able to calculate the EEPROM floating gate charge and potential (QFG and VFG) using Eq. (3), where Cpp is the interpoly capacitance and VT0 the threshold voltage when QFG = 0.

Q FG ¼ C pp ðV T  V T0 Þ

ð3Þ

Then, by deriving the FG charge during the degradation time, an evaluation of the FG current density JFG is extracted. As JTAT and JFN contribute to the floating gate current density JFG, JFG is also function of the trap density parameter NiT, used to compute the JTAT current. 4.2. Electrical stress versus retention tests defects activation Retention test leakage currents (‘‘Measure Retention’’, after 100 KCycles) and stress test leakage currents (‘‘Measure stress’’, after 100 KCycles) are reported in Fig. 8. These currents are extracted from experimental VT distributions after retention and stress tests (presented in Fig. 3 and Fig. 4 respectively). One can notice that leakage currents generated after retention test measurements are associated with FG voltage values between 0 V and 1 V. Indeed, during retention tests, charge loss is observed under low tunnel oxide electric fields. Concerning stress tests, leakage

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(a)

(b)

IFN

I TAT

Fig. 7. TAT current parameters in the tunnel region (a) and EEPROM Model with SILC capabilities (b).

JFG(A/cm²)

Measure Stress

JFN + JTAT

Measure Retention

JFN

VFG(V)

Fig. 8. Electrical stress tests versus retention tests defect activation matching.

current measurements are obtained for high tunnel oxide electric fields with FG voltage values included between 4 V and 5.5 V. In the same figure, the evolution of the simulated FG current density JFG (JFN + JTAT) versus the FG voltage VFG is represented. JFG current curve can be obtained for any NiT parameter values thanks to an EEPROM model calibrated on the technology considered in this study. A good matching between the simulated FG current and leakage currents extracted from measurements is obtained for a single trap density parameter equals to 1.7  1016 /m2. Also, the same FG current curve is used to fit retention and stress tests leakage currents. This observation demonstrates that the electron migration trough the tunnel oxide is done for the same trap configuration (i.e. same trap density parameter NiT) under low and high fields. Therefore, electrical stress tests and retention tests activate the same oxide traps, generated after a 100 KCycles endurance test in this study. It is important to note that other trap parameters keep the same values as those obtained on large tunnel capacitances having the same characteristics as the EEPROM tunnel oxide (rn = 1  1015 cm2, Et = 2.6 eV, Xt = 0.5 ttun). Only NiT has to be extracted due to the traps averaging effect observed on large capacitance. 5. Conclusion In this study, a new technique is presented to quickly and accurately forecast the degradation of the EEPROM memory device

lifetime. With this technique, the correlation between marginal cell populations impacted by stress tests and marginal cell populations impacted by retention tests is clearly highlighted. Stress time versus retention time correlation is given by a simple mathematical function for an advanced EEPROM memory technology. From a physical point of view, it is demonstrated that the same tunnel oxide traps, generated after endurance tests, are the main contributors of low field leakage currents during retention test and high field leakage currents during electrical stress tests. Thus, this correlation establishes that two different reliability tests activate the same type of defects.

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